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ORCIDISVLSI 2025: Kalamata, Greece
- IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2025, Kalamata, Greece, July 6-9, 2025. IEEE 2025, ISBN 979-8-3315-3477-6
- Aimilios Leftheriotis, Ilias Papalamprou, Apostolos Garos, Georgios Gardikis, Maria Christopoulou, George Xilouris, Georgios Livanos, Nikolaos Papadakis, Dimosthenis Masouros, George Theodoridis, Dimitrios Soudris:
PRIVATEER: Secure FPGA Acceleration for 6G AI Edge Analytics. 1-6 - Paramdeep Singh, David C. Anastasiu:
Efficient Deployment of Very Wide and Very Deep Hypersparse FFNs on FPGA. 1-6 - Shruti Patkar, Harsh, Souraja Kundu, Gaurav Trivedi:
Accelerating Equation Solvers using Gauss-Jacobi on Multi-FPGA Systems with Ring NoC. 1-4 - Charanya K. Rao, Ashmitha Talluri, Ava Hedayatipour:
ASIC Design Flow Using Simulink and Cadence Digital IC Design Tools. 1-5 - Rajdeep Kumar Nath, Daniel Nguyen, Mohammad H. Behfar, Mari Rytky, Teemu Ahmaniemi, Johan Plomp:
AI-enabled Application Process Interface for On-device Personalized Blood Pressure Monitoring. 1-6 - Mahdi Benkhelifa, Hussam Amrouch:
SRAM Beyond FinFET: Performance and Aging Challenges in Nanosheet and CFET. 1-6 - Sruti Goswami, Ansuman Banerjee, Swarup Kumar Mohalik:
A Sampling-based Method for Output Safety Verification of Spiking Neural Networks. 1-6 - Satyam Shubham, Sutirtha Bhattacharyya
, Ansuman Banerjee, Raj Kumar Gajavelly:
New Branching Heuristics for Incremental Bounded Model Checking. 1-6 - Maryam Esmaeilian, Louis Morge-Rollet, David Hély, Elena-Ioana Vatajelu, Romain Siragusa:
A PUF-Enhanced Ring Oscillator-Based Authentication System for IoT Devices. 1-6 - Shuhang Zhang, Bryan Olmos, Wolfgang Kunz, Djones Lettnin:
Synthesis-Aware Area Optimization for Safety Registers in Automotive SoCs. 1-6 - Ravi S. Siddanath, Mohit Gupta, R. Dhirendra Rao, Souvik Kumar Das, Raghavendra Manjunath Hegde, Prasanna Kumar Misra, Manish Goswami, Kavindra Kandpal:
High-Precision BGR Design with Advanced Curvature Compensation & Optimized Layout in 28 nm CMOS Technology. 1-6 - Charles Gouert, Nektarios Georgios Tsoutsos:
PolyFHEmus: Rethinking Multiplication in Fully Homomorphic Encryption. 1-6 - Haoran Pan, Bohang Xiong, Jing Tian, Shikun Zhang, Hao Zhu, Zhongfeng Wang:
High-Performance FPGA-Based Accelerator of L-BFGS for 3D Face Reconstruction. 1-6 - Felix Zilk, Alessandro Tundo, Vincenzo De Maio, Ivona Brandic:
Breaking Down Quantum Compilation: Profiling and Identifying Costly Passes. 1-6 - Jaeha Lee, Woonseon Cheon, Yunseok Noh, Huijae Lim, Subin Jin, Shinwoo Kim, Hayoung Kim, Sanghoon Baek:
Boundary-Power Overlapped Design for Sub-3nm Standard Cell Placement. 1-6 - Deniz Najafi, Mehrdad Morsali, Hamza Errahmouni Barkam, Brendan Reidy, Sepehr Tabrizchi, Arman Roohi, Mahdi Nikdast, Ramtin Zand, Mohsen Imani, Shaahin Angizi:
From Pixels to Reasoning: A Cross-Layer Photonic Design for Edge Visual Intelligence. 1-6 - Mahdi Shamsa, Laavanya Rachakonda, Saraju P. Mohanty, Elias Kougianos:
VegeCare: An IoT Framework To Monitor and Maintain Vegetable Quality. 1-6 - Theodoros Papavasileiou, Georgios Keramidas, Vasilis F. Pavlidis:
Tournament Cache Decay: Tight Control of Leakage Power for Last-Level Caches. 1-6 - Iuliia Topko, Alexey Serdyuk, Tanja Harbaum, Jürgen Becker:
Hardware-Accelerated On-Device Learning: Training, Partitioning, and Compilation for Constrained Edge AI. 1-6 - Zhe Zhang, Sani R. Nassif, Mehdi B. Tahoori:
ChatTCAD: Leveraging Large Language Models for Automated TCAD Simulation File Generation. 1-6 - Charanya K. Rao, Ravi Monani, Ava Hedayatipour:
Digital IC Design of a 45nm CMOS Chua Encryption Architecture for Resource Limited Devices. 1-6 - Panagiotis Chaidos, Alexios Maras, Georgios Alexandris, Xiaoling, Asmae El Arrassi, Bas Ahn, James D. Garside, Yunhao Deng, Theofilos Spyrou, Anteneh Gebregiorgis, Mottaqiallah Taouil, Manil Dev Gomony, Sotirios Xydis, Marian Verhelst, Said Hamdioui, Dimitrios Soudris, Henk Corporaal:
Flexible Hardware Accelerators for Ultra-Low Power Edge AI: The CONVOLVE Approach. 1-6 - Hyunyoung Yoo, Muhammad Fakhri Mauludin, Yeonsu Kim, Su-Hyeon Kim, Eun-Ji Yoo, Jae-Yun Park, Jusung Kim, Jae-Won Nam:
MASH Digital Delta-Sigma Modulators for the CMOS Qubit Controller. 1-2 - Arnav Ramamoorthy, Kiran K. Gunnam:
Adaptive Multi-Precision Inference for Large-Scale AI Using IEEE P3109 FP8. 1-2 - Ahsan Rafiq, Alberto Bosio, Salvatore Pappalardo, Maksim Jenihhin:
AxEnMULT: Design of an Efficient and Reliable Approximate Encoding-Based Multiplier. 1-6 - Ardhendu Sarkar, Sriparna Mandal, Surajeet Ghosh:
Scalable and Power-Efficient Merging Network Design: Automatic RTL Generation for FPGA. 1-6 - Tarun Sharma, Deepank Grover, Sujay Deb:
A Secure and Sustainable RISC-V Processor with Intrinsic PUF for Edge AI. 1-6 - Mahdi Nikdast:
Advancing Edge Analog Processing with Photonic In-Memory Computing. 1 - Krishnendu Guha:
TiAS: Time Aware Split Computing to Secure AI/ML Workloads for FPGA based Edge Platforms against Unintentional Delays. 1-6 - Hsiang-Cheng Hsieh, ShengPo Lin, Arbind Kumar Mahto, Kuei-Chung Chang, Juin-Ming Lu, Tay-Jyi Lin, Tien-Fu Chen:
Hybrid Bayesian Optimization with Early Termination Strategies for Auto Tuning. 1-6 - José Cubero-Cascante, Rebecca Pelke, Noah Flohr, Arunkumar Vaidyanathan, Rainer Leupers, Jan Moritz Joseph:
Evaluating the Scalability of Binary and Ternary CNN Workloads on RRAM-based Compute-in-Memory Accelerators. 1-6 - Christoforos Vasilakis, Alexandros Tsagkaropoulos, Angelos Motsios, Dionysios I. Reisis:
Autonomously Reconfigurable Telemetry and Monitoring System for CubeSats. 1-5 - Xinpeng Li, Ji Liu, Jeffrey M. Larson, Shuai Xu, Sundararaja Sitharama Iyengar, Paul D. Hovland, Vipin Chaudhary:
State Dependent Optimization with Quantum Circuit Cutting. 1-6 - Md. Saif Hassan Onim, Travis S. Humble, Himanshu Thapliyal:
Emotion Recognition in Older Adults with Quantum Machine Learning and Wearable Sensors. 1-6 - Neha Gupta, Lomash Chandra Acharya, Mahipal Dargupally, Khoirom Johnson Singh, Amit Kumar Behera, Johan Euphrosine, Sudeb Dasgupta, Anand Bulusu:
Aging Model Development for ASAP 7 nm Predictive PDK: Application in Aging-Aware Performance Prediction of Digital Logic and ADCs in Data Acquisition System. 1-4 - Sascha Neske, Bryan Olmos, Shuhang Zhang, Martin Kröning, Stefan Lankes, Wolfgang Kunz, Djones Lettnin:
HW/SW Formal Co-Verification of Rust-based Designs Using Hardware Abstraction Model. 1-6 - Hafizur Rahaman, Chandan Giri, Surajit Kumar Roy, Amlan Chakrabarti:
Optimization and Security of AI Models for Deployment at Edge: A Comprehensive Review. 1-6 - Cheena Singhal, Sparsh Mittal:
A 6T SRAM based reconfigurable in-memory XOR/XNOR and accumulation architecture. 1-6 - Constantinos Efstathiou, John Liaperdos, Yiorgos Tsiatouhas:
Efficient Tree Architecture for the Design of Static CMOS Magnitude Comparators. 1-6 - Georgios Papaspyropoulos, Evanthia Faliagka, Theodoros Skandamis, Christos P. Antonopoulos, Nikos S. Voros:
Real-time Padel Strokes Classification. 1-4 - Sebastian Fischer, Nithya Raj, Alberto García-Ortiz:
gem5-SysXelerator: A Full-System Simulator for Accelerator Architectures. 1-6 - Shruti Pandey, Aneeket Yadav, Smruti R. Sarangi:
AnaIR: A Semi-Analytical Green's Function Inspired Neural Network for Static IR Drop Prediction. 1-6 - Leon Li, Alex Orailoglu:
Boosting Scan Chain Security in a White-box through Restricted Pattern Filtering. 1-6 - Ali Azarpeyvand, Mohammad Eslami, Gert Jervan, Jaan Raik, Tara Ghasempouri:
SynAssert: Automated Synthesis of CSCA Leakage Patterns into Cost-Effective Security Assertions. 1-6 - Batuhan Hangün, Emine Akpinar, Oguz Altun, Önder Eyecioglu:
Comparative Analysis of QNN Architectures for Wind Power Prediction: Feature Maps and Ansatz Configurations. 1-6 - Milad Kokhazadeh, Georgios Keramidas, Vasilios I. Kelefouras:
Joint Compression Strategies for CNNs: A Case Study on Low Rank Factorization, Filter-based Pruning and Unstructured Pruning. 1-6 - Omkar Kokane, Gopal Raut, Salim Ullah, Mukul Lokhande, Adam Teman, Akash Kumar, Santosh Kumar Vishvakarma:
Retrospective: A CORDIC Based Configurable Activation Function for NN Applications. 1-6 - Andrew Nash, Dirk Pesch, Krishnendu Guha:
Distributed Classification with Dynamic Communication for Air Quality Sensing. 1-6 - Nivedita Shrivastava, Smruti R. Sarangi:
A Theoretical Framework For Modeling Cache-based Side-Channel Attacks and Countermeasures. 1-6 - Meng-Syuan Li, Jung-Fang Ke, En-Ming Huang, Zhi-Wei Liu, Yu-Guang Chen, Chun-Yi Lee:
CIM for Transformer Models: Enhancing Large Language Model Inference Efficiency. 1-6 - Ioannis T. Rekanos, Evanthia Faliagka, Michael Paraskevas, Vaggelis Kapoulas, Christos P. Antonopoulos, Nikos S. Voros:
Motion Detection over 5G through Sensing Signal Disturbance Analysis leveraging COTS platform. 1-6 - Angelos S. Voros, Evanthia Faliagka, Alexandros Spournias, Christos P. Antonopoulos, Nikos S. Voros:
A Novel Firmware Architecture leveraging Race to Sleep paradigm for Ultra-Low-Power CPS. 1-4 - Priyanka Agarwal, Pruthvi Parate, Madhav Rao:
FF-GFA: Flipped Folded Architecture enabled Power- and Area-Efficient Gabor Filter Design. 1-6 - Sai Mahesh Mudavat, Alakananda Mitra, Saraju P. Mohanty, Elias Kougianos:
LiteViT: Leveraging the Power of Transformers for Edge AI in Crop Disease Classification. 1-6 - Lorenzo Pfeifer, Rainer Leupers, Jan Moritz Joseph:
EXAMINER: IP Extraction Algorithm from MAGIC Logic-in-Memory. 1-6 - Yassin Atwa, Süleyman Savas:
FPGA Implementation of a Fixed-Point Arctangent Function Using Harmonized Parabolic Synthesis. 1-5 - Mohamed Watfa, Alberto García Ortiz, Gilles Sassatelli:
Designing Compatible Analog Circuits for Equilibrium Propagation: Implementations Using The Adjoint Method and Reciprocity Principles. 1-6 - Cheng-You Tsai, Hung-Yu Tseng, Po-Yen Chang, Yi-Chang Lu:
Energy-Efficient Basecalling for ONT Long Reads on a Hybrid ASIC-GPU Platform. 1-6 - Giovanni Agosta, Stefano Cherubin, Derek Christ, Francesco Conti, Asbjørn Djupdal, Matthias Jung, Georgios Keramidas, Roberto Passerone, Paolo Rech, Elisa Ricci, Philippe Velha, Flavio Vella, Kasim Sinan Yildirim, Nils Wilbert:
Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project. 1-6 - Panagiotis Mousouliotis, Georgios Keramidas:
A Parameterizable Convolution Accelerator for Embedded Deep Learning Applications. 1-6 - Durba Chatterjee, Debdeep Mukhopadhyay, Aritra Hazra:
MADel0: A Modelling and Assessment Framework for Delay PUFs leveraging Gradient-based Optimization Techniques. 1-7 - Alperen Bolat, Sakir Sezer, Kieran McLaughlin, Henry Hui:
Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V. 1-6 - Evanthia Faliagka, George Tefas, Christos P. Antonopoulos, Nikos S. Voros:
Real-Time Person Recognition Using MoveNet for Pose-Based Identification. 1-4 - Hao-Yu Lu, Yu-Ting Kao, Yeong-Jar Chang, Jason Gemsun Young, Darsen D. Lu:
Quantum-Chiplet: A VLSI-Like Methodology for Hierarchical Quantum Design and Verification. 1-5 - Venkata P. Yanambaka, Jian Zhang, Jonathan Gratch, Kahlan Edwards:
PUF-ML: Machine Learning - Based Physical Unclonable Functions For Cost Effective Integration In Smart Healthcare. 1-6 - Marcelo K. Moori, Arthur Francisco Lorenzon, Hiago Mayk G. de A. Rocha, Antonio Carlos S. Beck:
GAAMP: Automatic Thread Count/Affinity and DVFS Tuning for Asymmetric Multicores. 1-6 - Luigi Ghionda, Riccardo Tedeschi, Yvan Tortorella, Arpan Suravi Prasad, Davide Rossi, Luca Benini, Francesco Conti:
HMR-NEureka: Hybrid Modular Redundancy DNN Acceleration in Heterogeneous RISC-V SoCs. 1-6 - Matthias Nickel, Lester Kalms, Julian Haase, Jieyu Zhao, Diana Göhringer:
Hardware-Optimized RNN Detection for Insertion/Deletion Channels in Wireless Communication. 1-6 - Giacomo Orlandi, Christian Conti, Marco Vacca, Mariagrazia Graziano, Fabrizio Riente:
Enabling fully connected probabilistic computing through a fast pipelined multi-operand adder. 1-6 - Ava Hedayatipour, Pouya Motakef:
Accelerating Layout Automation Using AI-Driven Smart Routing for Custom Circuit Design. 1-2 - Parisa Amiri-Eliasi, Silvia Mella, Lejla Batina:
Assessing Gaston: Side-channel Security and Hardware Cost Comparison with Ascon-p. 1-6 - Biswadeep Chatterjee, Swagata Mandal, Amlan Chakrabarti, Sayan Chatterjee:
A Novel Architecture using Dynamic Computing Nodes to Improve Multi-Access Edge Cluster Productivity. 1-6 - Mahieddine Anouar Hadjadj, Redouane Kaibou, Said Sadoudi:
Design and Hardware Implementation of a PRNG-CS for Embedded Security Applications. 1-4 - Constantinos Efstathiou, Ioannis Kouretas, Paris Kitsos:
Efficient Majority Logic Modulo 2n-1 Adder Design. 1-6 - Spyros Chalkias, Anastasis Avgoustidis, Thomas Noulis, Georgios Keramidas, Vasilis F. Pavlidis:
Parametric RISC-V Compliant Floating-Point Arithmetic and Conversion Circuits. 1-6 - Subhradip Chakraborty, Kapish Singh, Ankur Singh, Zihan Yin, Akhilesh Jaiswal:
Application Specific Hardware-Algorithm Metric Analysis for Vision based In-Sensor Computing. 1-6 - Ioannis Rizos, Georgios Papatheodorou, Aristides Efthymiou:
Tunable Approximate Booth Multiplier. 1-6 - Elena Ferrero, Federico Ravera, Roberto Listo, Yuri Ardesi, Gianluca Piccinini, Mariagrazia Graziano:
Technology and Power-aware Investigation of Nanostructures for Molecular Field-Coupled Nanocomputing. 1-6 - Shion Samadder Chaudhury, Sudhindu Bikash Mandal, Turbasu Chatterjee, Arnav Das, Amlan Chakrabarti:
Quantum Circuit Synthesis of an Approximate Hybrid Kolmogorov-Arnold Network. 1-6 - Heba Khdr, Mohammed Bakr Sikal, Benedikt Dietrich, Jörg Henkel:
Towards the Optimization of Hardware Efficiency through Machine Learning. 1-6 - Abhoy Kole, Mohammed E. Djeridane, Arighna Deb, Kamalika Datta, Indranil Sengupta, Rolf Drechsler:
Unlocking the Benefits of Dynamic Quantum Circuits in Resource Constraint Architecture. 1-6 - Shu Zhao, Ajay Narayanan Sridhar, Harland M. Patch, Vijaykrishnan Narayanan:
InsectAgent: Improving Insect Recognition through Dynamic Information Augmentation with Multimodal Large Language Models. 1-6 - Xiaoxu Peng, Tu Anh Ngo, Farrel Koh, Anupam Chattopadhyay:
Watermarking Edge Neural Network for Object Detection. 1-6 - Alessandro Varaldi, Alessio Naclerio, Fabrizio Riente, Maurizio Zamboni, Mariagrazia Graziano, Marco Vacca:
Optimizing TCN Inference: A Hardware-Software Co-Design Approach with CGRA Acceleration. 1-6 - Dimitrios Vamvakidis, Christos Georgakidis, Aikaterini Tsilingiri, Nikolaos Sketopoulos, Christos P. Sotiriou, Vasilis F. Pavlidis:
3DPlace: Timing-driven Detailed Placement for Monolithic 3D ICs. 1-6 - Dimitrios C. Tzarouchis, Evangelos Pikasis, Elias D. Tsirbas, Eleftherios C. Loghis, Sotirios Aloimonos, Vassilis Koratzinos, Dimitrios Bastas, Dimitrios Kritharidis, José Luis González-Jiménez, Antonio Clemente, Francesco Foglia Manzillo, Alexandre Siligaris, Sean Ahearne, Thomas Merkle:
Towards Future 6G Telecommunications: Research at the THz Domain in Intracom Telecom. 1-4 - Sian Lun Lau, Saad Aslam, Amlan Chakrabarti, Jari Porras:
Sustainable AI in the Cloud-to-Thing Continuum: A Bibliometric Review on Lightweight, Small-Sample, and Federated Learning Approaches. 1-6 - Devon Lister, Prabhu Vellaisamy, John Paul Shen, Di Wu:
Catwalk: Unary Top-K for Efficient Ramp-No-Leak Neuron Design for Temporal Neural Networks. 1-6 - Zhixin Pan, Ziyu Shu, Xinrui Yu:
SAGE: Shapley Attention Graph nEtwork for Gate-level Trojan Detection and Localization. 1-6 - Hendrik Borchert, Karthik KrishneGowda, Milos Krstic:
Ultra-Low-Latency Data Link Layer TX Buffer Architecture for Wireless Communications. 1-6 - Laavanya Rachakonda, Samuel Stasiewicz:
SanaSolo 3.0: A Low-Ground, IoT-Based Rover for In-Situ Soil Fertility Monitoring. 1-6 - Abhinaba Chakraborty, Ansuman Banerjee, Vinay B. Y. Kumar, Arindam Mallik:
On-the-fly Validation of Hierarchical Cache Coherence Protocols using Directed Testing. 1-6 - Sepideh Kheirollahi, Sinatra Babele Khanshan, Zainalabedin Navabi:
A Quasi Fat Tree-based Formation of Micro-Programmable Processing Elements for Machine Learning Applications. 1-4 - Adriano Lopes Pata, Nithya Raj, Alberto García-Ortiz:
Configurable Hardware Module for Low-Power Coding in Heterogeneous-Monolithic 3D NoC Links. 1-6 - Asier Gambra, Unai Rioja, Durba Chatterjee, Igor Armendariz, Lejla Batina:
Machine Learning Fault Injection Detection in Clock Signals: An Analysis of Frequency Impact. 1-6 - Laia Domingo, Christine Johnson:
Quantum-enhanced optimization for patient stratification in clinical trials. 1 - Zahra Kokhazad, Milad Kokhazadeh, Georgios Keramidas, Vasilios I. Kelefouras:
Leveraging Low-Rank Factorization for Compressing DNN Speech Enhancement Models. 1-5 - Vasileios Titopoulos, George Alexakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
Efficient Implementation of RISC-V Vector Permutation Instructions. 1-6 - Arpan Suravi Prasad, Gamze Islamoglu, Luca Bertaccini, Davide Rossi, Francesco Conti, Luca Benini:
PACE: An Optimal Piecewise Polynomial Approximation Unit for Flexible and Efficient Transformer Non-linearity Acceleration. 1-6 - Shuhang Zhang:
Efficient Logic Evaluation Using RRAM-Based In-Memory Computing. 1-6 - Ahmad Houraniah, H. Fatih Ugurdag, Cengiz Emre Dedeagac:
Efficient Multi-Cycle Folded Integer Multipliers. 1-6 - Polykarpos Vergos, Theofanis Vergos, Florentia Afentaki, Konstantinos Balaskas, Georgios Zervakis:
Support Vector Machines Classification on Bendable RISC-V. 1-6 - Gunjan Dhanuka, Syam Sankar, John Jose:
Dynamic Mitigation of Hardware Trojan Induced Black Hole Router Attack in Network-on-Chip. 1-6 - Alessandra Dolmeta, Valeria Piscopo, Maurizio Martina, Guido Masera:
CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON. 1-6 - Mrunal Shende, Bodhisatwa Mazumdar:
Towards Improving Performance Metrics of Minority Majority Inverter Graph (mMIG) Circuits. 1-6 - Spyros Lavdas, Zafeiropoulos Konstantinos, Ktenas Athanasios, Constantinos B. Papadias:
EGaIn-Based Liquid Antennas: Beam Steering and Frequency Reconfiguration Using Microfluidic Control. 1-6 - Subhajit Paul, Ansuman Banerjee, Sumana Ghosh, Sudhakar Surendran, Raj Kumar Gajavelly:
LISA: LLM Informed Systemverilog Assertion generation with RAG and Chain-of-Thought. 1-6 - Tongyang Xu, Christos Masouros, Izzat Darwazeh:
Reliable, Secure, and Spectrally Efficient ISAC using Distributed Multiuser MIMO and Non-Orthogonal Waveform. 1-6 - Seyed Ahmad Mirsalari, Marco Fariselli, Léo Bijar, Francesco Paci, Luca Benini, Giuseppe Tagliavini:
Enabling Real-Time Streaming Temporal Convolution Network Inference on Ultra-Low-Power Microcontrollers. 1-6 - Changfu He, Xinle Jia, Yuxing Chen, Wenli Xu, Suwen Song, Zhongfeng Wang:
A Low-Complexity XOR-Based BCH Decoder for PAM4 Modulation Systems. 1-6 - Dimitris Bakalis, Haridimos T. Vergos:
Efficient modulo 2n-4 arithmetic units. 1-5 - Nima Kavand, Armin Darjani, Tushar Niranjan, Akash Kumar:
RAT: RFET-based Analog Hardware Trojan. 1-6 - Jiashuo Zhang, Hongge Li, Xinyu Zhu, Yinjie Song, Yumeng Liu:
Approximate Redundant Booth Multiplier Based on Error Compensation Mechanism. 1-6 - Sounak Bhowmik, Travis S. Humble, Himanshu Thapliyal:
Quantum Properties Trojans (QuPTs) for Attacking Quantum Neural Networks. 1-6 - Riadul Islam, Joey Mulé, Dhandeep Challagundla, Shahmir Rizvi, Sean Carson:
An Event Autoencoder for High-Speed Vision Sensing. 1-6 - Yiyu Wang, Vasilis F. Pavlidis, Rui Wang, Yuanqing Cheng:
PV-Clock: Process Variation-Aware 3D Clock Network Synthesis for Robust and Power-Efficient Timing Optimization. 1-6 - Sahar Moradi Cherati, Leonel Sousa:
MSDF-Based Hardware Accelerators for Energy-Efficient Neural Networks in Edge Computing Applications. 1-4 - P. S. Rajeswari Suance, Ruchika Gupta, Maurizio Palesi, John Jose:
Decentralized Framework for Teleportation in Quantum Core Interconnects. 1-6 - Ravish Kumar Raj, Arun Kumar, Yasser Rezaeiyan, Pernille Klarskov, Farshad Moradi, Sonal Shreya:
Analytical Approach to Engineer Strain-Gradient for Magnetic Skyrmion-based LeakyIntegrate and Fire Neuronal Dynamics. 1-6 - Aotao Wang, Haikuo Shao, Shaobo Ma, Zhongfeng Wang:
FastMamba: A High-Speed and Efficient Mamba Accelerator on FPGA with Accurate Quantization. 1-6 - Chi Zhang, Luca Colagrande, Renzo Andri, Thomas Benz, Gamze Islamoglu, Alessandro Nadalini, Francesco Conti, Yawei Li, Luca Benini:
FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators. 1-6 - Armin Darjani, Nima Kavand, Akash Kumar:
Flip-UnLock: An Anomaly Detection Attack on Flip-Flop-Based Logic Locking. 1-6 - Filippo Marostica, Alessio Carpegna, Alessandro Savino, Stefano Di Carlo:
Energy-Efficient Digital Design: A Comparative Study of Event-Driven and Clock-Driven Spiking Neurons. 1-6 - Indira Devi Siripurapu, Alakananda Mitra, Saraju P. Mohanty, Elias Kougianos:
iLog 3.0: Estimating Food Volume from 2D Images Using Mask R-CNN and Monocular Depth Estimation. 1-6 - Collin Beaudoin, Swaroop Ghosh:
Q-Fusion: Diffusing Quantum Circuits. 1-6 - Patroklos Pazionis, Andreas Tsimpos, Gerasimos Theodoratos, Georgios Panagopoulos:
A 4.8ps Resolution, PVT-insensitive Vernier-based TDC using switched-RO PLL and Back Gate Calibration. 1-6 - Konstantinos Nikellis, Garth Sundberg, Yiannis Moisiadis, Stefanos Stefanou:
RaptorQu: Electromagnetic Modeling of Superconductors. 1-6 - Subrata Das, Swaroop Ghosh:
Optimization of Quantum Error Correcting Code under Temporal Variation of Qubit Quality. 1-6 - Aikaterini Maria Panteleaki, Varatheepan Paramanayakam, Vasileios Pentsos, Andreas Karatzas, Spyros Tragoudas, Iraklis Anagnostopoulos:
A Vertical Approach to Designing and Managing Sustainable Heterogeneous Edge Data Centers. 1-6 - Verjina Torosian Khouygani, Shahnam Mirzaei, Christian Beck, Debi Prasad Choudhary:
Accelerating Solar Spectra Analysis:A High-Performance FPGA Framework with Parameterized Filters. 1-6 - Zanhe Qi, Kouki Hirono, David Clarino, Shigeru Yamashita:
A Decomposition Method for MCT Gates Considering T-depth of Each Qubit. 1-6 - Matteo Farronato, Piergiulio Mannocci, Alessandro Milozzi, Christian Monzio Compagnoni, Daniele Ielmini:
Bio-Inspired Computing with Emerging Devices: Bridging 2D Materials and Neuromorphic Architectures. 1 - Himanshu Rai, Sasi Snigdha Yadavalli, Aishwarya Sridhar, Nanditha Rao:
VFMA: Scalable Floating-Point Accelerator for Vector FMA on FPGAs. 1-6 - Ayisat Adedokun, Yerzhan Mustafa, Selçuk Köse:
Bistable All-Josephson Junction SQUID with Dual Φ-Junctions for State-Controlled Superconducting Circuits. 1-6 - Dixit Dutt Bohra, Dip Sankar Banerjee, Somitra Sanadhya:
Sparse-Aware NTT: Accelerating Lattice-Based Cryptography on FPGAs. 1-6 - Chengwei Zhou, Gourav Datta:
Invited: A Hardware-Algorithm Vision for In-Sensor Intelligence. 1-2 - Keyvan Shahin, Michael Hübner, Christian Herglotz:
A Width-Configurable Hardware Approach for Accelerating Fixed-Point Simulation. 1-6 - Jingcun Wang, Mengnan Jiang, Grace Li Zhang:
Efficient Neural Network Compression for Fast Inference on Hardware. 1-2 - Xuke Yan, Linxi Zhang:
A Multi-Scale Lightweight 1D-CNN for Efficient CAN Intrusion Detection. 1-6 - Tianheng Ling, Chao Qian, Lukas Johannes Haßler, Gregor Schiele:
Automating Versatile Time-Series Analysis with Tiny Transformers on Embedded FPGAs. 1-6 - Sonam Sharma, Dipanjan Roy, Digambar Pawar:
HardObfSec: Measuring Hardware Obfuscation Security at RTL. 1-6 - Aikaterini Maria Panteleaki, Konstantinos Balaskas, Georgios Zervakis, Hussam Amrouch, Iraklis Anagnostopoulos:
Carbon-Efficient 3D DNN Acceleration: Optimizing Performance and Sustainability. 1-6 - Deepali Garg, Lawrence T. Pileggi:
Universal Topological Arrays: An Efficient Solution for Provably Secure Hardware. 1-6 - Caio Vieira, Jerónimo Castrillón, Antonio Carlos Schneider Beck:
TQHD: Thermometer Encoding Based Quantization for Hyperdimensional Computing. 1-6 - Simone Machetti, Pasquale Davide Schiavone, Giovanni Ansaloni, Miguel Peón-Quirós, David Atienza:
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications. 1-6 - Jannis Schönleber, Lukas Cavigelli, Matteo Perotti, Luca Benini, Renzo Andri:
Stella Nera: A Differentiable Maddness-Based Hardware Accelerator for Efficient Approximate Matrix Multiplication. 1-6 - Shamiul Alam, Kazi Asifuzzaman, Ahmedullah Aziz:
UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM. 1-6 - Fanny Spagnolo, Stefania Perri, Pasquale Corsonello:
Approximate Swish Activation Function for Low-Energy Yet Low-Error VLSI Implementations. 1-5 - Katayoon Basharkhah, Zahra Hojati, Zainalabedin Navabi:
An Event-Based Gate-Level Framework for Power Side-Channel Leakage Assessment. 1-6 - Quansen Wang, Vasilis F. Pavlidis, Xuning Feng, Rui Wang, Wei Zhang, Yuanqing Cheng:
Inductive Effect-Aware Power Distribution Network Modeling and Analysis for Heterogeneous 3D Integrated Circuits. 1-6 - Kosmas Alexandridis, Vasileios Titopoulos, Giorgos Dimitrakopoulos:
Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware Operators. 1-6 - Pruthvi Parate, Daksh Sharma, Alwin Shaju, Madhav Rao:
Hierarchical Optimization of Karatsuba Multipliers for ECDSA Hardware Accelerators. 1-6 - Michalis Piponidis, Georgios Konstantinidis, Maria K. Michael, Theocharis Theocharides:
Dynamic Early-Exit Convolutional Neural Networks for Edge Vision: The Benefits, The Challenges, and the Road Ahead. 1-6 - Amirreza Yousefzadeh, Sameed Sohail, Ana Lucia Varbanescu:
Memory Wall is not gone: A Critical Outlook on Memory Architecture in Digital Neuromorphic Computing. 1-4 - Abhishek Yadav, Ayush Dixit, Utsav Jana, Masahiro Fujita, Binod Kumar:
Resource-Efficient LSTM Architecture for Keyword Spotting with CORDIC-Activation Approximation. 1-6 - Emine Akpinar, Batuhan Hangün, Murat Oduncuoglu, Oguz Altun, Önder Eyecioglu, Zeynel Yalcin:
Quantum-Enhanced Classification of Brain Tumors Using DNA Microarray Gene Expression Profiles. 1-6 - Ian Kersz, Arthur F. Ely, Pedro Alles, Michael G. Jordan, José Rodrigo Azambuja, Fernanda L. Kastensmidt, Antonio Carlos S. Beck:
HEDGY: Heterogeneous Design Management for Multi-Tenant Multi-FPGA Edge Systems. 1-6 - Koustubh Phalak, Junde Li, Swaroop Ghosh:
Dataset Distillation for Quantum Neural Networks. 1-5 - Andreas-Efstathios Eleftheriadis, Thomas Noulis, Georgios Keramidas, Vasilis F. Pavlidis:
Enhancing Performance of Floating Point Units Using Parallel Prefix Adders. 1-6
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