RISC-V: The AI-Native Platform for the Next Trillion Dollars of Compute

Ahead of AI Infra Summit 2025, the RISC-V AI Market Development Committee explores how companies across industries are proving the viability of RISC-V as a native architecture for modern AI workloads, from edge AI to powerful transformer models.

By Makeljana Shkurti, chair of the RISC-V AI Market Development Committee, with invaluable input from fellow committee members

The unstoppable ascendance of artificial intelligence (AI) across every field and industry is being driven by multiple symbiotic factors. On a technological level, an explosion in available data generated by digital and connected processes has provided firm foundations upon which AI can train and infer outcomes. Simultaneously, advances in processor and accelerator hardware, coupled with the availability of AI-ready software platforms and tools, have supplied the performance needed to tackle data-intensive workloads. The AI boom has, in itself, fostered an environment in which both private sector enterprises and governmental bodies are eager to participate. As a result, it has inspired an influx of investment, further accelerating growth.

This growth is not just about more data and more compute—it is about navigating trade-offs between cost, speed, and sustainability. AI Infra Summit 2025 emphasizes full-stack optimization for inference speed, power efficiency at every layer, and balancing innovation with sustainability. All fundamental aspects of a successful AI future.

The unprecedented push for AI has had an equal impact on the need to implement AI-capable compute solutions. According to Omdia, the global AI processor market is valued at $261.4bn in 2025 and is expected to grow, at a compound annual growth rate (CAGR) of 8.1% to $385.4bn by 2030.

Vitally, while hardware constitutes approximately 70% of the whole market revenue, the software component is growing fast, highlighting the strategic importance of deployment‑ready stacks and robust ecosystems.

Modern AI spans wildly different workloads, from battery-powered sensor algorithms and edge smart vision to datacenter-scale inference and autonomous systems in space. Many of these workloads (in particular, the training of large-scale AI models) are stretching conventional architectures to their limits.

Traditional, closed architectures may excel at general-purpose compute, but their fixed instruction set architectures (ISAs) and licensing models limit any deep, workload-specific customization. Despite their maturity, general-purpose processors often lack the specific AI workload capabilities required to optimize for inference latency, energy efficiency, real-time processes, or model specialization. Achieving these capabilities generally requires the addition of neural processing units (NPUs) and other such parallel compute hardware to be retrofitted.

Now, as AI infrastructure spending races toward $400 billion annually, the need for AI-native hardware designed for full-stack optimization and power efficiency at every layer is growing ever more urgent. By ‘AI-native’, we refer to customizable, efficient, and scalable systems designed from the ground up to deliver AI as a fundamental component (rather than an afterthought).

RISC-V: An AI-native Instruction Set Architecture (ISA)

The debate around custom vs general compute is a key theme at this year’s AI Infra Summit 2025, and there’s no guessing which side RISC-V is on. As an open and highly flexible ecosystem that offers both standardization and customization, the open standard offers hardware developers the level of silicon freedom they need to build highly targeted, AI-native silicon. It’s this that has helped to position RISC-V, an ISA that only recently turned 15, as the architecture of choice for the next trillion dollars of AI investment.

“AI moves faster than any other field, and RISC-V is the only architecture built to keep up” says Dr. Philipp Tomsich, Founder & Chief Technologist at VRULL GmbH, Vice-Chair of the RISC-V Technical Steering Committee. “With open standards, domain-specific acceleration, and freedom from legacy baggage, RISC-V is the AI-native foundation for innovation, from edge devices to supercomputers.”

Supporting this at an infrastructure level requires hardware and software vendors to come together to deploy AI-capable hardware and enabling software across the entire stack. This spans everything from sensor-level microcontrollers (MCUs), through edge AI processors, to high-performance cloud solutions in data centers.

Having grown up in the era of vectorization, extensibility, and heterogeneous compute, RISC-V enables levels of custom instructions and domain-specific acceleration far beyond what proprietary cores from incumbents can offer – providing hooks for future paradigms such as optical/photonic paths, composable infrastructure and memory innovation.

The “V” in RISC-V was always meant as a subtle nod to vectors – reflecting founder Krste Asanović’s thesis chip in the early 1990s, a vector machine for running neural nets. This includes extensions for scalable vector processing (with flexible vector lengths, something older SIMD models lack), mixed-precision data handling, and other accelerators that are baked into the ISA rather than retrofitted.

This architectural philosophy makes RISC-V a natural fit for AI-native, domain-specific compute—from ultra-low-power edge inference to data center transformer workloads—and not just theoretical. Major hyperscalers, startups, and chip designers are already proving its viability in custom, domain-specific AI silicon.

RISC-V also avoids the supply chain and roadmap development challenges that occur when ‘locked in’ to a single vendor. Access to the latest technology is not always guaranteed, and licensing from a proprietary ISA often means relinquishing some autonomy of roadmap development. In contrast, RISC-V empowers developers to innovate on their own terms. It ensures that their silicon strategy remains their own—technologically and commercially.

AI Workloads Need A New, Open Approach

The first phase of AI focused on time-to-market. This has resulted in the deployment of platforms that are high in cost, footprint and power. Consequently, the cost of training a model is now outside the capability of the vast majority of customers.

The RISC-V community sees us entering a new phase of maturation driven by two market forces:

1. A need to create solutions for the edge, where there are significantly more challenges related to cost, power, performance and area (PPA)
2. A need to drive down the total cost of ownership (TCO) of cloud platforms

The RISC-V ISA is designed for modularity. Its dual advantage of standardization and customization makes it ideal for domain-specific compute, such as:

And when it comes to AI workloads, it is transformer workloads – including GenAI and large language models (LLMs) such as ChatGPT – that underpin today’s most visible breakthroughs. These models, which also power vision and multimodal systems, rely heavily on matrix multiplications and attention mechanisms. With RISC-V, designers can add custom extensions and accelerators tuned for transformer workloads, making large-scale models more practical to deploy across diverse platforms and improving full-stack optimization for inference speed.

Transformer use cases include foundational model training, large-scale inference and serving, multimodal models that blend vision and language, long-context transformers handling millions of tokens, and specialized scientific and enterprise applications such as drug discovery, climate modeling, and protein folding.

These LLM-driven workloads reflect the challenges emphasized at the AI Infra Summit – LLM performance bottlenecks, the sustainability of agentic AI, and the demand for composable memory infrastructure.

Hardware and Open Software Co-design

Modern silicon development requires a co-design mindset: hardware features and software support must evolve in lockstep. RISC-V’s open model makes this possible by allowing hardware architects and software engineers to collaborate in real time. New instructions and accelerators arrive with toolchains, compilers, and libraries already in place—ready for developers to use on day one. This tight feedback loop ensures that AI-focused extensions are not created in a vacuum, but instead reflect real workload needs and deliver end-to-end optimization.

This emphasis also reflects the Summit’s ‘AI Building AI’ theme: design automation and generative models accelerating chip and software co-design cycles. It aligns perfectly with RISC-V’s broader narrative: dynamic, open-source infrastructure frameworks make the ISA evolution practical and accessible. They enable vendors to deploy the latest RISC-V variants quickly, without breaking legacy software, ultimately enriching the software ecosystem while empowering silicon innovation.This work to align hardware with software in order to optimize AI capabilities traverses industries and use cases. Industry leaders from Akeana, Alibaba, Andes, IBM, OpenChip, Rivos, Semidynamics, SiFive, Tenstorrent, Ventana, and VRULL are collaborating openly to establish standards that serve the global AI ecosystem. Task groups developing the Integrated Matrix Extension (IME), Matrix-in-Vector Extension (VME), and Attached Matrix Extension (AME) are advancing capabilities for high-efficiency matrix operations—a cornerstone of modern AI workloads such as transformers and deep learning.

These efforts aim to enable high-efficiency matrix operations, a cornerstone of modern AI workloads such as deep learning, by tightly coupling hardware enhancements with corresponding software readiness. Every design choice is backed by data. In the RISC-V standardization process, engineers analyze real machine-learning (ML) and high-performance computing (HPC) workloads, identify software bottlenecks that hardware could address, and model “what-if” scenarios using prototype instructions. These matrix initiatives are a clear demonstration of how software needs, and empirical data from real workloads, directly inform hardware design decisions.

The specification drafts must explicitly provide rationales for each instruction using rigorous quantitative and qualitative arguments. Co-designing the software and hardware together ensures that one is not left without the other, avoiding the age-old ‘chicken vs egg’ trap that siloed development so often falls into. Extensions are justified with rigorous profiling and performance measurement, ensuring every addition to the ISA solves a meaningful problem. By insisting on evidence-driven design and early software prototypes, RISC-V extensions avoid “feature creep” and instead target the features that matter most to developers and end-users.

Crucially, all of this happens in the open. Compiler, simulator, and library support is upstreamed into LLVM, GCC, and the Linux kernel well before silicon ships. By the time chips reach tape-out, software stacks—including ML frameworks such as PyTorch and TensorFlow—already exploit their AI features. This “zero-day” bring-up means new hardware delivers immediate performance gains in real-world applications, as well as giving enterprises the deployability assurances they expect from MLOps, confidential computing & secure AI.

Again, standardization plays a key role. RISC-V “profiles” bundle extensions into guaranteed feature sets that software developers can target with confidence. This confidence also guides enterprise ‘build vs buy’ decisions by providing a standardized baseline across the ecosystem. With the RVA23 platform ratified in late 2024 and with hardware expected in 2026, hardware vendors and software developers alike gain a trusted platform standard. Canonical, Red Hat, and NVIDIA have already pledged support, signaling confidence that their contributions will carry forward across a wide RISC-V ecosystem.

This hardware/software co-engineering yields concrete results. Upstreaming of software enables “zero-day” bring-up of new RISC-V AI cores – meaning the moment silicon comes back from the fab, the Linux operating system, compilers, and runtime libraries already support its AI features. The result is that hardware enhancements immediately translate into real-world performance gains for AI applications, with no lag time.

At the same time, the nature of RISC-V is such that companies are free to implement their own instructions; albeit with a rigorous process in place as to how that is achieved. power or performance, writing libraries that map directly to their customized hardware while keeping the application software layer consistent. Today, the onus is on each vendor to enable software to support those customizations. A good example is in AI software stacks, where standards like Pytorch or TensorFlow exist. A company could decide to implement instructions where the combination of their software and hardware delivers meaningful benefits on a metric such as power or performance. The application software remains consistent, but the company writes libraries that take advantage of their customized hardware.

In summary, RISC-V’s open co-design methodology represents a scalable path to building AI-native platforms. From day one, the upstream software ecosystem supports each hardware enhancement. This synergy between toolchains, ISA innovation, and the flexibility to address real-world AI requirements now and far into the future, is a powerful differentiator. It allows RISC-V to deliver rapid, domain-specific innovation at the pace the AI era demands.

RISC-V in the Real World: Tangible Momentum

RISC-V is already powering AI-native silicon designed specifically to tackle modern AI challenges. Among the companies pushing the boundaries with RISC-V are:

• Andes Technology, a founding member of RISC-V International, provides a comprehensive family of RISC-V IP cores with DSP, vector, and extensibility features — supported by automation tools for custom instruction extensions — powering AI in SoCs across applications from ultra-low-power sensor nodes to the data center.
• Codasip empowers SoC developers with customizable RISC-V cores using its CodAL design language. It claims over 2 billion cores shipped, including configurations tailored for AI/ML edge use cases.
• NVIDIA, which provides much of the accelerator technology that has empowered the AI boom, shipped over 1bn RISC-V cores in 2024, as well as announcing its intention to port its CUDA AI acceleration stack to the RVA23 profile. This underscores that RISC-V’s relevance extends beyond the open software ecosystem to mainstream AI applications, serving as the orchestrator of the world’s leading proprietary GPU architecture.
• Semidynamics, a European Integrated Matrix Extensions (IME) pioneer and supplier of IP cores, recently introduced a RISC-V Tensor Unit that supports streaming workloads, sparse/dense tensor ops, and AI dataflow processing. By embedding vector and tensor capability into the CPU, Semidynamics is tackling energy efficiency and PPA challenges central to the AI data centers track at Infra Summit 2025.
• SiFive, a commercial vendor formed by RISC-V’s inventors, delivers CPU cores in IP form for AI use cases – from minimally configured edge sensors up to enterprise-grade cloud infrastructure systems.
• SpacemiT develops RISC-V processors for AI CPUs—its Muse Book features the K1 chip, as does Deep Computing’s laptops. The upcoming 64-core VitalStone V100 targets server-grade AI workloads using the upcoming RVA23 standard.
• Tenstorrent builds high-performance AI processors using RISC-V CPU cores and chiplet architectures, focusing on scalable compute from edge to data center. It collaborates with Japan’s LSTC on a 2nm AI accelerator and has opened its chiplet specification (OCA), fostering a composable, interoperable silicon ecosystem.
• Ventana delivers high-performance RISC-V processors and chiplets designed for scalable data center, AI, and automotive workloads. Its Veyron family achieves industry-leading single-thread performance and enables modular system integration through open chiplet standards such as OCP Open Chiplet Economy (OCE). By combining compute leadership with flexibility, Ventana accelerates the adoption of RISC-V across all high performance markets.
• VRULL advances foundational R&D in the software stack – including runtime systems, toolchain optimization, and pre-silicon exploration – to ensure that RISC-V evolves as a truly AI-capable platform. Grounded in real-world workloads and performance modelling, its contributions to the Attached Matrix Extension (AME) and IME focus on enabling outer-product operations and other matrix patterns critical to AI inference.
• XuanTie, a brand under Alibaba’s DAMO Academy, advances RISC-V for AI across cloud-to-edge, designing server-grade processors like the XuanTie C930 for AI-HPC applications. It also drives compiler and toolchain support and contributes to new matrix-extension standards, enabling sovereign domestic infrastructure.

On the software front, the recent developer preview of Red Hat Enterprise Linux 10 on SiFive’s HiFive Premier P550—delivered in collaboration with the RISE Project—provides a proven enterprise-grade platform for building and deploying RISC‑V-based AI workloads. Similarly, Canonical is preparing to deliver Ubuntu desktop support targeting the RVA23 profile in upcoming 25.10/26.04 releases, ensuring RISC‑V developers have stable, modern Linux distributions. RVA23 is set to usher in many more of these landmark software moments–not least, CUDA for RISC-V.

Open projects like llama.cpp are now fully leveraging 128-bit RISC-V Vector extensions to accelerate quantized inference. Compiler teams, supported by RISE initiatives, are upstreaming support for RISC-V in key AI frameworks like PyTorch—enhancing compatibility and performance without the need for proprietary extensions.

What Does This Mean for AI Developers?

For AI developers, RISC‑V transforms the hardware landscape from a proprietary constraint into an open canvas that adapts to workloads, not the other way around. This shift delivers innovation at speed, workload specialization, and freedom from vendor lock-in.

To shape and innovate the future of AI infrastructure, developers must embrace the RISC‑V opportunity. Here’s how:

• Explore and Adopt: Explore the growing ecosystem of RISC‑V IP cores, development boards, and toolchains and their role in full-stack inference optimization. Integrate RISC‑V into your next-gen AI systems—whether at the edge or the cloud—and experience AI-native hardware in action.
• Contribute and Collaborate: Join RISC-V International—the standard-setting body behind the open ISA. Membership for individuals is free and grants access to working groups, while companies may join at tiered levels, from General to Premier, with associated fees and governance benefits. If you’re a software developer, consider joining the RISE AI/ML Working Group—a community-led initiative under the Linux Foundation—to help drive RISC‑V’s AI software maturity. The group fosters collaboration on frameworks like PyTorch, TensorFlow, TFLite, and llama.cpp, ensuring they perform optimally on RISC‑V and directly influencing LLM performance and agentic AI readiness.
• Innovate and Optimize: Leverage RISC‑V’s open, modular ISA to co-design custom hardware and software. Tailor extensions—like vector, tensor, or matrix operations—specifically to your workloads, achieving unprecedented power efficiency and latency improvements at every layer, without sacrificing portability.
• Enhance Software Success: Developers who accelerate time-to-value by embracing RISC-V as their everyday development platform will get ahead. Getting hands-on hardware matters—but so does working on RISC-V-powered laptops. In fact, you can now purchase a DeepComputing RISC-V mainboard for the Framework Laptop 13, turning a modular notebook into a full RISC-V workstation and enabling you to build by running RISC-V on RISC-V. This real-world environment gives early adopters confidence, speeds porting, and deepens toolchain-level proficiency. Of course, if you’d rather start small, even the $5 Raspberry Pi Pico 2 has RISC-V hardware ready to experiment with – and we’re looking forward to new RVA23-compatible developer boards coming 2026.

In short, RISC-V flips the traditional model: hardware now adapts to the realities of modern AI software. For those building the next generation of models, frameworks, and platforms, that means faster iteration, reduced time-to-value (and in turn, lower cost), and a direct path from innovation to impact.