Arteris

📰 NEWS ALERT: Arteris to Provide FlexGen Smart NoC IP in Next-Generation AMD AI Chiplet Designs 🚀 Arteris’ smart NoC IP will be utilized by AMD in semiconductor designs to enable improved product performance and efficiency. FlexGen will provide high-performance data transport in AMD chiplets powering AI across the company’s broad portfolio which spans from data centers to edge and end devices. Mydung Pham, Corporate Vice President Silicon Design Engineering at AMD 🎤: “Integrating Arteris’ FlexGen NoC IP technology into a range of AMD chiplets, we can automate interconnect configuration and enable seamless connectivity among SoC components while strengthening the best end-to-end AI compute portfolio in the industry.” 🔗 Learn more in the press release: https://hubs.ly/Q03B6hVX0 #AI #semiconductors #innovation #Arteris #AMD #FlexGen #NoC #SoC #chiplets

Semiconductors are transforming our world faster than ever. At Arteris, we're not just enabling chip design — we connect ideas, expertise, and bold vision 🤝🧩 We've built a global network with our numerous partners that accelerates SoC development - delivering interoperability, scalability, and production readiness for silicon success. Learn more about the partnerships we have in place ➡️ https://hubs.ly/Q03BJlG_0 Or — connect with our ecosystem team to learn more Guillaume Boillet, Jean-Blaise Pierrès #semiconductors #SoC #NoC #AI #interoperability #innovation #ecosystem #Arteris

Are you joining DVCon Japan 2025 on August 20 in Tokyo? If yes, we should meet 🤝🏼 We’re excited about heading to DVCon Japan, the leading conference dedicated to design and verification methodologies, tools, and standards for complex electronic systems and ICs. 🎤 Join our tutorial session: “Will it Blend?” – Verifying the Hardware / Software Interface of Complex SoCs 🗣️ Presented by: Josh Rensch, Director of CAE, Arteris 🕒 4:50–5:40 PM This tutorial will explore using SoC integration technologies to "blend" the components such as Hardware Description Languages (VHDL, System Verilog), Unified Power Format (UPF), Software Languages (C#/C++), Interconnect standards (IP-XACT, AMBA) and purpose built layers such as the Universal Verification Methodology (UVM) and System Verilog Assertions (SVA) together by proposing a more efficient methodology to increase productivity and help ensure first time SoC project success. Want to discuss your specific design needs? 📅 Explore how Arteris products and solutions can optimize your team's success by booking a meeting with the team: https://hubs.ly/Q03BJqlL0 #DVConJapan #Arteris #SoC #HSI #NoC #semiconductors #innovation

On August 5th, we reported our 2Q2025 results. Check it out. We reported another strong financial quarter, meeting or exceeding all of our guided financial metrics. ACV plus royalties in the quarter reached another record-high at $69.1 million. Revenue was at the top-end of our guidance at $16.5 million. AMD licensed Arteris FlexGen smart NoC IP for its chiplets powering AI. For 3Q2025, we are guiding ACV plus royalties between $69.5M and $72.5M (+17% Y/Y), and revenue between $16.8M and $17.2M (+16% Y/Y). For FY2025, we are guiding between $72M and $78M in ACV plus royalties (+15% Y/Y), and revenue between $66M and $70M (+18% Y/Y). We believe the scale and scope of our long-term opportunity remain robust and are supported by our current products and strong product pipeline of new Silicon System IP technologies, as well as growing relationships with some of the largest and most advanced electronics companies in the world. Our customers continue to innovate in exciting high-growth areas, such as Generative AI, Autonomous Driving, 5G and 6G communications using Arteris products and global support.

The fifth edition of our monthly newsletter, Connected by Arteris - LinkedIn edition is here 📬 It covers the latest product updates, industry news, useful resources, and upcoming events to meet the team in person. There are two easy ways to subscribe: 🔸 Hit the Subscribe button here on LinkedIn 🔸 Fill in the form here: https://hubs.ly/Q03mq__G0 👋 This edition features: AMD, Mydung Pham, K. Charles Janac, Insaf Meliane, Ed Sperling, Semiconductor Engineering, Nitin Dahad, Michal Siwinski, EE Times | Electronic Engineering Times, Bernard Murphy, Andy Nightingale, SemiWiki.com, Josh Rensch, Laurent Moll, John Min #newsletter #semiconductor #innovation #Arteris

AI and HPC workloads are pushing the limits of traditional SoC design — and chiplets are emerging as the scalable, flexible solution. Learn how disaggregating monolithic dies into multi-die systems improves yield, enables IP reuse, and accelerates innovation. From die-to-die interfaces to NoC IP and automation tools, this article covers the essentials. 👉 Learn more in this article by Andy Nightingale for EDN: Voice of the Engineer: https://lnkd.in/gPzQR7Pe #chiplets #semiconductors #SoC #NoC #Ncore #HPC #AI #innovation #Arteris

⏰ Starting soon! Don’t miss the deep dive into the future of chiplet-based design. Join the second day of The Future of Chiplets Virtual Event by EE Times | Electronic Engineering Times by Nitin Dahad & Sally Ward-Foxton with the speakers from the leading semiconductor companies engaging in keynotes, panel discussions and in-depth technical talks! On July 31 at 10:25 AM PDT Ashley Stevens & Andy Nightingale from Arteris will explore “Chiplets: Opportunities & Challenges”, covering: 🔸 Interoperability 🔸 Ecosystem collaboration 🔸 What’s next for AI, SoC & advanced design 👉 Register now to listen live or get a recording: https://hubs.ly/Q03zrmGR0 #chiplets #semiconductors #innovation #SoC #interconnect #NoC #AI #Arteris

Proud to share a quick overview of the Voyager Software Development Board by our partner Andes Technology, featuring their 7nm QiLai RISC-V International SoC — as showcased at our booth during DAC, The Chips to Systems Conference 2025 and presented by John Min, VP of Customer Success at Arteris. This powerful board runs both Linux/Android and AI workloads across multiple CPU clusters, and includes: 🔸 Quad-core AX45MP @ 2.2GHz — ideal for rich OS environments 🔸 NX27V Vector Processor @ 1.5GHz — optimized for ML, image & signal processing 🔸 Arteris FlexNoC — enabling high bandwidth, low latency, and deterministic performance between processors and peripherals FlexNoC was chosen to meet the stringent interconnect demands of this high-performance SoC, and it’s great to see it in action on a platform like this. Thanks to the Andes team for the partnership and to everyone who stopped by the booth to learn more about it! 🤝 #Arteris #AndesTechnology #FlexNoC #SoC #ChipDesign #semiconductor #AI #62DAC2025

What’s arguably the most pivotal technology behind every major breakthrough? It’s the chip — specifically, the system-on-chip (SoC) that integrates everything into one advanced piece of silicon 🔗 In this two-minute video, we show how successful SoCs come to life with Arteris — from enabling chiplet interoperability to accelerating innovation for some of the industry's most transformative companies and hot startups. With over 200 customers utilizing Arteris, this video reflects the innovation, expertise, and collaboration that define our work and our role in shaping the future of advanced silicon design. We invite you to watch it to learn more ✌️ #Arteris #semiconductor #chiplets #SystemIP #innovation #ecosystem

Magillem Registers from Arteris, the technology for SoC integration automation, reduces errors by using a consistent correct-by-construction methodology and an automated process that eliminates hours of repetitive manual work. This means the following for the design teams: 🔸 Smoother development of the Hardware/Software Interface 🔸 Faster scaling for large designs with less risks 🔸 Lower potential for human error 🔸 Higher efficiency of the RTL design Learn more in the datasheet: https://hubs.ly/Q03xG8fy0 #MagillemRegisters #Arteris #innovation #semiconductor #SoC #NoC