From the course: Computer Architecture Essentials
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Instruction schedulers today
From the course: Computer Architecture Essentials
Instruction schedulers today
- [Instructor] So how have out of order processors evolved? What are their specs today? Well, for starters, they are all superscalar now. Remember that the speed of a pipeline is dominated by its weakest link. The slowest part of this design is the instruction queue, which works sequentially. The Tomasulo design doesn't really benefit from the parallel execution going on. It only solves the problem with data hazards. So upgrading the instruction queue to issue more than one instruction per cycle is a tremendous improvement. Modern processors handle an impressive number of instructions at any given time. We're talking hundreds of instructions being executed simultaneously. If you're thinking that a machine so complex and efficient must have a weakness, you're on to something. Indeed, although this machine is immune to data hazards, there are actually hundreds of instructions at stake if we hit a control hazard with a misprediction. That's why these processors are usually equipped with…
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