How PCIe manages power consumption for high bandwidth

View profile for ALANKAR AGARWAL

SoC verification engineer

PCIe is usually demands for high bandwidth, robustness, reliability and no data loss but also to address one of the critical area which is to manage power consumption. As with the increase in no. of gates going into silicon due to small process geometry, power consumption is on the rise. As with increase in power consumption in auto sector where it include power flow, optimizing energy usage, and ensuring a stable and reliable power flow to various electronics system like ECU (Engine control Unit), Infotainment and ADAS. Also in now days with increase in EV power management is very vital features with use of battery. There are 3 main factors that affect the power consumption or dissipation: frequency, operating voltage and switching capacitance. P=V^2/R Power is directly proportional to voltage square, as increase in power will increase the square of voltage. Other approach to reduce the power dissipation is to have separate power wells. The majority portion of chip is operated at core clk, and a small portion of chip which is used to wake up rest of the chip when pcie operate a low power auxiliary clk. With increasing the high speed pcie we can use dual PIPE, where single PIPE operates at 8bit/250MHz, but dual PIPE operates at 16bit/125MHz. With dual PIPE, the core logic L0 is fully functional functional state with fully power on and all the clks are running.  L0s is a low exit latency (delay between a signal’s input and the corresponding output) and relatively low power saving link state.  L0s is a low exit latency (delay between a signal’s input and the corresponding output) and relatively low power saving link state. L1 offers larger power savings with larger exit latency, and is designed to work on larger period of inactivity on the link, L2 gives the most power saving & it comes to larger exit latency. #PCIE #TLP #Verification #ElectricalEngineering #ElectronicsDesign #HighSpeedProtocol #RootComplex #RC #EndPoint #PCIeLayers #Transactionlayer #Datalinklayer #Physicallayer #CPU #GPU #SSD #PCIeSwitch #LTSSM #FSM #Detect #Quiet #Active #Polling #Polling.Active #Polling.configuration #Polling.compilance #Usecase #ADAS #WIFI #cockpit #Blackbox #DMA #CRC #scalability #sensor #Response 

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