Hex-Rays’ Post

[TRACE32] How to debug the system call handler in RISC-V If we use 'var.tab %y.on sys_call_table' command using TRACE32, the complete system call handler can be printed. This material covers the debugging on system call handler in RISC-V. Hope this resource is helpful.

🔹 𝗦𝗲𝗿𝗶𝗲𝘀 𝗧𝗶𝘁𝗹𝗲: “Demystifying RISC-V External Debug” 𝗣𝗼𝘀𝘁 𝟯 — 𝗠𝗲𝗺𝗼𝗿𝘆 𝗔𝗰𝗰𝗲𝘀𝘀 𝗶𝗻 𝗥𝗜𝗦𝗖-𝗩 𝗗𝗲𝗯𝘂𝗴𝗴𝗶𝗻𝗴 “Accessing memory during debug sounds simple… until cache, PMP, and bus restrictions join the party.” Three main methods exist to access memory during debug: 1️⃣ 𝙎𝙮𝙨𝙩𝙚𝙢 𝘽𝙪𝙨 𝘼𝙘𝙘𝙚𝙨𝙨: Direct, core-independent — but can hit cache incoherence unless fenced. 2️⃣ 𝙋𝙧𝙤𝙜𝙧𝙖𝙢 𝘽𝙪𝙛𝙛𝙚𝙧: Uses core load/store instructions — simple, coherent, but depends on the core correctness. 3️⃣ 𝘼𝙗𝙨𝙩𝙧𝙖𝙘𝙩 𝘾𝙤𝙢𝙢𝙖𝙣𝙙 𝘼𝙘𝙘𝙚𝙨𝙨: Direct hardware path — coherent and core-independent, but adds design complexity. The right choice depends on balancing 𝘀𝗽𝗲𝗲𝗱, 𝗰𝗼𝗵𝗲𝗿𝗲𝗻𝗰𝗲, and 𝗿𝗼𝗯𝘂𝘀𝘁𝗻𝗲𝘀𝘀 for your debug scenario. 𝗡𝗲𝘅𝘁 𝘂𝗽: We’ll break down how loading a program and setting a breakpoint really works under the hood. 𝗛𝗮𝘀𝗵𝘁𝗮𝗴𝘀: #HardwareDebug #ProcessorDesign #RISCV #HardwareSecurity

🚀 Day 18 & 19 ✅ Solved Leetcode problems: Roman to Integer Valid Parenthesis Valid Anagram Longest Common Prefix 📡 Study (Operating Systems): CPU Scheduling: FCFS, SJF, Priority, Round Robin (concepts + examples) Context Switching Process States Scheduling Interview Qs 💡 Key Learnings: CPU scheduling algorithms balance efficiency and fairness — Round Robin is especially useful for time-sharing systems. Context switching is the backbone of multitasking, but it adds overhead that must be minimized. #90daysofcodechallenge #leetcode #dsa #operatingsystem #cpuscheduling #codingjourney

This is a re-post with new picture. I had modified the RISC-V picture without changing the bottom portion to reflect x86. ϕEngine has only 4.5× the code density of x86. The 19× was for RISC-V. Sorry about that. We compared RISC-V with ϕEngine on saturated add. But how does the x86 compare? At least it has flags, so the code won't be quite as bad as RISC-V. For an even comparison, we will assume that the calling convention allows passing of the arguments in EAX and EBX: 0000: 01 d8         add  eax,ebx 0002: 71 07         jno  b <NoSat> 0004: 72 06         jb  c <Minus> 0006: B8 FF FF FF 7F     mov  eax,0x7FFFFFFF 000B: c3           ret 000C: B8 00 00 00 80     mov  eax,0x80000000 0011: C3           ret 0012 Keep in mind that, when overflow happens, the sign is the opposite of what it should be. The code came to 18 bytes. That is 4.22× times the code density of RISC-V. Much of that is because it has flags and can detect overflow in hardware. But the x86 can't do clamping in hardware so it has to test the flags and load the appropriate values into the register that returns the result. So ϕEngine code density is 4.5× that of the x86. The x86 is about midway between RISC-V and ϕEngine on a log scale.

The ϕEngine ISA has gone through a huge number of iterations and permutations over the past seven years of its existence. That is R&D at its finest. The ϕSemiVec portion of ϕEngine supports vectors with an arbitrary number of elements (called their Counts). It was recently expanded to double the maximum number of elements in each Vector Segment that can be processed in parallel. Since ϕSemiVec shares the Scalar Register Files with their Scalar Operation Counterparts, it makes accessing the same values easy when mixing scalar and vector operations. However, the vector operations can now use up registers more quickly. So, once again, I used a technique that was inspired by the AMD64 REX byte which extends the number of integer registers in the x86. But instead of quadrupling the number, I am just doubling the number of both integer and floating point registers. This requires two prefixes. One is for the Subject and one is for the Object when it is a register. Vector operations are done in segments, so whole vectors do not have to reside in registers at the same time. Instead, they are cycled in and out of registers from and to memory working on a chunk at a time. These chunks are limited to a maximum magnitude of 16 units (used to be 8). For integers this is 16 bytes and for float is 32 bytes. One quarter of all data registers are Scratch Registers that also serve as Argument Registers when passing arguments by register. All of these can be reached without a prefix. An equal number of Protected Registers beyond those can also be reached without a prefix. All of the new registers that require a prefix are Protected Registers.

hardware peeps correct me if im wrong; So it turns out you can't safely use C bitfields for any struct that maps directly to a hardware interface (like GDT entries, device reg, etc.). because C standard says bitfield order (LSB-to-MSB vs. MSB-to-LSB) is implementation-defined.

Critical Section (CS):A section of code that must be executed by only one thread at a time to prevent data inconsistency. Race Condition:Program correctness depends on thread scheduling → can cause unpredictable results. ✅ Solution: Locks or atomic operations. Preemption:When the scheduler interrupts a running thread to give CPU to another. Controlled by locks, disabling interrupts, and priorities.

Ever had a microservice dependency fail and bring down your entire application with it? It's a common problem in distributed systems, but one that can be solved with the Circuit Breaker pattern. I'm excited to share my new Dart package, dart_circuit_breaker, now available on pub.dev. It provides a simple, state-driven solution to prevent cascading failures and keep your services healthy. Learn how to build more robust applications and add it to your project today! 🔗 https://lnkd.in/dFKargyV #Dart #Flutter #SystemDesign #DistributedSystems #ResilientSystems #CircuitBreaker #SoftwareArchitecture

Dear connections here I explain android based storage IC critical partitions backup step by step procedure First, we need to connect IC - EMMC or UFS, we need any JTAG software boxes for this like easyjtag, MIPI, UFI, F64, Medusa pro .. here I am using Easyjtag plus for the illustration After connecting the IC, just load firmware, then the firmware gpt will be filled, then we need to manually unselect the filled partitions and select the unfilled partitions, this partitions will be the critical partitions of the particular IC ✍️ Anees Kokadan aneeskokadan.com

For some reason, I like the idea of generators and their use, even in the cases when they create too much overhead. However, the DFS/BFS problems are boring overall, so using some unnecessary solutions might help with it. The post: https://lnkd.in/dUu77XV9 The problem: https://lnkd.in/dcg3fkSN