New ECE/EEE/CSE Grads: Essential VLSI Topics

Summary of topics important for new college graduates in the field of ECE/EEE/CSE willing to enter into VLSI. ✓ Verilog: [1] Stratified Event Queue and how each event regions are executed. [2] Difference b/w wire and reg, blocking and nonblocking, Task and Function, Intrastatement and Intra assignment delay. [3] Synthesizable and non-synthesizable construct. [4] Dataflow, behavioral and Structural modelling style of coding. [5] Clock generation, Glitch, D FF, counters, multiplexer code using verilog [6] Race condition in verilog. Coding guidelines. Different sets of code using blocking and nonblocking. Drive strengths. UDP primitives. [7] initial and always block execution. localparam and defparam statements. Generate statements. ✓ Digital Circuits: [1] Combinational circuit: a. All Basic gates using 2:1 Mux. b. Full adder / Half adder using Mux c. Mux tree calculation d. Adder using decoder, counter using Mux e. All types of adder implementation using gates. f. Priority Encoder circuit [2] Logic Gates: a. Boolean expression reduction techniques. b. Hazards c. Implicants, PI, EPI [3] Sequential Circuits: a. Mod counter implementation with duty cycle. b. Conversion of one Flip Flop to another. c. Difference b/w latch and FF [4] State Machine: a. Overlapping and non overlapping Sequence detector. b. Mealy and Moore FSM ✓ Timing Analysis: [1] Concepts of Clock Skew, Slew, Slack, Metastability, Propagation delay, Setup time, Hold time. [2] Synchronizers and FIFO [3] Worst delay Calculation ✓ Miscellaneous: [1] ASIC and FPGA flow in detail [2] Clock Domain Crossing (CDC) - Data loss, Data incoherence. [3] Cache related concepts, Algorithms like LIFO, etc [4] Protocols - AHB, APB, I2C [5] MOSFET concepts ✓ Systemverilog: [1] Difference b/w Logic / reg /wire. [2] RTL design constructs used in SV. [3] All OOP related concepts - class, Objects, Abstract class, pointers, Inheritance, Polymorphism and Encapsulation, Data hiding, Interface class [4] Concept of Semaphore, Mailbox, interface. [5] Event Queue of SV. How to construct a simple testbench in SV. [6] Arrays understanding - Static, Dynamic, Packed, Unpacked, associative. #vlsi #asic #uvm #electricalengineering