We are pleased to show you another demo of the capabilities of SYSTEM-STACK. SYSTEM-STACK detects and fixes in real-time PCIE gen speed degradations (at root and endpoint). See below the impact on a high-speed Ethernet network card at 100Gb/s (12.5GB/s) that suffered a degradation from gen3 to gen2. For applications with small message sizes the degradation goes unnoticed while for large message sizes, the bandwidth is halved. The recovery in this case had a 2X improvement on bandwidth and the application/benchmark wasn't disrupted by the real-time fix. Think next on the positive impact at very large scale for the scale out network of an AI cluster with tens of thousands of these PCIE devices exposed to these missed performance degradations.
SYSTEM-STACK fixes PCIE speed degradations in real-time
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A new line of clock fanout buffers from Skyworks Solutions, Inc. simplifies clock trees and improves signal integrity in next-generation networks, data centers, and PCIe Gen 7.
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Closing DDR4 IP at multi-GHz on an advanced node isn’t just about squeezing timing margins—it’s about managing the hidden complexities of IP handoff, mixed tool flows, and constraint mismatches. When we hardened DDR4 at 1+ GHz on 12nm for an Edge AI SoC, the real challenges went far beyond timing. The ripple effects of SDC migration, unresolved module mapping, and congestion hot spots quickly became barriers to convergence—issues that, if left unchecked, can derail an entire flow. In this whitepaper, we share the methodology that helped us break that cycle: - Early floorplan decisions that shaped timing success - Constraint migration that mattered more than endless ECO loops - SI/PI checks that flagged issues well before tape-out If DDR hardening feels unpredictable, these lessons offer a framework to cut iterations, reduce risk, and get closure with confidence. 👉 Read the full whitepaper here → https://lnkd.in/dXBf4F5W
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In this video, we showcase our Xgig PCIe6 Exerciser acting as a host, and another Xgig PCIe6 Exerciser acting as an endpoint sending data traffic across a Nubis optical link. Learn more: https://lnkd.in/gXJ8Tbm8
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PCIe over optics extends #PCIe links over distance for more efficient data center organization. VIAVI Solutions Sara Haber walks through a demonstration of a VIAVI Xgig Exerciser generating and verifying PCIe traffic over a Samtec Inc Firefly™ optical transport system to an endpoint. #AI #Hyperscale #semiconductors #aihardware #CXL #cloudtechnology #fiberoptics https://lnkd.in/eEJ24_Ae?
PCIe Traffic Over Samtec FireFly™ Optical Transport System
video.viavisolutions.com
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Our new Intel Ethernet E830 series NIC is a PCIe Gen4 powerhouse. - It can scale from 25 GbE to 200 GbE with sub-microsecond timing and built-in Secure Boot. -Backward-compatible with E810 drivers for seamless upgrades. - Ideal for hyperscale data centers, AI clusters, and 5G/edge networks. https://lnkd.in/ea58kuRf
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Live from Seoul today! Granite River Labs is proud to sponsor the PCI-SIG Developers Conference Korea 2025, where industry leaders and experts are sharing insights on how PCIe® technology is shaping the future of high-performance computing. As the first PCIe Authorized Test Lab approved by PCI-SIG® to perform official Integrators List compliance testing for PCIe 4.0 & 5.0, GRL has been supporting the industry with trusted PCIe® expertise — from compliance and pre-compliance testing to signal integrity and automation solutions across 9 labs worldwide. 🔗 Learn more about GRL’s PCIe Test Services https://hubs.la/Q03KfwX70 🔗 Signal Integrity Test Automation Solutions https://hubs.la/Q03KfyK00 #EventsAtGRL #PCIe #SignalIntegrity #TestSolutions #TestServices #Interoperability #Seoul
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