big.LITTLE Architecture

ABSTRACT

Rapid advancements in technology have brought about a remarkable increase in the performance of the CPUs used in mobile computing devices, such as smartphones and tablet computers. Operating frequencies or clock rates of such CPUs have increased from a few hundred MHz to several GHz, and the devices have expanded from having a single core to multiple, high performance, separate cores. However, the immediate downside to any of these techniques is a significant rise in the power consumed by the device‟ s CPU.

For battery-powered mobile devices, this translates to a higher drain on the device‟ s battery, resulting in a reduced battery life and lower usable duration of the device for the user. 

INTRODUCTION

To achieve higher computing performances at the same or lower power consumption levels in mobile computing devices, several new processor architectures have been designed. One of these is the asynchronous clock architecture, which uses the concept of running one core at a lower voltage and clock frequency, and the other at a higher voltage and clock frequency, in a dual-core CPU.big little architecture concept is an upgraded one of asynchronous clock architecture.

OVERVIEW

The big.LITTLE architecture is designed using the technique of employing separate cores with different computing powers within the same CPU. The more powerful (or “big”) core is responsible for handling computing intensive tasks, such as high-definition video playback, whereas the less powerful (or “LITTLE”) core handles lesser demanding tasks, such as text editing.

Both the cores implement exactly the same processor architecture (ARMv7), and are capable of executing the same instructions. The only difference lies in the way the cores handle the execution. While the “big” core is designed with performance as its primary goal, the “LITTLE” core is designed with efficiency as its principal target. The big.LITTLE architecture from ARM uses a Cortex™ A15 processor as its “big” CPU, along with a Cortex™ A7 processor as the “LITTLE” CPU to form the combination of high- and low-powered cores within a single unit.

• The high performance Cortex™ A15 is an out-of-order, triple issue processor with a pipeline length of between 15 and 24 stages. 
• The low power Cortex™ A7 is an in-order, non-symmetric dual-issue processor with a pipeline length of between 8 and 10 stages.

The big.LITTLE architecture benefits from the fact that the two separate cores are identical, capable of handling the same instructions and the same higher-level software applications. This proves to be extremely beneficial in power-conscious applications, such as smartphones. The big.LITTLE architecture can be deployed in smartphones, with the “LITTLE” core handling normal telephony-related functions of the device, and the “big” core taking over control from the “LITTLE” core when higher levels of performance, such as multimedia playback, are needed. To efficiently realize a system based on the big.LITTLE architecture.

The time needed to migrate a task between the cores must be taken into account. A finite amount of time would be needed to save the state (which includes the content of all the registers and caches) of both the cores, and this time should not be too long. If the context switching latency is beyond a certain threshold, the system will suffer from noticeable performance degradation.

To complete the switching in the minimum possible time, a specially designed interconnection bus, known as the CCI (Cache Coherent Interconnect) is used to transfer data among the cores. For an application running on a device at 1 GHz, the big.LITTLE architecture ensures that this switching is completed in less than 20,000 clock cycles (or 20 µs), a duration so small that it does not affect or interfere with the end user‟s application running on the device. The big.LITTLE architecture also provides the flexibility of configuring the number of “big” and “LITTLE” cores within the CPU. The present version of the architecture allows up to four cores of both types to be configured, letting the designer have extensive control over the performance of the CPU. Furthermore, due to differences in computing powers, both the “big” and “LITTLE” cores occupy different areas on the die, with the “LITTLE” core taking up just 13% of the area of the “big” core. It is recommended that the number of “big” and “LITTLE” cores in a particular CPU be kept equal, to simplify the context switching and task migration software. 

Conclusion

The article presented an overview of the big.LITTLE architecture, and its key benefits in providing a superior performance at reduced power consumption. It also compared the big.LITTLE architecture with other competing architectures, such as the asynchronous architecture.

Reference: Benefits of the big.LITTLE Architecture- whitepaper (SAMSUNG ELECTRONICS)

Name: Harish K

Mail id: harishk200200@gmail.com