Don't be deceived. Hardware implementations of CRC (cycle redundancy check) algorithms are not based on polynomial division.

I'm a bit frustrated to see all those Youtube videos explaining how hardware CRC implementation circuits are based on polynomial division.

Actually reality is different and if you find any CRC HDL generator in the internet (for instance one from OutputLogic.com) you will be surprised to see no state machine or other algorithm that detects the end of the received message and then carry on for a few more clock cycles to actually generate CRC for that message.

Instead you will see that CRC sequence becomes immediately available for just received message in the same clock cycle.

How is this? Because shift registers used for CRC calculation of streaming data are different in design than shift registers that mimic polynomial division.

To see how hardware CRC circuits work, and also see how they can be modified to calculate parallel CRC that can process multiple incoming bits in a single clock cycle check this video: