How DAC Glitch and Settling Time Impact Output Quality

Digital-to-Analog Converters play a critical role in modern electronics by transforming digital signals into analog voltages or currents. While they are indispensable in systems like audio playback, waveform generation, communication systems, and instrumentation, their performance hinges on several key dynamic and static characteristics.

Among these, glitch impulse energy and settling time are two often overlooked yet fundamentally important parameters that greatly influence output signal quality. In this article, we'll unpack what they are, why they matter, and how they manifest in real-world systems.

Understanding DAC Glitch

What is a DAC Glitch?

A DAC glitch (also known as glitch impulse energy) is a momentary and unwanted spike in the analog output when the digital input changes. It occurs due to mismatches in the internal switching of binary-weighted components (such as current sources, resistors, or capacitors) inside the DAC.

When a digital code changes, especially at major code transitions (e.g., from 0111 to 1000), not all bits change state simultaneously. This causes transient errors that result in a short-duration spike or dip in the output voltage.

Root Cause

The glitch arises from:

• Capacitive coupling between internal switches
• Timing skew in switching logic
• Unequal settling of bits, especially in thermometer or binary-weighted architectures

Why It Matters

In high-speed or high-precision applications, glitch energy can:

• Distort the analog output waveform
• Introduce spurious signals in frequency domain (spectral purity degradation)
• Create audible artifacts in audio DACs
• Causes data integrity issues in communication or control systems

Measuring Glitch Energy

Glitch impulse is typically measured in nV·s (nanovolt-seconds) and is quantified by integrating the area under the voltage-time spike during a code transition.

Understanding Settling Time

What is Settling Time?

Settling time is the duration it takes for the DAC output to reach and stay within a specified error band (e.g., ±0.5 LSB or ±1%) of its final value after a code change. It includes all internal switching and stabilization processes.

Fast vs. Accurate Settling

• Slew rate-limited region: The Initial part of the response where the output changes rapidly.
• Linear settling region: Where the output slowly converges to the final value, potentially affected by parasitics and internal compensation.
• Ring-down or overshoot: Depending on the DAC architecture and layout, there may be small oscillations before settling.

Impact on System Performance

Longer settling time leads to:

• Lower throughput: System must wait longer between DAC updates.
• Poor temporal resolution: Harmful in waveform generation or control systems.
• Signal distortion: Especially for step or impulse signals in DAC-driven circuits.

Combined Impact: Glitch + Settling Time

When both glitches and slow settling are present, the DAC output may show severe transients followed by delayed convergence. This is especially problematic in:

• Data acquisition systems
• Audio DACs (clicks and pops)
• Software-defined radios (SDRs)
• Mixed-signal ICs where DAC output drives sensitive analog blocks

These imperfections not only degrade signal quality but may also lead to system-level errors, such as incorrect feedback in closed-loop controls or degraded SFDR (Spurious-Free Dynamic Range) in RF systems.

Minimizing Glitch and Settling Time

Architecture Choices

• Segmented DACs: Combining thermometer and binary-weighted segments reduces glitch energy.
• Current-steering DACs: Favored for high-speed and low-glitch applications.
• Resistor-string DACs: Lower glitch but slower settling.

Design Techniques

• Matched layout for critical paths
• Dummy switches to balance transition paths
• Oversampling or zero-order hold techniques to smooth transitions

Calibration and DSP Compensation

• Pre-emphasis or digital filtering to mask or correct errors
• Post-correction based on measured impulse response

Real-World Example

Consider a 12-bit DAC in a waveform generator operating at 1 MSps. A glitch energy of 30 nV·s may seem negligible, but repeated over thousands of updates, these transients add up and appear as high-frequency noise, reducing the effective resolution (ENOB) and degrading signal-to-noise ratio (SNR).

Similarly, if the settling time is 1 µs and the system requires an update every 500 ns, the DAC won’t stabilize before the next code arrives—leading to distorted or erratic waveforms.