One-Transistor CMOS SRAM 0.025 square microns on 28nm CMOS

One-Transistor SRAM Stuffs More Into CMOS 

http://www.eetimes.com/document.asp?doc_id=1328453

0.025 square microns on 28nm CMOS
LAKE WALES, Fla.—The smallest static random access memory (SRAM) to date fits in the space of a single metal-oxide semiconductor (MOS) transistor, according to serial entrepreneur and regular EE Times blogger, Zvi Or-Bach, executive chairman of the newest memory maker in Silicon Valley, Zeno Semiconductor Inc. (Sunnyvale, Calif.). Zeno Semiconductor unveiled its wares at the International Electron Devices Meeting (IEDM) on December 9th.

"The magic," that enables a single NMOS transistor to act as a stable SRAM, according to Or-Bach, "comes from the two intrinsic bipolar N-P-N transistors whose emitters are the n+ material beneath the source and drain with an open base and a common collector in the N-well at the bottom." (see figures.)

Zeno Semiconductor builds its single-transistor static random access memory (SRAM) out of one NMOS transistor containing inside it two intrinsic bipolar transistors with a p-well as open bases, with a buried n-well (BNWL) as collectors and with n+ doped source/drain regions below the gate as emitters. The memory is accessed by bit lines (BL) and source lines (SL) surrounded by shallow trend isolation (STI). 
(Source: Zeno Semiconductor, used with permission)

One could argue this a three transistor bit-cell (which would still be quite a feat) but because their elements are "intrinsic" the two bipolar N-P-N transistors with open gates and common collector count at most as "virtual" transistors, and to boot, take up no more die area than the single MOS transistor on which the SRAM bit cell is based. Its really just a clever manipulation of the architecture of the single MOS transistor.

Same vertical NMOS transistor (left photo) with intrinsic N-P-N bipolar transistors (right diagram) accounting for the bi-stable states for 1 and 0 in a single transistor device forming a complete SRAM in a single NMOS transistor. 
(Source: Zeno Semiconductor, used with permission)

No matter which side you argue, there is no arguing that the bit-cells are tiny—just 0.025 square microns when cast in 28 nanometer CMOS compared with the usual 0.127 square microns. Zeno's 28-nanometer SRAM bit cells are even 37 percent smaller than Samsung's 10-nanometer FinFET SRAM bit-cells, which measure 0.040 square microns. They can also be used in either 3-D FinFET or fully-depleted silicon on insulator (FD-SOI) planar fabs while maintaining their tiny size which scales to even smaller sizes—approaching the sub-nanometer range—at more advanced nodes.

Zeno has over 50 granted patents on every aspect of its architecture and operation. Zeno's business model is to license their intellectual property (IP) to anyone for a reasonable fee, the company says.

The source (S) and drain (D) doped n+ (with gate region above the channel between them), a P-well below and a buried N-well at the bottom above a bulk silicon substrate. The single-transistor SRAM's "magic"--as Zvi Or-Bach calls it--comes from the intrinsic bipolar N-P-N transistors on each side with open base and a common collector in the bottom N-well and their emitters at the n+ material at the source and drain. 
(Source: Zeno Semiconductor, used with permission)

Zeno is also hoping to cover most of the market niches with two models of its novel transistors, one with a single transistor for the ultimate in compactness—5-timed as many bit-cells as traditional six-transistor SRAMs—and another that adds a second access transistor in series with the memory cell to create a two-transistor memory cell that cuts the leakage current and reduces access time by 40 percent while still packing three-times as many bit-cells per unit area.

"The two versions of our memory bit-cell enable us to target different markets,” said Yuniarto Widjaja, Founder and chief executive officer (CEO) of Zeno Semiconductor. “The single transistor Bi-SRAM is targeted at cost- sensitive, low-power applications such as IoT, while the two transistor Bi-SRAM technology is targeted at high-performance applications such as networking and high-performance computing (HPC)."

Two stable states result from the balance of forward bias current flowing out of the p-well and reverse bias current (0) and from electron-hole (e-h) generation at the P-well / buried N-well junction (1) after a transition switching potential in between. 
(Source: Zeno Semiconductor, used with permission.)

Widjaja claims that the same size advantage an be gained at advance nodes using FinFET or FD-SOI architectures, as well as at older nodes for non-demanding applications that are price sensitive. Zeno is also developing the architecture for logic as well a memory.

"We did memory first," Yuniarto Widjaja, Zeno chief executive officer (CEO) told EE Times. "And we are still concentrating on memory, but we are working on logic too."

Breaking cycle of advanced nodes
If Zeno can shrink the size of other devices made from its dual-function digital transistors, they may be able to obviate the need to continue seeking more and more advanced nodes in order to scale devices. Instead of continually attempting to shrink dies ad nauseam, more and more clever combos of MOS with buried intrinsic bipolar might meet many more needs than pure scaling.

The two stable states (1 and 0) maintain their integrity over time and after multiple reads, just as an SRAM should. 
(Source: Zeno Semiconductor, used with permission.)

"Zeno is working on a couple of technologies for memory and logic," Zeno board member Jeff Lewis told EE Times. "While others keep increasing their die sizes to accommodate an increasing number of transistors, Zeno is concentrating on using fewer and smaller transistors to get the same job done."

Adding an access transistor in series with the memory cell to create a two-transistor memory cell cuts the leakage current and reduces access time by 40 percent while still packing three-times as many bit-cells as traditional 6-transistor SRAMs. 
(Source: Zeno Semiconductor, used with permission.)

The "magic" according to chairman-of-the-board Or-Bach and board member Lewis, is not just the intrinsic bipolar transistors, but also the lack of die-consuming components like capacitors. In fact, the whole process uses only standard CMOS processes to achieve up to 5-times smaller components with up to 40 percent faster access times.

Applications for the single-transistor (left) or dual-transistor (right) versions of the Zeno SRAM bit-cell depends on whether you need fastest possible access time, or whether you need all-out super high density. 
(Source: Zeno Semiconductor, used with permission.)

"And not only are they smaller, but they can achieve up to 5-times less standby power," Lewis told us.

So far the company is not announcing any customers, even though they claim to have several on-the-hook.

Read all the details in Zeno's IEDM paper A Novel Bi-Stable 1-Transistor SRAM for High Density Embedded Applications coauthored by Marvell Semiconductors and Stanford University in addition to Zeno Semiconductor authors.

— R. Colin Johnson, Advanced Technology Editor, EE Times