Digital ASIC design engineer
• Overall 3 years' experience in FPGA and IC (ASIC/VLSI/System-on-Chip) with VHDL/Verilog.
• Full flow of RTL development from spec to full chip integration.
• RTL simulations and synthesis, gate level simulations, chip-level logic debug.
• Full BackEnd process (RTL2GDS) from Synthesis, Floorplan, P&R and Clk Tree.
• Custom IC design (schematic, layout, post-layout validation - DRC,LVS,ERC,PEX)
• Post silicon debug (circuit and PCB design, FPGA based test).
Student for Master's Degree in Electrical & Computer Engineering with specialization in VLSI & Mixed signal IC at Ben Gurion University under the supervision of Dr. Mor Peretz.
Research Assistant,...
Digital ASIC design engineer
• Overall 3 years' experience in FPGA and IC (ASIC/VLSI/System-on-Chip) with VHDL/Verilog.
• Full flow of RTL development from spec to full chip integration.
• RTL simulations and synthesis, gate level simulations, chip-level logic debug.
• Full BackEnd process (RTL2GDS) from Synthesis, Floorplan, P&R and Clk Tree.
• Custom IC design (schematic, layout, post-layout validation - DRC,LVS,ERC,PEX)
• Post silicon debug (circuit and PCB design, FPGA based test).
Student for Master's Degree in Electrical & Computer Engineering with specialization in VLSI & Mixed signal IC at Ben Gurion University under the supervision of Dr. Mor Peretz.
Research Assistant,...
