VLSICS Design

vlsi circuits vlsi design reliability computer-aided design (cad) post-cmos vlsi wireless communications testing emerging technologies vlsi applications design fault-tolerance molecular low power low power and power aware design security sensor networks video nano electronics biological and quantum computing communication systems intellectual property creating and sharing fpga vlsi cmos vlsi applications (communications communications leakage power phd full adder wireless wireless networks sram reversible logic phdstudent soc etc) finfet dsp design vlsi circuits computer-aided design (cad) l biological and quantum computing intellectual prop etc) nano electronics pipeline analog testing transistor stacking pattern recognition high speed fault-tolerance emerging technologies post-cmos vl write delay image processing digital signal processing (dsp) visualization power gating xilinx communication digital image processing analog-to-digital converter nanotechnology static noise margin power consumption image formation delay dibl adaptive biasing traceback method read delay iir fir fault-tolerance * emerging technologies * etc) * nano electronics vlsi circuit design * vlsi circuits * computer-aided design biological and quantum computing * intellectua nanoelectronics low voltage noise figure sleep transistor low-power power dissipation 45nm technology adiabatic logic matlab static random access memory simulation universal verification methodology (uvm) leakage current garbage output lna register exchange method adc voltage control circuit standby power reverse body bias dual threshold design quantum dot regularity lfsr asic vlsi technology low power. phase locked loop (pll) voltage scaling quantum computing cryptography pass transistor logic network on chip floating gate mosfet dynamic power verilog assist circuitry low power design domino logic fault simulation dram snm power management mosfet single-port linear range wilson mirror bulk-input voltage stacking asynchronous trajectory of mn standby start-up circuit mos resistor square wave generator misr bist characteristic polynomial primitive hardware security motion estimation hevc cordic algorithm segmentation frequency range control voltage generator integrator dcc adiabatic logic. opamp call admission control functional verification questasim multiple-valued logic quaternary logic reusable vip spi master core back gate biasing. mtncl bram gsm optoelectronics schottky junction photodetectors photovoltage ieee 802.11 side-channel analysis gate diffusion input (gdi) fast fourier transform (fft) sub threshold leakage link training and status state machine (ltssm) universal serial bus (usb) synthesizable active agent embedded rams functional coverage uvm(universal verification methodology) axi(advanced extensible interface) amba(advance microcontroller bus architecture) ahb2apb stepwise charging adiabatic ber accuracy approximate computing network-on-chip efficient dsp processing kogge stone adder roba architecture error analysis high speed multiplier fault injection scan-based attack testability security. energy harvesting impalntablr bio-medical devices pacemaker power delivery sensors single-electron transistor coulomb blockade coulomb oscillation hspice cntfet mri reversible gate resonant tunneling diode (rtd) simulink molecular electronics logic circuits fault diagnosis transistor modeling. carry save adder (csa) fault dictionary high performance vlsi circuits context information voltage control least-squares method ecu scheduling oem lattice network embedded systems power dissipation. crosstalk field emission alu multimedia concurrent processing flip-flop rf cmos sub-threshold circuits carbon nano-apex vlsi researcher research slack based genetic algorithm edge point sequential extraction carbon nanotube field effect transistor dynamic gesture recognition implicit interaction eeg lattice networks process variations operational amplifier transconductance quantum cost slew rate lock range low power circuit oscillator injection-locked spartan3e current mirror mips risc processor clock and data recovery eye diagram amplifier approximate computing (ac) error rate formal symmetrization concurrent computing carbon nano-apex emission very large scale integration (vlsi). power gain temperature-insensitive complementary metal oxide semiconductor fault coverage single precision stuck-at fault rtl. engineering change order (eco) eco cell spare cell state dependent instruction set analog multiplexer xilinx system generator edge detection power line carrier communication digital down-counter digital up-counter application specific integrated circuit snm and process variations. amba cell re-ordering recycling folded cascode channel. high vth low vth dynamic threshold etc active mode leakage reduction minimum leakage vector (mlv) standby mode band to band tunneling (btbt) feynman gates fredkin gate nmos & pass transistor. deblocking filter nios-ii soft processor dynamic range garbage exclusive-or (xor) exclusive-nor (xnor) automatic test pattern generation (atpg) subthreshold virtual channel ripple carry adder elastic buffer virtual allocator phase frequency detector vhdl bus encoding gate diffusion cell voltage controlled oscillator charge pump. trans - conductance. polarization algan/gan modfets drain - conductance cut-off frequency regulated cascode low-voltage & low-power molecular communication nano networks short channel effects (sces) diffusion channel channel capacity rf dc optical illumination ac multi-vdd tsmc bulk-driven mos ota bota body effect 12-t sram cell hotspot peak temperature three dimensional integration through silicon via. pass transistors sram cell current mode logic 32nm technology microcontroller 2d mesh virtual output queuing hol blocking fifo ddc file gds format. cdma work function gdi pae doherty power amplifier phase shifter adaptive scheduled fault detection fault library heuristic approach test minimization. garbage input/output reversible parallel binary adder/subtractor. digital-to-analog converter floating gate fet field programmability enob encoder dtmos finite impulse response (fir) parallel fir carry-look-ahead adder (cla) booth multiplier mac static and dynamic aes pipelining key pipelining search based memory double gate triple gate underlap overlap vlsi signal processing sub-threshold advanced encryption standard sub-channel mix-column bio-medical kogge-stone adder offset quadrature phase shift keying modulator and symbol-to-chip bit-to-symbol cyclic redundancy check min current substractor. wide band code division multiple access quaternary voltage mode quality of service. multiple-valued logic (mvl) noise shaping modulo-n addition and multiplication autosar voltage-controlled oscillator (vco) snr power supply. nano transistors lut & sdr multicore gps (global positioning system) neighbor aps mmic poly-thiophene pt thin film transistor tft. jpeg quantization zigzag inventive gate system-on-chip on-chip routing switch scheduler islip fft dwt ofdm constant input full subtractor stability multism bipolar junction transistor fabrication 4tdram 3tdram 3t1d dram lifting scheme vlsi architecture library free synthesis on the fly mapping critical path speed high performance (hp) itrs low power consumption cad cmos inverter encoding asynchronous design power opencircuit fault hybrid system hardware description language (hdl) 1.5 bit stage cmfb discrete wavelet transform (dwt) fault. hybrid register exchange method planar mosfet grooved mosfet concave corner corner angle deep submicron regime rfid return losses nsga-ii algorithm cnt high performance & power delay product n-bit reversible comparator transmission gate logic power delay product (pdp) combinationalcircuits design for test sub- threshold signal cmos vlsi signal identification image coding and compression image segmentation hdl computer vision statistical modelling design of experiments uvm mean error distance synthesis sv concurrency artificial intelligence sum of absolute difference parallel prefix adders brent kung adder machine learning layout congestion signal routing data compression random access scan average power ft mimo journalism state retention symmetric function * vlsi applications • visualization analog and mixed-signal mimo. vlsi communication analog and mixed signal processing emd imf face recognition multiplier audio/speech processing and coding back gate biasing precompilation watermarking télécommunications error metrics technology noc argument elaboration design error built in self-repair (bisr) module interconnections test generation fault model memory built in self-test (mbi circuit metrics compilation integer wavelet transform (iwt) residue number system (rns) lifting scheme (ls) average latency deflection routing filter bank (fb). modulo rns division galois addition and multiplication. low power vlsi circuit. binary compressor coding and transmission alu designing sctmr scan chains & sctmr. critical applications fault recovery tolerance firm ip core i2c protocols asic designing serial bus interfaces ip designing. on-chip communications image and video processing & analysis field programming gate array (fpga) application specific integrated circuit (asic) reconfigurable dsp processor software defined radio (sdr) union of graph signal flow graph (sfg) digital signal processing (dsp) processor femtocells; handover; soft handover; hard handover computer graphics and visualization nfc class ab output stage row driver column driver liquid crystal display (lcd) gamma correction image acquisition & medical image processing differential mux average power consumption pattern recognition and analysis face recognition & super-resolution imaging 3d and surface reconstruction digital & mobile signal processing analog signals. sub threshold multiplexer source coupled logic data mining techniques detection and estimation of signal parameters bme gate pass transistor logic. leakage power and switching probability. signal processing signal and image processing nonlinear signals and systems opencircuit fault. reversible decoder etc. minimal buffering dynamic threshold mos inverter dac propagation delay stuck_open stuck_short noise-margin fpga (field programmable gate array). atm (automated teller machine) hdl (hardware description language) subthreshold slope (ss) impact ionization barrier tunneling schottky-contacts analog- to- digital converter successive approximation split array digital- to- analog converter charge redistribution benchmark circuit& noise iscas85 logic gate soft error variable threshold mos inverter android api ndef formal methods in conformance • motion detection • communication networks • object detection genetic algorithm shape representation snr and low power. forward body bias multi threshold. vlsi design & communication systems verilog a nano-technology. quaternary current mode quasi-cyclic -low-density-parity-check (qc-ldpc) max richardson and urbanke lower- triangular algorithm wlan (ieee802.11n) symmetric function. low pass filter. switched-capacitor brent kung adder. regularity. iterative symmetry decomposition nano-apex emission. digital clock manager minimum transition register exchange method. multi vth swing limited interconnect circuit boostable repeater buffer insertion • depend3d and stereo imaging digital clock manager. • image segmentation delay stages • face recognition time to digital converter (tdc) gated ring oscillator (gro) pvt corners. analog data selector surface reconstruction • multi-view geometry • dsp implementation reversible decoder • distributed source coding • video signal processing carbon nanotube filed effect transistors • data mining techniques mixed signal processing power supply. 1. introduction biomedica autosar. power and delay modified booth multiplier (mbe) high performance architecture unate function boolean decomposition rca verilog hdl. cia cla rf cmoslna wimax finite impulse response (fir) filter clock power multimedia systems and devices datapath hdmi serial interface usb supply current gbps advanced verification methodology test bench. verification simulation software firefly algorithm transistor sizing co-ordinate evaluation remote sensing radix-2 fft radix-4 fft single path delay commutator pn (phase noise analy vco (voltage controlled oscillator) lpf (low pass filter) pd (phase detector) pll (phase locked loop) read/write assist circuitry standby start-up thermal hot spots kink energy level triggered flip-flop quantum-dot cellular automata (qca) counter nanometre scale. iterative dfg non-canonical. cutset retiming folding signal assessment transient noise assessment aural noise spectral exploration digital multiplier recursive encoder/decoder bulk driven. embedded architecture middleware static d flip-flop real time system dual-edge triggered vedic multiplier. anurupye nikhilam navatashcaramam dashatah urdhva tiryagbhyam shannon’s expansion theorem carry propagate adder low power vlsi design. gate diffusion input technique flash analog to digital converter resistorless mobile networks switched inverter scheme (sis) cmos 45nm read/write transitions area & power performance analysis zbt sram low drop-out low quiescent current voltage regulator risc reversible comparator signed ar ithmetic cade nce fpgas validation testbench asics noise margin electronics power clock diode adiabatic logic circuits energy web design graphic design tri-state inverters boolean algebra clustering. 1. introduction karnaugh map digital logic circuit cascode topology 1. introduction wireless sensor network rfic impedance matching power optimization education spatial wave-function switched fet digitalto- analog converter (dac) analog-to-digital converter (adc) university privacy power delay product (pdp). power evaluation mips architecture clock gating performance optimization acceptance probability carbon nanotube filed effect t digital signal processing (dsp very large scale integration lut sdr built-in self-test design for testability low power testing march algorithm embedded memories quantum-dot cellular automata current substractor voltage-controlled oscillator adaptive scheduled fault detec simulation. hybrid register exchange lector technique. cmos buffer quiescent current class-ab rail-to-rail finite state machine; parking system; virtex- 5 arithmetic circuit logic circuit parity preserving gates fault tolerant full adder von neumann landauer limit reversible computing call for papers cell library vlsics bidirectional buffer shielding journals skewing rotation mode roc vectoring mode scale free cordic systolic array articles pipeline architecture. integrated circuit minimum transition mitchell log multiplier phase lock loop (pll) delay lock loop (dll) current balanced logic (cbl) current starved inverter (csi) source coupled logic (scl) comparator flash adc. variable switching voltage threshold inverter quantization drains circuit cascaded stages and source driver database buffer circuits data stucture jldmsg (junctionless dual material surrounding gat short channel effects (sce). mrfb filter bank da based multiplication multipliers transistor stacking. acceptance probabilit 12 lead ecg acceptance probabi * low power test methodology low power circuit; carbon nanotube filed effect tr redundancy bit removal algorithm hybrid register exchange metho memoryless hrem positive feed back organic thin film transistors radio frequency identification intellectual property creating discrete cosine transform (dct array signal processing implementation internet of things technology storage and retrieval iterative symmetry decompositi high power * wireless communications * post-cmos vlsi information data mining dg-pnin tfet tunnel field effect transistor (tfet) ion/ioff ratio dg-pin tfet psnr karatsuba ofman multiplier gaussian image filter ieee754 standard floating point format look-up tables complex floating point arithmetic hardware on-chip ram processor hardware and embedded block ram * design ieee754 standard floating point format look-up tables complex floating point arithmetic hardware * post-cmosvlsi on-chip ram processor hardware matching networks s-parameters output power * wireless communications body-bia s. transmission gate gate diffusion input digital circuits leakage current . dual sub-threshold dpa resistance side channel attack risa clock- gati ng. ate automated test equipment dcl pin parametric unit variable-amplitude dithering a digital calibration mtcmos inverter v pocket dgtfet singal processing xrtl tasks/functions (xtf) emulator transactor interface (tif) universal verification component (uvc) verification ip (vip). testbench-xpress (tbx) mobile systemverilog acceleratable uvc standard co-emulation api: modelling interface (sc post-cmosvlsi field programmable gate arrays reverse converters chinese remainder theorem residue arithmetic and embedded block ram interrupt pass logic implementations logic devices low- power power delay product keywords sram layout design. deadlock recovery deadlock detection routing algorithm bus enhanced noc. aes mixcolumn vhdl code encryption razor cmos transmission logic meta-stability detector dvs lifting based scheme leakage power and switching probability field-programmable gate-array (fpga) pipeline architecture reduced bit precision fixed point scs mc-cdma uwb aca current comparator current mode static ram (sram) carbon nanotube field-effect transistor (cntfet) key generation elliptic curve cryptography mud walsh code bit/block errors. memory section addressing progressive coding memory fault transmission gates stacking effect process technology parasitic fringe capacitance. hetero-gate band-to-band tunnelling router proposed parity preserving gate constant inputs and proposed fault tolerant full a carry skip adder carry look ahead adder average power dissipation radix -2 modified booth algorithm digital signal processing spurious power suppression technique adders apa spartan-3e fast addition field programmable gate array (fpga) channel mba snm and process variations linearity gate stack dg-tfet analog multiplexer based adders effective thermal conductivity fine mesh(fm) coarse mesh(cm) heat sink source point target point logical effort integrated circuits continuous domain floorplaning hotspots 3d chips delay calculation 10 transistor serf adder svl circuit stand-by leakage power sub-micron regimes. discrete time sigma delta modulation oversampling bme gate. cic decimation filter switching activity equal / unequal rise time simultaneous switching signal skew medical imaging technology independent mapping adder topologies power saving capacitance[5] mealy and moore machines fsm decomposition [2] nanowire mosfet. interface traps hot carrier effect fixed charges channel length modulation atlas-3d crossbar routing virtex – 6 low power. virtex-5 virtex-4 verilog hdl truncated multiplier corrector. detector decoder double edge triggered(det ) d flipflop(dff ) ring-counter gated-clock first-in–first-out (fifo) gc-element analog to digital converter. fat tree tc-bc encoder tiq wishbone interface wishbone bus soc buses phase detector loop filter adpll dco reversibility miniaturization analog multipliers analog integrated circuits carbon nanotube fet data weighted averaging dynamic element matching bandpass σ∆ modulator sigma delta modulation over sampling hybrid full adder xor-xnor circuit gabor algorithm medical image very large scale integrated (vlsi)circuits vlsi circuits computer-aided design (cad) low powe sub-threshold region ultra low power threshold voltage (vt) back gatebiasing. independent-gate (ig) gate workfunction dual-metal gate (dmg) rf switch wireless network radio-frequency low noise amplifier advanced design system image compression. vlsi architectures lifting schemes discrete wavelet transform neural network architecture back propagation algorithm ultra-low voltage asynchronous logic delay-insensitive schmitt-triggered tmr input third order intercept point (iip3) shunt-series peaking dual source degenerated current reuse pdp full adder & vlsi. carbon nano-tube carbon nano-tube field effect transistor low power full adder stacking technique self cascode folded cascode ota meter count efficiency loom machine analog and mixed signal (ams) cmos ring oscillator (ro) integrated circuit (ic) phase noise moore’s law. gain trans-conductance center frequency of oscillation silvaco tcad tool dmg mosfet gate leakage sram and vlsi. cmos logic hysteresis. virtuoso cadence write-ability read stability n-curve interconnects silicon-on-insulator coupling fpga spartan 3 development board vending machine cnfet fsm biological and wireless communications full-adder cell basic gates. biological bus-invert inductance effects rsa. modular multiplication sign estimation technique sign detection carry-save adder efficient architecture carry select adder. carry increment adder carry save adder ptl multi-channel latch test time double edge triggered flipflop scanflop video data interface(s) universal verification component(uvc) register and memory model ip-xact incisive software extension (isx) virtual register interface (vri) verification abstraction layer(val) carbon nanotube mulitple valued logic vlsi. uvm-ml. reversible logic gates toffoli gates partial products future computing. navigation rtl schematic low power multipliers column bypass multiplier 2-d bypass multiplier reduced switching activity fast fourier transform zero padding. fsm optimization test bist generator multiple outputs high performance voltage-controlled oscillator (vc phase-locked loop (pll) eda tool. memory effect system verilog vco baseband pll charge pump pll pll redundancy hardware controller fault tolerance high frequency current buffer compensation cmos analog circuit mobility & mole fraction. drain current channel thickness biaxial strained flash analog to digital converter sampling switch peak power register interface(s) track and hold circuit scan chain. synthesis constraints data synchronization reconfigurable computing domain-specific architecture reconfigurable architecture coarse-grained fabric test vector compaction iscas atpg pareto-optimal fine-grained dvs galois addition and multiplication branch-and- bound low power vlsi bus transition reduction arithmetic coding compressed code systems. computer-aided design (cad exclusive -or equivalence implication inhibition inverse. nano scale electronic design and applications face and gesture filter design and structures adaptive filters • image acquisition & medical image processing state encoding logic optimization minority function cntfet technology logic gates pbch pmch pdcch pdsch pcfich mbsfn mbms memory testing error correction codes matrix codes multiple error detection combinational circuits multiple error correction. dual-threshold subthreshold leakage gate oxide tunneling leakage current. co-ordinate evaluation. crypto processor prime field binary field. gals ternary tree network synthesis. total harmonic distortion design vlsi circuits computer-aided design (cad) fault-tolerance emerging technologies post-cmos etc) nano electronics biological and quantum computing intellectual pro gate all around(gaa) tg finfet discrete cosine transform (dct) high k gate oxide silicon-on-insulator(soi) short channel effect radio frequency identification rfid organic thin film transistors otft serf adder subthreshold slope positive feed back adiabatic logic 3-d sentaurus tcad tool. two phase clocked energy recovery split-level diode based logic lphs (low power high speed). rtd spice threshold tlg track swsfets march c- modified march c- algorithm concurrent technique complexity traditional march tests. buffer dynamic circuit precharge pulse barrier lowering cylindrical surround gate (csg) mosfet fringing field process and device simulation sces corba
soi finfets merit factor polyphase sequence quaternary sequence ternary sequence pulse compression psrr temperature coefficient bgr sub threshold slope tcad gilbert cell noise spectral density channel routing moscap dynamic circuits majority-not gate pseudo nmos dual rail domino logic static cmos logic comparator. interval arithmetic floating-point wireless application. rf design low noise amplifier (lna) 90nm technology bics iddq testing resistive path short (bridging) defect operational amplifier (op amp) opamp sharing nano-cmos technology areaoptimization. power ooptimization turbo decoder turbo encoder single/multiple input signature register linear feedback shift register tool computer-aided design manhattan routing model memoryless hrem. vcg & merging. delayed flip-flop (d-ff) phase frequency detector (pfd) redundancy bit removal algorithm true signal phase clock (tspc) divider (div) voltage controlled oscillator (vco) analog and mixed-signal circuit formal methods in conformance testing charge pump (cp) low pass filter (lpf) noc routing diametrical 2d mesh routing on-chip communication forbidden pattern free micron coupling capacitance parasitic extended xy flash adc xor gate based encoder analog to digital converter (adc) bridge full adder. hybrid xor-xnor circuit very large scale integrated (vlsi) circuits power-delay product (pdp) • image acquisition & medical image processing • p