Sougata Bhattacharjee

Sougata Bhattacharjee Sougata Bhattacharjee is an influencer

Samsung (SSIR) | Ex - Intel | 6 times TEDx Speaker | ASIC Verification | Proficient in SV, UVM, OVM, SVA, Verilog | Functional Safety ISO 26262 Certified | Paper publication at VLSI Conferences

Bengaluru, Karnataka, India
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About

A competent professional with a total work experience of around 12 years in ASIC Design and Verification and the experience is broadly classified into the following categories:

✔️ Expertise in developing testbench infrastructure in UVM for IP and subsystem-based design.
✔️ Expertise in Coding and developing UVCs like Driver, Monitor, Sequencer, Agent, and Scoreboard. Experience in writing directed and random Test Scenarios to make sure there are no bugs in the design and also ensures the verification is complete.
✔️ Experience in creating the Verification Plan, Test Plan, Feature extraction plan, and Assertion plan.
✔️ Hands-on experience in HDVL like System Verilog and Pre-Silicon Verification.
✔️Good in RTL Design Concepts using Verilog.
✔️ Experience in writing Assertions and have experience in Assertion Based Verification (ABV). Experience in Functional and Code Coverage closure by covering uncovered bins.
✔️ Hands-on Experience and good understanding of Protocols and IP like AXI3, AXI4, AHB, AHB5, ATB, APB, LPDDR4, and I2C.
✔️ Expertise in Integrating Testbenches and Writing test cases for GPU and 5G Modem.
✔️ Experience in debugging complex logic and finding the root cause of the failure.
✔️ Expertise in Functional Safety Verification (FuSa) and handling multiple Safety mechanisms (SM) to reach adequate Diagnostic Coverage (DC) for reaching the ASIL target.
✔️ Paper published related to ASIC Design and Verification in prestigious conferences.
✔️ Regression management and Bug closure.
✔️ Experienced with X propagation checks to find bugs within the design.

Additional Skills & Interests:

➡️ Having good knowledge of creating Python test benches using cocotb
➡️ PSS modeling
➡️ Delivered multiple Tech Talks related to ASIC Verification and VLSI at renowned colleges and Institutes including IIT Ropar, IIT BHU, IIT Tirupati, VIT Vellore, RV College Bangalore, SKF, and GIBS.

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Experience

  • Samsung Semiconductor Graphic

    Senior Staff Engineer(ASIC Verification)

    Samsung Semiconductor

    - Present 3 years 10 months

    India

    [1] Expertise in developing UVM testbench infrastructure from scratch for IP / Subsystem-based design along with hands-on experience in coding the UVCs like Driver, Monitor, Sequencer, Agent, Scoreboard, etc. Also responsible for creating Test scenarios (Directed, Random, Corner, Stress) to verify a design thoroughly to ensure that there is zero Silicon bugs without compromising quality.

    [2] Currently leading several IP's and responsible for project execution from the start…

    [1] Expertise in developing UVM testbench infrastructure from scratch for IP / Subsystem-based design along with hands-on experience in coding the UVCs like Driver, Monitor, Sequencer, Agent, Scoreboard, etc. Also responsible for creating Test scenarios (Directed, Random, Corner, Stress) to verify a design thoroughly to ensure that there is zero Silicon bugs without compromising quality.

    [2] Currently leading several IP's and responsible for project execution from the start (Specification understanding to Coverage Closure), delivering multiple projects within the stipulated time and ensuring quality. Also responsible for creating the Assertion plan, driving the execution strategy, writing the Verification Plan and Testplan for project execution, and also Code / Functional Coverage Closure

    [3] Drive innovation and mentor junior colleagues within the team. Responsible for bringing innovation to the DV methodology to reduce time and effort for coding the testbench and finding more RTL bugs.

    [4] Published papers at multiple International Conferences like DVCON, DAC, CDNLive, VDAT, etc.

    [5] Functional Safety ISO 26262 Level 1 Certified and part of a Fault Campaign project. Responsible for injecting the faults, capturing faults, and increasing Diagnostic Coverage through several safety mechanisms (SM), executed SRF to increase the DC in comparison with Full fault space.

    [6] Leverage Portable Stimulus Standard (PSS) for Coverage and constraints offloading.

    [7] Experience in leading and managing team members for IP Verification projects and meet all the required deadlines for project execution within the stipulated time. Responsible for taking ownership of projects from scratch and also maintaining Legacy projects by adding scenarios for new features.

    Expertise in below languages and Methodologies:
    1. UVM
    2. SystemVerilog
    3. SystemVerilog Assertions(SVA)
    4. Verilog
    5. Functional Safety (FuSa)
    6. PSS

  • Intel Corporation

    Intel Corporation

    3 years 9 months

    • Intel Corporation Graphic

      Pre - Si Verification Engineer

      Intel Corporation

      - 6 months

      Bangalore Urban, Karnataka, India

    • Intel Corporation Graphic

      Component Design Engineer

      Intel Corporation

      - 2 years 1 month

      India

      Working on GPU Verification

    • Intel Corporation Graphic

      Modem Verification Engineer

      Intel Corporation

      - 1 year 4 months

      Bengaluru Area, India

      -> Worked on complete Testbench Setup from Scratch for Verification of Registers of 5G Modem through RAL.
      -> Debugged Testcases and created Verification Environment.
      -> Worked on Clock control Unit and Reset Control Unit and modify Verification Environment,Created TestPlan and execute the Testcases along with all the implemented features.
      -> Meet Coverage goals of all the related IP's and Sub blocks

  • Sankalp Semiconductor Graphic

    Senior Asic Verification Engineer

    Sankalp Semiconductor

    - 11 months

    Bangalore

    -> Worked on APB-SPI enabled slave Verification Environment.
    -> Worked on feature implementation of HDMI 2.1 and writing Testcases.

  • Mindtree Graphic

    Senior Engineer, VLSI

    Mindtree

    - 1 year 6 months

    Bengaluru Area, India

    -> Responsible for writing UVM/OVM based verification environment for several SOC & IP based design
    -> Debugging several TestCases and environmental changes wrt UVM/OVM for SOC Verification.
    -> Responsible for writing Assertion to verify specific functionality of design.
    -> Responsible for writing Test Cases in SystemVerilog for complex IP's.
    -> Enable Code Coverage Report and able to locate and modify the design according to needs.
    -> Responsible for writing…

    -> Responsible for writing UVM/OVM based verification environment for several SOC & IP based design
    -> Debugging several TestCases and environmental changes wrt UVM/OVM for SOC Verification.
    -> Responsible for writing Assertion to verify specific functionality of design.
    -> Responsible for writing Test Cases in SystemVerilog for complex IP's.
    -> Enable Code Coverage Report and able to locate and modify the design according to needs.
    -> Responsible for writing TestPlan and also fix the bug related to RTL

  • Uniquify Inc Graphic

    VLSI Engineer

    Uniquify Inc

    - 2 years 4 months

    Pune Area, India

    -> Associated with the project on Modelling and Verification of LPDDR4 IP in which my role includes
    writing of verification model in verilog,implemented all the timing parameters related to LPDDR4,wrote several Test Cases(SystemVerilog/TCL/Verilog) to evaluate the correctness of timing.Also wrote Test Cases for Read/Write/Masked write.Documented various Test Scenario and create Test Plan.
    -> Responsible for understanding of Verilog-TCL bridging.
    -> Also executed Projects like…

    -> Associated with the project on Modelling and Verification of LPDDR4 IP in which my role includes
    writing of verification model in verilog,implemented all the timing parameters related to LPDDR4,wrote several Test Cases(SystemVerilog/TCL/Verilog) to evaluate the correctness of timing.Also wrote Test Cases for Read/Write/Masked write.Documented various Test Scenario and create Test Plan.
    -> Responsible for understanding of Verilog-TCL bridging.
    -> Also executed Projects like SEIO/DIO Decoder for selecting DDR modes,AMBA AXI4 protocol and Vx1 Transmitter and Receiver.
    -> Responsible for writing Test Plan and documenting Test Scenarios.
    -> Understanding of OOPS and use of Multithreading in TCL.
    -> Responsible for Creation of Verification Environment and Testbenches.
    -> Hands on Experience in RTL coding using Verilog.

Education

  • Birla Institute of Technology and Science, Pilani Graphic

    Birla Institute of Technology and Science, Pilani

    M.Tech Microelectronics

    -

    Received the highest Grade "EXCELLENT" in my Dissertation i.e. the project work titled "Exploration and Usage of Scaling Algorithms for Image Processing Applications"

  • Centre for Development of Advanced Computing (C-DAC) Graphic

    Centre for Development of Advanced Computing

    PG Diploma in VLSI DESIGN VLSI 70.26%(Grade - A)

    -

    Subjects:
    1.Advanced Digital Design.
    2.VHDL
    3.Verilog.
    4.System Architecture.
    5.Linux Shell Scripting.
    7.CMOS.
    8.System Verilog .
    9.C-Programming
    10.MATLAB-SIMULINK

    Tools Used:-
    Modelsim, Xilinx ISE, QuestaSim, Leonardo Spectrum, Tanner, ISIM, Microwind, Linux

  • G.H. Raisoni College of Engineering(GHRCE), Nagpur Graphic

    GH Raisoni Engineering College, Digdoh

    B.E(E & TC) Electronic and Telecommunication Engineering

    -

Licenses & Certifications

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Volunteer Experience

  • CRY - Child Rights and You Graphic

    Volunteer

    CRY - Child Rights and You

    - Present 5 years 1 month

    Children

    1) Involved in activities like Translation of Content from English to Local Regional Language and release the content in Time.
    2) Involved in Social Media Campaign

Skills

Publications

  • Leveraging Statistical Random Fault (SRF) Sampling for Efficient Functional Safety with Reduced Efforts

    DVCON INDIA 2024

    The paper talks about the Statistical Random Fault (SRF) technique used in the Fault Campaign and how it helps to achieve maximum diagnostic coverage with minimum time and effort to reach the desired ASIL target. The paper also draws a comparative analysis of how SRF fares better in achieving the desired results than the Full fault campaign.

  • Formal Assurance of Connectivity and Data Integrity for Efficient IP Verification

    VDAT 2024

    The paper emphasizes the adoption of Formal Verification to enhance vulnerability and address system reliability. The integration of reverse connectivity and Assertion based verification techniques has been used to check data integrity and reliability.

  • Leveraging Formal Methodologies for Connectivity and Data Integrity

    Cadence Connect

    The paper discusses the connectivity checks through Formal Verification for a given RTL module.

  • Leveraging several automated techniques and methodologies for faster coverage closure and design sign off

    DAC USA 2024

    The motivation of this paper is to introduce several automated techniques which saves iterations and time for Coverage Closure. Further, the Poster also talks about implementation of PSS and its usage in Coverage sign off with reduced efforts.

    See publication

  • Leveraging Several Functional Safety Methodologies (Full Faults and SRF) to enhance Design Quality in Automotive IC

    DVCON USA 2024

    The paper discusses about several functional safety flows and how Diagnostic Coverage can be achieved in a full fault space. Moreover, the paper also elaborated about SRF and how it's beneficial in reducing the number of iterations and achieve the required DC with minimum time and effort.

    See publication

  • Counterintuitive approaches to have better communication between UVM and Python for registers with Single controlling algorithm.

    DVCON INDIA

    The motivation behind writing this paper is to build a Single Controlling algorithm with additional customization features to enhance the performance of Register verification using UVM and Python. Along the way, the paper also describes several methods as to how to make proper interaction between UVM and Python.

    See publication

  • Novel approach to improve the process of register verification in UVM

    DAC USA 2023

    The idea of the paper is to make the register and memory verification process more efficient, thorough, and time-bound and due to this two new algorithms have been implemented in addition to the inbuilt sequences of UVM. Among the novel methods that are implemented, one is the March-Bash algorithm and the other one is the modified register access sequence.

    See publication

  • Memory Verification in UVM made simpler using Algorithms and the role of vManager

    CadenceLive Europe

    Like Register Verification, Memory Verification is one of the most important phases of Verification in both SOC and IP-based Design. Although both look similar there are certain differences:

    [1] The access methods for register access are read and write while the access methods
    for memory access are read, write, burst_read, and burst_write as the memory model contains a range of addresses.

    [2] The concept of shadowing is not applicable to memory as they are not able to hold…

    Like Register Verification, Memory Verification is one of the most important phases of Verification in both SOC and IP-based Design. Although both look similar there are certain differences:

    [1] The access methods for register access are read and write while the access methods
    for memory access are read, write, burst_read, and burst_write as the memory model contains a range of addresses.

    [2] The concept of shadowing is not applicable to memory as they are not able to hold state
    With the increasing complexity of the Design and keeping the time-to-market in mind, verifying a huge chunk of Memory within the specified duration using hard-coded address and nonautomated techniques is a cumbersome task.

    This paper addresses the above challenges in Memory verifications and provides different techniques and Algorithms implemented in the existing Testbench to increase productivity and reduction of debug effort and code length and how Vmanager helps to reduce the burden of Regression management.

    See publication

  • Leveraging RAL and alternate automation (cocotb) techniques to improve register verification in UVM

    DVCON INDIA

    The paper explains the different inbuilt sequences of Register Abstraction Layer (RAL) used within the UVM infrastructure, and a comparison is being drawn on how this improves the performance of the Testbench with the increasing complexity of the Design and keeping the time-to-market in mind.
    One more technique described in this paper is about cocotb (co-routine co-simulation) based environment which further simplifies the automation of Register verification in the Testbench.

    See publication

  • Advance Usage of SystemVerilog Construct in Verification Environment

    Cadence - CDNLive Event

    The presentation mostly revolve around interface construct in systemverilog, multiple inheritence and how it reduces the debugging effort in verification environment. Also introduces properies of composition and constraint to make the debugging much more easier.

    See publication
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Courses

  • PG Diploma in VLSI

    -

Projects

  • Exploration and Usage of Scaling Algorithms for Image Processing Applications

    -

    The idea of the project is to design a generic architecture that acts as a hardware accelerator and comprises the capabilities of image scaling algorithms like Bilinear, Nearest Neighbour and Box Filter. The generic architecture has the capabilities of a DMA controller and in addition to this contains a scaler unit that helps in resizing images, Bilinear scaling, noise and interference reduction, and also provides the best downscaled images.

    The scaler unit acts as a hardware accelerator…

    The idea of the project is to design a generic architecture that acts as a hardware accelerator and comprises the capabilities of image scaling algorithms like Bilinear, Nearest Neighbour and Box Filter. The generic architecture has the capabilities of a DMA controller and in addition to this contains a scaler unit that helps in resizing images, Bilinear scaling, noise and interference reduction, and also provides the best downscaled images.

    The scaler unit acts as a hardware accelerator which helps in memory-to-memory transfers. The project aims towards building the generic architecture by including Box filter along with Bilinear, NN so that it supports more data formats and features keeping in mind the area and speed requirement which are the main aspect of SOC based design. The architecture supports both NPU data and image format.

    Finally the design is verified with the help of UVM infrastructure testbench and creating proper stimulus to check whether the design is verified properly and working as per the specification.

Honors & Awards

  • Employee of the Month (EOM)

    Samsung Semiconductor

    Received the award to drive Functional Safety and PSS within the team and executed the project successfully and also due to publishing several papers at various International Conferences

  • Spot Award

    Samsung

    Receives the Spot Award for publishing Papers at several VLSI Conferences

  • Quality Recognition Award in Intel

    Intel, Graphics

    Ramping up the activities quickly, Developing the Test plan for the Power Management IP, execute the flows and worked closely with the Architect and the Designer to close on majority of flows.File the bugs and also validate the same.

  • Recognition award in Intel

    Intel

    Participated and progress through the final Round in IDAN Quiz fest 2020 and considered as IDAN Ambassador

  • Certificate of Appreciation Award at Intel

    Intel

    Created the RAL flow of UVM from scratch and execute all the Register based tests

  • Quora Top Writer

    Quora

    Won the Top writer Quora award in 2018 for providing good content mostly in the field of VLSI focussing on ASIC Verification.

Languages

  • English

    Full professional proficiency

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