Connected by Arteris | LinkedIn Edition #3
Welcome to the third edition of our monthly newsletter 👋
Innovation never slows down — and neither does our team at Arteris. In this edition, we are spotlighting the breakthroughs redefining how system-on-chip (SoC) designs are developed, optimized, and brought to market. From 10x faster interconnect creation with our FlexGen smart NoC IP to closing the hardware-software gap with Magillem Registers, we’re solving the toughest design challenges facing semiconductor teams.
Whether you're optimizing RISC-V International architectures for AI workloads or evaluating automation for chiplet design, this edition brings valuable insights and resources to help you accelerate your path to market. Dive into our product updates, expert perspectives, podcast conversations, and upcoming events — including an opportunity to meet us at DAC, The Chips to Systems Conference in San Francisco.
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Product Spotlight
Smart NoC IP — Revolutionizing System-on-Chip Design
At ChipEx in Tel Aviv, Israel, our team presented how products such as FlexGen smart NoC IP from Arteris can bring unprecedented productivity improvements and quality of results. Smart NoC generation is 10x faster than traditional NoC flows, shortening SoC or chiplet iterations from weeks to days for design efficiency.
Industry Expertise
Boosting RISC-V SoC performance for AI and ML applications
Modern SoC designs are more innovative and complex than ever, therefore RISC-V-based designs must address challenges like interoperability, hardware-software integration, and safety certifications to meet stringent performance and reliability standards.
Arteris Bridges Hardware-Software Gap with New SoC Integration Automation Software
The hardware-software interface, or HSI, plays a central role in a modern chip design, bridging the physical hardware and the software and firmware that executes on top of it. We introduced the latest electronic design software, Magillem Registers, to cut through this complexity.
Automating NoC Design Masters SoC Complexity
In this podcast, Sally Ward-Foxton, Senior Reporter at EE Times | Electronic Engineering Times, sat down with Michal Siwinski, CMO at Arteris, to discuss the challenges of designing efficient interconnects with the increasing integration of AI workloads. They also discuss why NoC design automation products are no longer a nice-to-have but rather a necessity for chip designers, which companies have already benefited, along with Michal's thoughts on what the future holds for NoC technology.
Hiring
We're Hiring Engineers
If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands — and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter. We're looking for talented engineers to join our team.
Upcoming Events
Meet the Arteris team in person at DAC, the chip to systems conference in San Francisco.
Visit us at Booth #2529 to discover how Arteris interconnect IP and SoC integration automation can help you design smarter, faster, and with more confidence. Book a meeting with the team.
🎁 Bonus for early birds: the first 100 booth visitors who mention this email, will receive a special gift from Arteris – while supplies last!
Don't miss our speaking session! Hear from our product experts Andy Nightingale & Ashley Stevens on the opportunities and challenges that come with chiplets at 4:15pm, June 24th at the EE Times | Electronic Engineering Times Chiplets Pavilion, Booth #2308.
📌Prefer to receive this newsletter straight into your inbox? Subscribe here on LinkedIn or sign up via this form.