VHDL MODELING.pptx
- 1. VHDL MODELING Group Members:- 1) Rajat Chaskar 2) Abhishek Ingale 3) Onkar lawate 4) Balaji Kapse
- 2. Contents 1) Introduction 2) VHDL SYNTAX And Code
- 3. Introduction • VHDL is a powerful language that allows for the creation of complex hardware designs that can be simulated and tested before being implemented in hardware. • VHDL modeling is a language-based approach to designing digital systems. It is used to create hardware designs that can be implemented in hardware such as FPGAs and ASICs.
- 4. VHDL SYNTAX And Code Different Types of VHDL Modelling Styles:- The architecture of VHDL code is written in three different coding styles : 1) Dataflow Modelling 2) Behavioral Modelling 3) Structural Modelling The Design and implemention of the AND and OR logic gates using VHDL (VHSIC Hardware Description Language) programming languages.
- 5. • Dataflow modeling provides the means of describing combinational circuits by their function rather than by their gate structure. Dataflow modeling uses a number of operators that act on operands to produce the desired results. • Behavioral modeling represents digital circuits at a functional and algorithmic level. It is used mostly to describe sequential circuits, but can be used to describe combinational circuits. 1) Dataflow Modelling:- 2) Behavioral Modelling:-
- 6. In structural modeling the components of the system are listed and the interconnections between them are specified. In this modeling the designs are described in the form of block diagrams. Components represented by blocks are interconnected by lines representing signals. 3) Structural Modelling:-