Introduction to VHDL
Download as PPTX, PDF1 like149 views
The document provides an introduction to VHDL, a hardware description language standardized for high-speed integrated circuits. It outlines key concepts including VHDL invariants, basic structures, data objects, operators, and essential syntax elements like entities, architectures, and packages. The content serves as a foundational overview for understanding how to effectively use VHDL in circuit design and simulation.
![Basic structures in VHDL…
iii. Package
• The primary purpose of a package is to collect
elements that can be shared among two or more
design units.
• Syntax:
12/22/2019 Introduction to VHDL 23
Package package_name is
package_declarative_item
End package_name;
package body package_name is
package_declarative_item
End package_name];](https://image.slidesharecdn.com/vhdl21-191222103802/85/Introduction-to-VHDL-23-320.jpg)
Introduction to VHDL
- 2. Agenda • Introduction • VHDL Invariants • Basic structures in VHDL • Data objects • VHDL operators • Sequential statements • Concurrent statements • Reference 12/22/2019 Introduction to VHDL 2 Reading Assignment
- 3. Introduction V H D L Hardware Description Language V H S I C High Integrated Circuit Very • Designed to develop a very high speed integrated circuit. Speed 12/22/2019 Introduction to VHDL 3
- 4. Introduction… • It is an industry standard language used to describe hardware from the abstract to concrete level. • It is human and machine readable • It supports both behavioral and structural description of a system • It has a standard package • It support both synchronous and asynchronous timing model 12/22/2019 Introduction to VHDL 4
- 5. VHDL Invariants • Qualities of VHDL: • It is not case sensitive • Example: • It is not sensitive to white space (spaces and tabs) • Example: • Comments in VHDL begin with “--“ (two consecutive dashes) • Example: 12/22/2019 Introduction to VHDL 5 Dout <= A and B; doUt <= a AND b; nQ <= In_a or In_b; nQ <= in_a OR in_b; -- This next section of code is used to blah-blah
- 6. VHDL Invariants… • Qualities of VHDL… • VHDL is relatively lax on its requirement for using parenthesis • Example: • every VHDL statement is terminated with a semicolon 12/22/2019 Introduction to VHDL 6 if x = ‘0’ and y = ‘0’ or z = ‘1’ then -- statements; End if; if ( ((x = ‘0’) and (y = ‘0’)) or (z = ‘1’) ) then -- statements; End if;
- 7. VHDL Invariants… • Qualities of VHDL… • the VHDL language contains if, case, and loop statements • Note: 12/22/2019 Introduction to VHDL 7 • Every if statement has a corresponding then component • Each if statement is terminated with an “end if” • If you need to use an “else if” construct, the VHDL version is “elsif” • Each case statement is terminated with an “end case” • Each loop statement has a corresponding “end loop“ statement
- 8. VHDL Invariants… • Qualities of VHDL… • Identifiers: • the name given to discern various items in VHDL • Note: 12/22/2019 Introduction to VHDL 8 • Identifiers should be self-commenting • Identifiers can be as long as you want (contain many characters). • Identifiers can only contain some combination of letters (A-Z and a-z), digits (0-9), and the underscore character (‘_’) • Identifiers must start with an alphabetic character • Identifiers must not end with an underscore and must never have two consecutive underscores
- 9. VHDL Invariants… • Qualities of VHDL… • Identifiers… • Example: 12/22/2019 Introduction to VHDL 9
- 10. Basic structures in VHDL • Basic building blocks of a VHDL description can be classified into five groups: i. Entity ii. Architecture iii. Package iv. Configuration v. Library 12/22/2019 Introduction to VHDL 10
- 11. Basic structures in VHDL… i. Entity: • provides a method to abstract the functionality of a circuit description to a higher level (i.e. does not provide information about how a component is implemented). • Syntax: 12/22/2019 Introduction to VHDL 11 entity entity_name is port ( port_name : mode data_type; port_name : mode data_type; port_name : mode data_type ); end entity_name; Mode: specifies the direction of a port signal. Data_type: specifies the data type of a port,
- 12. Basic structures in VHDL… i. Entity… • Port modes: • In : indicates that the signal is an input • Out: indicates that the signal is an output of the entity whose value can only be read by other entities that use it • Inout: the signal can be an input and output • Buffer: indicates that the signal is an output of the entity whose value can be read inside the entities architecture 12/22/2019 Introduction to VHDL 12
- 13. Basic structures in VHDL… i. Entity… • Types: • A built-in or user-defined signal type. 12/22/2019 Introduction to VHDL 13 Boolean: An enumeration type with two values, false and true Bit: An enumeration type with two values, ‘0’ and ‘1’. Character: any printing character Integer: Represents positive and negative numbers. Range is specified from -2,147,483,647 to +2,147,483,647 . Natural: Subtype of integers used for representing natural (non- negative) numbers. Positive: Subtype of integers used for representing positive (non- negative, nonzero) numbers.
- 14. Basic structures in VHDL… 12/22/2019 Introduction to VHDL 14 i. Entity… • Types… Bit_vector: Represents an array of BIT values. String: An array of CHARACTERs. A STRING value is enclosed in double quotation marks. REAL: Represents real numbers. Range is -1.0E+38 to +1.0E+38. Physical type Time: Represents a time value used for simulation. Std_logic, Std_ulogic, Std_logic_vector, Std_logic_uvector: can have nine values to indicate the value and strength of a signal.
- 15. Basic structures in VHDL… i. Entity… • Types… • The nine std_logic types are: 12/22/2019 Introduction to VHDL 15 Type STD_LOGIC is ( ‘U’ --Uninitialized ‘X’ --Forcing unknown ‘0’ --Forcing low ‘1’ --Forcing high ‘Z’ --High impedance ‘W’ --Weak unknown ‘L’ --Weak low ‘H’ --Weak high ‘_’ --Don’t care ) ;
- 16. Basic structures in VHDL… i. Entity… • Example: 4 X 1 Multiplexer 12/22/2019 Introduction to VHDL 16 entity mux4_8 is port ( a_data : in std_logic_vector(0 to 7); b_data : in std_logic_vector(0 to 7); c_data : in std_logic_vector(0 to 7); d_data : in std_logic_vector(0 to 7); sel1,sel0 : in std_logic; a_st_1, a_st_2 : out std_logic_vector(0 to 7)); end mux4_8;
- 17. Basic structures in VHDL… ii. Architecture: • Specifies how the circuit operates and how it is implemented (i.e. it describes what the circuit actually does) • Syntax: 12/22/2019 Introduction to VHDL 17 Architecture architecture_name of entity_name is architecture_declarative_part begin --statements End architecture_name; - Components - Signals - Constant - Function - Procedure - Type etc.
- 18. Basic structures in VHDL… ii. Architecture… • It defines the relationships between the inputs and the outputs of a design entity which may be expressed in terms of : A) Behavioral style B) Data flow style C) Structural style 12/22/2019 Introduction to VHDL 18
- 19. Basic structures in VHDL… ii. Architecture… A) Behavioral architecture • specifies what a particular system does in a program like description using processes, but provides no details as to how a design is to be implemented. • Example: 12/22/2019 Introduction to VHDL 19 architecture behavior of FULL_ADDER is Begin process (A, B, CIN) Begin if (A=‘0’ and B=‘0’ and CIN=‘0’) then SUM <= ‘0’; COUT <=‘0’; Name of the Entity Name of the Port
- 20. Basic structures in VHDL… ii. Architecture… A) Behavioral architecture… • Example: 12/22/2019 Introduction to VHDL 20 elsif (A=‘0’ and B=‘0’ and CIN=‘1’) or (A=‘0’ and B=‘1’ and CIN=‘0’) or (A=‘1’ and B=‘0’ and CIN=‘1’) then SUM <= ‘1’;COUT <=‘0’; elsif (A=‘0’ and B=‘1’ and CIN=‘1’) or (A=‘1’ and B=‘0’ and CIN=‘1’) or (A=‘1’ and B=‘1’ and CIN=‘0’) then SUM <= ‘0’; COUT <=‘1’; elsif (A=‘1’ and B=‘1’ and CIN=‘1’) then SUM <= ‘1’;COUT <=‘1’; end if ; end process ; end behavior ; Signal assignment
- 21. Basic structures in VHDL… ii. Architecture… B) Data flow architecture • specifies a system as a concurrent representation of the flow of control and movement of data. • Example: 12/22/2019 Introduction to VHDL 21 architecture DATAFLOW of FULL_ADDER is signal S : BIT ; Begin S <= A xor B ; SUM <= S xor CIN after 10ns ; COUT <= (A and B) or (S and CIN) after 5ns ; end DATAFLOW ;
- 22. Basic structures in VHDL… ii. Architecture… C) Structural architecture • defines the structural implementation using component declarations and component instantiations. • Example: 12/22/2019 Introduction to VHDL 22 architecture STRUCTURE of FULL_ADDER is component HALF_ADDER port ( L1, L2 : in BIT ; CARRY, SUM : out BIT ) ; end component ; component OR_GATE port ( L1, L2 : in BIT ; O : out BIT ) ; end component ; signal N1, N2, N3 : BIT ; Begin HA1 : HALF_ADDER port map (A, B, N1, N2) ; HA2 : HALF_ADDER port map (N2, CIN, N3, SUM) ; OR1 : OR_GATE port map (N1, N3, COUT) ; end STRUCTURE ;
- 23. Basic structures in VHDL… iii. Package • The primary purpose of a package is to collect elements that can be shared among two or more design units. • Syntax: 12/22/2019 Introduction to VHDL 23 Package package_name is package_declarative_item End package_name; package body package_name is package_declarative_item End package_name];
- 24. Basic structures in VHDL… iii. Package… • Example: 12/22/2019 Introduction to VHDL 24 Package my_pkg is constant delay : time := 10ns ; end my_pkg ; Variable assignment
- 25. Basic structures in VHDL… iv. Configuration • used to provide fast substitutions of component instances of a structural design. • Syntax: 12/22/2019 Introduction to VHDL 25 Configuration configuration_name of entity_name is {configuration_declarative_part} For block_specification {use_clause} {configuration_item} End for;
- 26. Basic structures in VHDL… iv. Configuration… • Example: 12/22/2019 Introduction to VHDL 26 configuration FADD_CONFIG of FULL_ADDER is for STRUCTURE for HA1, HA2 : HALF_ADDER use entity burcin.HALF_ADDER(STRUCTURE) ; for OR1 : OR_GATE use entity burcin.OR_GATE ; end for ; end FADD_CONFIG ; Name of the Entity Name of the architecture Library
- 27. Basic structures in VHDL… v. Library • Used as a place where the compiler stores information about a design project. • It contains the following library units: • Packages • Entities • Architectures • Configurations 12/22/2019 Introduction to VHDL 27
- 28. Basic structures in VHDL… V. Library • Used as a place where the compiler stores information about a design project. • Example: 12/22/2019 Introduction to VHDL 28 Library ieee; Use ieee.std_logic_1164.all Use ieee.std_logic_arith.all Use ieee.std_logic_unsigned.all Indicates to use all of the ieee.std_logic_u nsigned package package
- 29. Data objects • An object which holds both a name (associated identifier) and a specific type • Types: 1. Constants • Have a single value of a given type and can not be changed during the simulation. 2. Variables • Can have a single value, but it can be updated using a variable assignment statement. 3. signals • can be interpreted as wires or busses in an actual circuit. 12/22/2019 Introduction to VHDL 29
- 30. Data objects… 12/22/2019 Introduction to VHDL 30
- 31. VHDL operators • Used to operate a signal, variable, and constant. • Operators in VHDL are grouped into seven different types: logical, relational, shift, addition, unary, multiplying, and “others” 12/22/2019 Introduction to VHDL 31
- 32. 12/22/2019 Introduction to VHDL 32
- 33. Reference 1. Sjoholm, S. and Lindh, L., 1997. VHDL for Designers. Prentice Hall PTR. 2. Skahill, K., 1996. VHDL for programmable logic. Addison-Wesley Longman Publishing Co., Inc.. 3. Holland, B., Vacas, M., Aggarwal, V., DeVille, R., Troxel, I. and George, A.D., 2005, September. Survey of C-based application mapping tools for reconfigurable computing. In Proceedings of the 8th International Conference on Military and Aerospace Programmable Logic Devices (MAPLD 2005), Washington, DC, USA (September 2005). 4. Sagahyroon, A.A., 2000. From AHPL to VHDL: A course in hardware description languages. IEEE Transactions on Education, 43(4), pp.449- 454. 5. Brown, S., 2010. Fundamentals of digital logic design with VHDL. 6. Navabi, Z., 1997. VHDL: Analysis and modeling of digital systems. McGraw-Hill, Inc.. 7. Camposano, R. and Tabet, R.M., 1988. Design representation for the synthesis of behavioral VHDL models. IBM Thomas J. Watson Research Division. 12/22/2019 Introduction to VHDL 33
- 34. Reference… 8. Camposano, R. and Tabet, R.M., 1988. Design representation for the synthesis of behavioral VHDL models. IBM Thomas J. Watson Research Division. 9. Ferrandi, F., Fummi, F. and Sciuto, D., 1998, October. Implicit test generation for behavioral VHDL models. In Test Conference, 1998. Proceedings., International (pp. 587-596). IEEE. 10. Micheli, G.D., 1994. Synthesis and optimization of digital circuits. McGraw-Hill Higher Education. 11. Navabi, Z., 1997. VHDL: Analysis and modeling of digital systems. McGraw-Hill, Inc.. 12. Armstrong, J.R., 1989. Chip-level modeling with VHDL. Englewood Cliffs: Prentice Hall. 13. Sieh, V., Tschache, O. and Balbach, F., 1997, June. VERIFY: Evaluation of reliability using VHDL-models with embedded fault descriptions. In Fault- Tolerant Computing, 1997. FTCS-27. Digest of Papers., Twenty-Seventh Annual International Symposium on (pp. 32-36). IEEE. 14. Navabi, Z., 1997. VHDL: Analysis and modeling of digital systems. McGraw-Hill, Inc.. 12/22/2019 Introduction to VHDL 34