11 an-efficient-vlsi-architecture-of-a-reconfigurable-pulse-shaping-fir-interpolation-filter-for-multistandard-duc
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The document presents a two-step optimization technique for designing a reconfigurable VLSI architecture of a finite-impulse response interpolation filter for multi-standard digital up converters, significantly reducing power and area consumption. The proposed method achieves an 83% reduction in multiplications and additions, along with improvements in area and power usage of 41% and 38%, respectively. Implementing this architecture aims to address the challenges posed by varying standards in software-defined radio systems.
![Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore
www.pvrtechnology.com, E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457
Existing Method:
Requirement of various high data transfer rates and high channel capacities by different
operating modes of the present day cell phones motivated the telecommunication industry to
spawn the concept of software defined radio (SDR). SDR refers to a single device that is capable
of supporting all the present as well as emerging standards available under the wireless
communication category. In an SDR system, multiple standards can be realized in a single chip
by providing a programmable channel select filter at the baseband level. Different standards have
different channel bandwidths, sampling rates, carrier-to-noise ratios, blocking, and interference
profiles. This makes the development of a reconfigurable sample rate converter chip to be a
major challenge faced by the telecommunication industry of today. a combination of
symmetrical retimed direct form architecture, balanced modular architecture, separated signed
processing architecture, and modified canonical signed digit (CSD) technique-based finite-
impulse response (FIR) filter to improve the power consumption. However, the reduction in
power has been achieved by compromising with the speed of operation that makes this design
unsuitable for the SDR system. A multiplier-less FIR interpolator with smaller area usage has
been proposed in [5]. Efficient use of lookup tables (LUTs) in this design helps to reduce the
power and area while compared with the conventional FIR filter implementation. In case of
higher order filter implementation , this architecture fails to achieve low power because of an
increase in the ROM size.](https://image.slidesharecdn.com/11-an-efficient-vlsi-architecture-of-a-reconfigurable-pulse-shaping-fir-interpolation-filter-for-mul-151217143146/85/11-an-efficient-vlsi-architecture-of-a-reconfigurable-pulse-shaping-fir-interpolation-filter-for-multistandard-duc-2-320.jpg)
11 an-efficient-vlsi-architecture-of-a-reconfigurable-pulse-shaping-fir-interpolation-filter-for-multistandard-duc
- 1. Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore www.pvrtechnology.com, E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 An Efficient VLSI Architecture of a Reconfigurable Pulse- Shaping FIR Interpolation Filter for Multi standard DUC Abstract This brief proposes a two-step optimization technique for designing a reconfigurable VLSI architecture of an interpolation filter for multi standard digital up converter (DUC) to reduce the power and area consumption. The proposed technique initially reduces the number of multiplications per input sample and additions per input sample by 83% in comparison with individual implementation of each standard’s filter while designing a root-raised-cosine finite- impulse response filter for multi standard DUC for three different standards. In the next step, a 2- bit binary common sub expression (BCS)-based BCS elimination algorithm has been proposed to design an efficient constant multiplier, which is the basic element of any filter. This technique has succeeded in reducing the area and power usage by 41% and 38%, respectively, along with 36% improvement in operating frequency over a 3-bit BCS-based technique reported earlier, and can be considered more appropriate for designing the multi standard DUC. Index Terms—Digital up converter (DUC), finite-impulse response (FIR) interpolation filter, reconfigurable hardware architecture, software defined radio (SDR) system.
- 2. Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore www.pvrtechnology.com, E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 Existing Method: Requirement of various high data transfer rates and high channel capacities by different operating modes of the present day cell phones motivated the telecommunication industry to spawn the concept of software defined radio (SDR). SDR refers to a single device that is capable of supporting all the present as well as emerging standards available under the wireless communication category. In an SDR system, multiple standards can be realized in a single chip by providing a programmable channel select filter at the baseband level. Different standards have different channel bandwidths, sampling rates, carrier-to-noise ratios, blocking, and interference profiles. This makes the development of a reconfigurable sample rate converter chip to be a major challenge faced by the telecommunication industry of today. a combination of symmetrical retimed direct form architecture, balanced modular architecture, separated signed processing architecture, and modified canonical signed digit (CSD) technique-based finite- impulse response (FIR) filter to improve the power consumption. However, the reduction in power has been achieved by compromising with the speed of operation that makes this design unsuitable for the SDR system. A multiplier-less FIR interpolator with smaller area usage has been proposed in [5]. Efficient use of lookup tables (LUTs) in this design helps to reduce the power and area while compared with the conventional FIR filter implementation. In case of higher order filter implementation , this architecture fails to achieve low power because of an increase in the ROM size.
- 3. Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore www.pvrtechnology.com, E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 ProposedMethod: To overcome the disadvantages of the existing reconfigurable architectures for FIR filter mentioned above, a new reconfigurable architecture has been proposed in this brief for initial reduction of multiplications per input sample (MPIS) and additions per input sample (APIS) and subsequent reduction of hardware and power by designing an efficient constant multiplier using 2-bit binary The organization of this brief is as follows. The problem regarding the realization of a reconfigurable FIR interpolation filter in hardware and the proposed method for its solution have been explained and describe the architectural details of the proposed reconfigurable FIR filter architecture for multi standard DUC. Implementation results and discussion common sub expression (BCS). System Configuration:-
- 4. Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore www.pvrtechnology.com, E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 In the hardware part a normal computer where Xilinx ISE 14.3 software can be easily operated is required, i.e., with a minimum system configuration HARDWARE REQUIREMENT Processor - Pentium –III Speed - 1.1 GHz RAM - 1 GB (min) Hard Disk - 40 GB Floppy Drive - 1.44 MB Key Board - Standard Windows Keyboard Mouse - Two or Three Button Mouse Monitor - SVGA SOFTWARE REQUIREMENTS Operating System :Windows95/98/2000/XP/Windows7 Front End : Modelsim 6.3 for Debugging and Xilinx 14.3 for Synthesis and Hard Ware Implementation
- 5. Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore www.pvrtechnology.com, E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 This software’s where Verilog source code can be used for design implementation.