15CS32 ADE Module 3

Module-3 Data Processing Circuits
Kishore Kumar R RLJIT Page 1
Module -3
Data Processing Circuits
Topics:
3.1 Multiplexers
3.2 De-Multiplexers
3.3 1-of-16 Decoder
3.4 BCD to Decimal Decoder
3.5 Seven Segment Decoder
3.6 Encoder
3.7 Exclusive-OR gates
3.8Parity Checker
3.9 Parity Generator
3.10 Programmable Array Logic
3.11 Programmable Logic Array
3.12 HDL Implementation of Data Processing Circuits
3.13 Magnitude Comparators
3.14 Arithmetic Building Blocks
3.14.1 Half Adder
3.14.2 Full Adder
3.14.3 Controlled Inverter
3.15 Arithmetic Logic Unit
3.16 RS Flip Flops
3.16.1 NOR Gate Latch
3.16.2 NAND Gate Latch
3.17 Gated RS Flip-Flop
3.18 Gated D Flip-FLop
3.19 Positive Edge-Triggered RS Flip Flop
3.20 Positive Edge-Triggered D Flip Flop
3.21 Positive Edge-Triggered JK Flip Flop

Module-3
Data Processing Circuits
3.1Multiplexer:
 Multiplex means many to one.
 It is circuit with many inputs but only one input.
 By using control signals we can connect any one of the inputs to output.
 It is also called as data selector.
 Multiplexer has ‘n’ input signals, ‘m’ control signals and one output signal.
Note: n ≤ 2m
4 – to -1 Multiplexer:
 It has 4 data inputs (D0, D1, D2, D3), 2 control signals and one output.
4 to 1 Block Diagram 4 to 1 Logic circuit Diagram

Truth table of 4 to 1 Multiplexer Logic Equation of 4 to 1 multiplexer:
A B Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
In the above equation when A=0 B =0 Y = D0
A=0 B=1  Y = D1
A=1 B =0 Y = D2
A=1 B=1  Y = D3
8 to 1 Multiplexer:
 It has 8 data inputs( D0, D1, D2, D3, D4, D5 D6, D7) and 3 control inputs (A, B, C) and one
output.
 Control inputs ABC connects one of data inputs to output.
8 to 1 Block Diagram 8 to 1 Logic Circuit
Truth table of 8 to 1 MUX:
A B C Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7
Y=A B D0 + A B D1 + A B D2 + A B D3

Logic Equation of 8 to 1 Multiplexer
Y = A B C D0 + A B C D1+A B C D2+A B C D3+A B C D4+ A B C D5+A B C D6 +ABC D7
16 to 1 Multiplexer:
 It has 16 data inputs( D0, D1, D2, D3, D4, D5 D6, D7,D8, D9, D10, D11, D12, D13, D14, D15)
and 4 control inputs (A, B, C,D) and one output.
 Control inputs ABCD connects one of data inputs to output.
Truth table of 16 to 1 Multiplexer: 16 to 1 Multiplexer:
A B C D Y
0 0 0 0 D0
0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3
0 1 0 0 D4
0 1 0 1 D5
0 1 1 0 D6
0 1 1 1 D7
1 0 0 0 D8
1 0 0 1 D9
1 0 1 0 D10
1 0 1 1 D11
1 1 0 0 D12
1 1 0 1 D13
1 1 1 0 D14
1 1 1 1 D15
Logic equation for 16 to 1 Mux:
Y = Aꞌ
Bꞌ
Cꞌ
Dꞌ
D0 + Aꞌ
Bꞌ
Cꞌ
D D1+Aꞌ
Bꞌ
C Dꞌ
D2+Aꞌ
Bꞌ
C DD3+ ………………….+A B C D D15

Universal Logic circuit:
 Multiplexer is called universal Logic circuit because 2n
to 1 multiplexer can be used to
implement any n variable truth table.

Problem: Show how 4 to 1 multiplexer can be obtained using only 2 to 1 multiplexer.
Sol) Logic equation for 2 to 1 multiplexer is Y= AꞋ
D0 + A D1
Logic equation for 4 to 1 multiplexer Y= AꞋ
BꞋ
D0 + AꞋ
B D1 + ABꞋ
D2 + AB D3
Y= AꞋ
(BꞋ
D0 + BD1) + A (BꞋ
D2 +BD3)
Problem: Realize a) Y=AꞋ
B + BꞋ
CꞋ
+ABC using 8 to 1 multilexer, b) can it be realized with
4 to 1 multiplexer?
Sol) convert the given equation into 8 to 1 multiplexer logic equation
Y= AꞋ
B + BꞋ
CꞋ
+ ABC
Y = AꞋ
B(C+CꞋ
) +BꞋ
CꞋ
(A+AꞋ
) + ABC
Y= AꞋ
BC+AꞋ
BCꞋ
+ BꞋ
CꞋ
A+BꞋ
CꞋ
AꞋ
+ ABC
Y= AꞋ
BꞋ
CꞋ
.1 + AꞋ
BꞋ
C .0 + AꞋ
BCꞋ
.1 + AꞋ
BC.1+ABꞋ
CꞋ
.1 + ABꞋ
C .0 + ABCꞋ
.0 +ABC.1
From the above equation D0 = D2= D3=D4=D7=1 D1= D5=D6=0
Circuit diagram:

b) yes, the equation Y= AꞋ
B + BꞋ
CꞋ
+ ABC can be realized with 4 to 1 multiplexer
the above equation can be written as
Y= AꞋ
B + BꞋ
CꞋ
(A+AꞋ) + ABC
Y= AꞋBꞋ CꞋ + AꞋB .1 + ABꞋ CꞋ + AB C
From the above equation D0 = D2=CꞋ D1=1 D3=C
Problem: Show how 8 to 1 multiplexer can be obtained using only 2 to 1 multiplexer.
Sol) Logic equation for 8 to 1 multiplexer is
Y=AꞋ
BꞋ
CꞋ
D0 +AꞋ
BꞋ
CD1 + AꞋ
BCꞋ
D2 + AꞋ
BCD3 + ABꞋ
CꞋ
D4 + ABꞋ
C D5 + ABCꞋ
D6 + ABC D7
Y=AꞋ
(BꞋ
CꞋ
D0+BꞋ
C D1+BCꞋ
D2+BC D3) + A(BꞋ
CꞋ
D4+BꞋ
C D5+BCꞋ
D6+BC D7)
Y= AꞋ
(BꞋ
(CꞋ
D0+CD1)+B(CꞋ
D2+CD3)) + A(BꞋ
(CꞋ
D4 + C D5)+B(CꞋ
D6+CD7))

Problem: show how 8 to 1 multiplexer can be obtained using 4 to 1 multiplexer and
2 to 1multiplexer.
Y=AꞋ
BꞋ
CꞋ
D0 +AꞋ
BꞋ
CD1 + AꞋ
BCꞋ
D2 + AꞋ
BCD3 + ABꞋ
CꞋ
D4 + ABꞋ
C D5 + ABCꞋ
D6 + ABC D7
Y=AꞋ
(BꞋ
CꞋ
D0+BꞋ
C D1+BCꞋ
D2+BC D3) + A(BꞋ
CꞋ
D4+BꞋ
C D5+BCꞋ
D6+BC D7)
Problem: Design 32 to 1 multiplexer using two 16 to 1 multiplexer and one 2 to 1
multiplexer.
Y=AꞋ
BꞋ
CꞋ
DꞋ
EꞋ
D0 + AꞋ
BꞋ
CꞋ
DꞋ
E D1 + AꞋ
BꞋ
CꞋ
DEꞋ
D2+ ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙+ABCDEꞋ
D30 +ABCDE D31
Y=AꞋ
(BꞋ
CꞋDꞋ
EꞋ
D0+∙∙∙∙∙∙∙∙∙∙∙+BCDE D15) + A(BꞋ
CꞋ
DꞋ
EꞋ
D16+∙∙∙∙∙∙∙∙∙∙∙+ BCDEꞋ
D30+ BCDE D31)

Nibble Multiplexer:
 It has multiple nibble inputs and one nibble output
 Control signals connect one of input nibbles to the output
2 nibble to 1 nibble multiplexer:
Nibble multiplexer has two nibble inputs, one of the nibble can be connected to output by
using control line SELECT
Operation: when control signal SELECT=0 the output Y3 Y2 Y1 Y0 = A3 A2 A1 A0
SELECT=1 the output Y3 Y2 Y1 Y0 = B3 B2 B1 B0

3.2 DEmultiplexer:
 DEmultiplexer means one into many
 By applying control signals, we can connect input signal to one of the output lines.
 The circuit has 1 input, m control or select signals and n output signals where n≤2m
DE-multiplexer Block Diagram Logic Circuit of 1 to 2 DE-multiplexer
1 to2 DE-multiplexer:
 It has single data input ‘D’, one control input ‘A’ and two outputs Y0 and Y1
Truth table of 1 to 2 DE-multiplexer
1 to 4 DE-Multiplexer:
 It has single data input ‘D’, two control input ‘A’ and ‘B’ and four outputs Y0, Y1, Y2, Y3
1 to 4 De-multiplexer Logic circuit Truth table
A Y1 Y0
0 0 D
1 D 0
A B Y3 Y2 Y1 Y0
0 0 0 0 0 D
0 1 0 0 D 0
1 0 0 D 0 0
1 1 D 0 0 0
From the truth table
Y0 = AꞋ D
Y1 = A D
From above truth table
Y0=AꞋ
BꞋ
D
Y1=AꞋ
B D
Y2=ABꞋ
D
Y3=AB D

1-to-16 De-multiplexer:
 1to 16 DEmultiplexer has 1 data input, 4 control signals and 16 outputs.
 By using ABCD control signals, data input (D) can be connected to one of the outputs.
When ABCD =0000 Y0 = D, when ABCD =1111 Y15 = D
1to 16 DEmultiplexer Logic circuit: Truth Table:
Problem: Design 1 to 32 de-multiplexer using 1 to 16 demultiplexer.
A B C D output
0 0 0 0 Y0=D
0 0 0 1 Y1=D
0 0 1 0 Y2=D
0 0 1 1 Y3=D
0 1 0 0 Y4=D
0 1 0 1 Y5=D
0 1 1 0 Y6=D
0 1 1 1 Y7=D
1 0 0 0 Y8=D
1 0 0 1 Y9=D
1 0 1 0 Y10=D
1 0 1 1 Y11=D
1 1 0 0 Y12=D
1 1 0 1 Y13=D
1 1 1 0 Y14=D
1 1 1 1 Y15=D

Decoder:
 It contains m control inputs and n outputs, but it does not contain data input
3.3 1 of 16 Decoder:
 It has four control inputs A,B,C,D and 16 outputs (Y0, Y1, …………Y15)
 Control lines are used to activate one of 16 outputs.
Logic circuit of 1 of 16 Decoder (or)
In 1 of 16 decoder circuit, only one of 16 outputs is high, because it has four input lines and 16 output
lines, this circuit is also called as 4-Line to 16-Line Decoder
e.g. When ABCD=00001 only Y1 AND gate has high output
when ABCD=1001 , AND gate Y9 has high output

3-to-8 Decoder:It has three control inputs ABC and 8 output lines Y0,Y1……..Y7
Problem: Show how using a 3-to-8 Decoder and multi-input OR gates following Boolean
Expressions can be realized simultaneously.F1(A,B,C)=∑m(0,4,6) F2(A,B,C)=∑m(0,5)
F3(A,B,C)=∑m(1,2,3,7)
Sol)
Problem: implement Full- adder using 3 to 8 decoder and OR gates
Full adder truth table: Full adder using 3 to 8 decoder
A B C Sum carry
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0
1 0
1 0
0 1
1 0
0 1
0 1
1 1

BCD (Binary coded Decimal):
BCD uses 4 bits to represent the corresponding Decimal digit
E.g. 4 = 0 1 0 0 9 = 1 0 0 1
BCD code for 496 = 0 1 0 0 1 0 0 1 0 1 1 0
3.4 BCD to Decimal Decoder (or) 1 of 10 decoder:
In the above circuit, only of 10 output lines is high at any given time
When A B C D = 0 0 1 1 only Y3 AND gate output is high
When A B C D = 1 0 0 1 only Y9 AND gate output is high
In this circuit, subscript of high output is always equal to decimal equivalent of applied BCD
code.

3.5 Seven –Segment Decoder:
 Seven segment decoder contains seven segments.
 Each segment has one LED.
 LED glows when it is forward biased ( 1 to anode and 0 to cathode)
Seven- Segment indicator:
Seven segment indicator has seven LEDs labelled a to g.
To display 0, we need to light up segments a,b,c,d,e,f
To diaply 1, we need to light up segments b and c
To display 3, we need to light up segments a,b,c,d,g
Common Anode Seven segment Indicator Common Cathode seven segment indicator
In common Anode type, all anodes are connected together and common voltage +Vcc is applied
In common Cathode type, all cathodes are connected together and common voltage gnd is
applied

3.6Encoder:
 An encoder converts active input signal into coded output signal.
 It has ‘n’ inputs and ‘m’ outputs
 One of ‘n’ input lines is active at any given time.
Problem: Design Decimal – BCD Encoder
In the above circuit, the switches are push buttons, when the button 3 is pressed, or gates C and
D have high inputs therefore the output is A B C D = 0 0 1 1
When button 5 is pressed, output A B C D = 0 1 0 1
When button 9 is pressed, output A B C D = 1 0 0 1

3.7 Exclusive –OR gate:
 Ex-OR Gate produces HIGH output only when ODD number of inputs is HIGH.
 Ex-OR Gate produces LOW output only when EVEN number of inputs is HIGH.
Logic Symbol for Ex-OR gate Truth Table:
Build Ex-OR gate using Basic gates:
Four –Input Ex-OR gate:
In four-inputs Ex-or gate, if all inputs A to D are Low, output is Low
If A to C are LOW and D is HIGH, upper gate produces LOW output, Lower gate
produces HIGH output, and output gate produces HIGH output.
EX-OR Gate produces HIGH output when number of 1s in input are ODD
EX-OR Gate produces LOW output when number of 1s in input are EVEN
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
In this circuit, upper AND gate produces AꞋ
B
and Lower AND gate produces ABꞋ
and the
output of the OR gate Y=AꞋ
B + ABꞋ

4-input EX-OR gate truth table:
Exclusive – OR gate with several Inputs:
3-input Ex-OR gate
6-input Ex-OR gate:
Even Parity: number of 1’s in Binary number is even
e.g. 110011  this number has even parity
Odd Parity: number of 1’s in binary number is odd
e.g. 110001  this number has Odd parity

3.8 Parity Checker:
 Parity checker is used to check the parity of a binary number
 Ex-OR gate can be used to check parity of binary number.
 If output of Ex-or gate is 0, the binary number has even parity
 If output of Ex-or Gate is 1, the binary number has odd parity.
Example : in the below circuit, binary number 1010110010001100 is applied has input to Ex-or
gate, it produces 1 output since the binary number has 7 1’s(odd parity)
3.9 Parity Generator:
Parity generator is used to generate the parity bit based on the number of 1’s in input
binary number, it adds extra bit to given binary number to produce new binary number with even
or odd parity.
Odd-parity generator:
The figure shows odd parity generator, it has 8-bits input
X7,X6X5,X4,X3,X2,X1,X0 and produces the output bit called
parity bit (X8) . this extra bit is added to input binary number
to produce new binary number X8, X7,X6X5,X4,X3,X2,X1,X0
the parity of new binary number is always odd.
When 8-bit binary input has even number of 1’s X8=1
When 8-bit binary input has odd number of 1’s X8=0
Example: suppose input X7,X6X5,X4,X3,X2,X1,X0 = 01000001
Ex-or Gate produces 0, because of inverter X8=1
New binary number
X8, X7,X6X5,X4,X3,X2,X1,X0 = 101000001 (odd parity)
Suppose input X7,X6X5,X4,X3,X2,X1,X0 = 01100001
Ex-OR gate produces 1, because of inverter X8=0
New binary number  X8, X7,X6X5,X4,X3,X2,X1,X0 = 001100001 (odd parity)

Application of parity Generator:
In telephone communication, parity generator is used at transmitter end and receiver end
to check single-bit errors.
3.10 Programmable Array Logic:
PAL has programmable AND array, and a fixed OR array, PAL is used to implement
Logic functions.
Structure of 4-input and 4-output PAL:
In the figure, array of 16 AND
gates are used, and array of four
OR gates are used, symbol ‘×’ is
fusible link and dot(∙) is fixed
connection the output of first four
AND gates are connected as inputs
to OR gate Y3, and outputs of next
four AND gates are connected as
inputs to OR gate Y2 and so on

Problem: Implement the following Boolean functions using PAL
Y3 = AꞋ
BCꞋ
D + AꞋ
BCDꞋ
+AꞋ
BCD +ABCDꞋ
Y2= AꞋ
BCDꞋ
+ AꞋ
BCD +ABCD
Y1=AꞋ
BCꞋ
+ AꞋ
BC +ABꞋ
C +ABCꞋ
Y0 = ABCD

3.11Programmable Logic Array:
PLA has programmable AND array and programmable OR array, PLA is more versatile
than the PAL, and PLA is more complicated to utilize since the number of fusible links are more.
Structure of 3-input 3-output PLA:
As shown in figure, it has three inputs A,B,C
And three output X,Y,Z, Array of eight AND
Gates are used and array of 3 OR gates are
used
Problem: Implement a 7-segmnet display using PLA

BCD – Seven Segment Display converter table:

3.12 HDL Implementation of Data processing Circuits:
Program: Write HDL Verilog code to realize 2 to 1 multiplexer
Y = AꞋ
D0 + AD1
module 2to1 mux(A, D0, D1, Y);
input A, D0, D1;
output Y;
assign Y=(~A&D0) | (A&D1);
endmodule
Conditional Assignment :
assign X= S?A : B
When S=0, B will be assigned to X (X=B)
S=1, A will be assigned to X (X=A)
Program: Write HDL Verilog code to realize 2 to 1 multiplexer using conditional
assignment
input A, D0, D1;
output Y;
assign Y=A?D1 : D0 /* Conditional Assignment*/
endmodule
program: Write HDL Verilog code to realize 2 to 1 multiplexer using Behavioral model
input A, D0, D1;
output Y;
reg Y;
always @ (A or D0 or D1)

if (A==1) Y=D1;
else Y=D0;
endmodule
Program : Write HDL Verilog code to realize 2 to 1 multiplexer using Case Statement
input A, D0, D1;
output Y;
reg Y;
always @ (A or D0 or D1)
case (A)
0:Y=D0;
1: Y=D1;
endcase
endmodule
program: write HDL Verilog code for 4-to-1 multiplexer using conditional assignment and
case statements
i) using conditional statements
module 4to1 mux(A,B, D0, D1,D2,D3, Y);
input A,B, D0, D1,D2,D3;
output Y;
assign Y = A?(B?D3:D2) : (B?D1:D0);
endmodule

ii) Using Case statement
module 4to1 mux(A,B, D0, D1,D2,D3, Y);
input A,B, D0, D1,D2,D3;
output Y;
reg Y;
always @ (A or B or D0 or D1 or D2 or D3)
case ({A,B})
0:Y=D0;
1:Y=D1;
2:Y=D2;
3:Y=D3;
endcase
endmodule
BUS or Vector Representation in HDL:
Program: write Verilog HDL code for the following circuit
module 1to4Demux(S,D,Y);
input [1:0] S;
input D;
output [3:0] Y;
reg [3:0 ]Y;
always @ (S or D)
case ({D,S})
3’b100 : Y=4’b0001; //when d=1 S1S2 = 00 Y= 0001
3’b101 : Y=4’b0010; //when d=1 S1S2 = 01 Y= 0010
3’b110 : Y=4’b0100; //when d=1 S1S2 = 10 Y= 0100
3’b111 : Y=4’b1000; //when d=1 S1S2 = 11 Y= 1000
default : Y=4’b0000; // when d=0 y=0000
endcase
endmodule
D S1 S2 Y3 Y2 Y1 Y0
1 0 0
1 0 1
1 1 0
1 1 1
0 × ×
0 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0
0 0 0 0

problem: A Verilog HDL code for digital circuit is given as follows, can you describe the
function it performs? Can it be related to any logic circuit?
module unknown(A,B,C,Y);
input [3:0] A,B;
input [3:0] Y;
reg [2:0] Y;
always @ (A or B or C)
if (A<B) Y=3’b001;
else if (A>B) Y=3’b010;
else Y=C;
endmodule
sol) the circuit described by above HDL compares two 4-bit numbers A and B and generates 3
bit output Y. if A is less than B Y=001 , if A is greater than B Y=010 , if A=B  Y=C
3.13 Magnitude Comparator:
It compares magnitude of two n-bit binary numbers say X and Y and activates one of
three outputs X=Y, X>Y, X<Y.
1-bit Comparator:
Logic equations for output are Logic Circuit of 1-bit Comparator
(X > Y) :G = XYꞋ
(X < Y) :L = XꞋ
Y
(X=Y) : E = XꞋ
YꞋ
+ XY
= (XYꞋ
+XꞋ
Y) Ꞌ
= (G+L) Ꞌ
1-bit
Comparator
X
Y
X>Y
X=Y
X<Y
Input
X Y
Output
X>Y X=Y X<Y
0 0
0 1
1 0
1 1
0 1 0
0 0 1
1 0 0
0 1 0

2-bit Comparator:
2-bit Comparator compares two bits of X:X1 X0 and two bits of Y: Y1 Y0
Logic Equations for outputs are
(X=Y) = E1∙E0 note: G1=X1Y1
Ꞌ
G0=X0Y0
Ꞌ
(X>Y) = G1+E1G0 L1=X1
Ꞌ
Y1 L0=X0
Ꞌ
Y0
(X<Y)= L1+E1L0 E1=(G1+L1)Ꞌ
E0 = (G0+L0)Ꞌ
n-bit Comparator :
n-bit comparator compares n-bits of X:Xn-1Xn-2……X0 and n-bits of Y:Yn-1Yn-2……Y0
Logic equations for outputs are
(X=Y) = En-1En-2……….E0
(X>Y) = Gn-1+En-1Gn-2+……….+ En-1En-2………E1G0
(X<Y)= Ln-1+ En-1Ln-2+……….+ En-1En-2………E1L0
2-bit
Comparator
X1
X0
Y1
Y0
X>Y
X=Y
X<Y

3.14 Arithmetic Building Blocks:
The three Basic Arithmetic building Blocks are
1. Half Adder
2. Full-Adder
3. Controller Inverter
3.14.1Half Adder:
Half adder has two inputs and two outputs
Truth table: Logic circuit:
A B Carry Sum
0 0
0 1
1 0
1 1
0 0
0 1
0 1
0 0
As shown in the above figure, A and B are inputs SUM and CARRY are outputs, Ex-OR gate
produces SUM output, AND gate produces CARRY output.
3.14.2 FULL Adder:
 Full adder can add 3-bits at a time.
 It has three inputs and two outputs Truth table:
Logic Circuit: A B C CARRY SUM
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0
0 1
0 1
1 0
0 1
1 0
1 0
1 1

Logic Equations for outputs SUM and CARRY:
Three AND gates are used to produce CARRY output, one AND gate is used to produce SUM
output.
3.14.3 Controlled Inverter:
Operation:
 When INVERT is LOW, it transmits 8-bit input to the output.
 When INVERT is HIGH, it transmits 1’s complement of the input to output.
E.g. If A7A6A5A4A3A2A1A0 = 0 1 1 0 1 1 1 0
When INVERT = LOW outputs Y7Y6Y5Y4Y3Y2Y1Y0 = 0 1 1 0 1 1 1 0
When INVERT=HIGH outputs Y7Y6Y5Y4Y3Y2Y1Y0 = 1 0 0 1 0 0 0 1
3.15 Arithmetic Logic Unit:
 ALU can perform arithmetic and Logic functions
 ALU is an integral part of central processing unit of a computer
 It can perform addition, subtraction, multiplication and division operations and Logic
operations like AND, OR, EX-OR and many other logic functions.
 It also has PRESET and CLEAR options, which are used to make outputs 0 and 1.
 Mode selector (M) is used to select either Arithmetic or Logic operation.

Functional Representation of ALU IC 74181:
Truth Table:
E.g. A= 1101 B=0111 perform A AND B
To perform AB operation, M=1, S3S2S1S0 = 1011, A3A2A1A0=1101 B3B2B1B0=0111
Output F3F2F1F0 = 0101

Combinational Circuits:
A combinational circuit is defined as a circuit in which the outputs are dependent on only
present inputs.
Sequential Circuits:
A sequential circuit is defined as circuit in which outputs depend on present inputs as
well as past outputs.
Differences between Combinational and sequential circuits
Combinational circuits Sequential Circuits
 In combinational circuits, outputs are
dependent on only inputs
 Memory element is not required
 Combinational circuits are faster
 Combinational are easy to design
Eg. Decoder
 In sequential circuits, the outputs are
dependent on present inputs and past
outputs.
 Memory elements are required
 Sequential circuits are slower
 Sequential circuits are difficult to
design
E.g. Counters

Flip-Flop:
 Flip-Flop is memory element, which can store 1-bit
 Flip Flop has two outputs Q and Q
 Q is normal FF output, Q is inverted FF output.
 State of Flip-Flop = Q
 Flip Flop is also called as Latch or Bistable-Multivibrator
3.16.1NOR-Gate Latch: Truth table:
In NOR-gate Latch, two NOR gates are used, one of the inputs for NOR gates is S and R
respectively, the other two inputs are fed back from the outputs
Case1:When R=0 and S=1, the output of upper NOR gate is 1 and lower NOR gate output is 0,
hence the outputs Q=1 Q= 0
Case2:When R=0 and S=0, the inputs for upper gate are 00 hence the output Q=1 and inputs for
lower gate are 10 the output Q=0 (outputs of Flip flop did not change)
Case3:When R=1 and S=0 the inputs for upper gate are 10 hence the output Q=0 and inputs for
Lower gate are 00 hence the output Q =1
Case4: when R=1 and S=1, the output of both NOR gates become zero, which violates the
basic definition of flip flop(Q should be complement of Q), hence R=1 and S=1 input
combination is violated in NOR latch
Flip-FlopInputs
Q
Q

IEEE symbol of NOR Gate Latch: Logic Symbol of NOR gate Latch:
3.16.2NAND-Gate Latch:
 NAND-Gate Latch is also called as S R Flip-Flop
 NAND gate Latch output Q=1, Q=0 when R=1 S=0
 Q=0 and Q =1 when R =0 S=1
 When R=1 and S=1, output of flip flop remains in previous state (Last State)
 When R = 0 and S=0, both outputs will become 1, which is not allowed
Logic Circuit Truth Table:
IEEE Symbol: Logic Symbol:

3.17 Gated or Clocked RS Flip-Flop:
Logic Symbol
Operation:
 When ENABLE=HIGH, outputs are dependent on R and S, and Latch is said to be
enabled.
 When ENABLE=LOW, Latch is disabled, outputs do not change with change in inputs R
and S, Latch holds the previous state.
Truth table of Clocked RS Flip-Flop: Logic Circuit:
Timing Diagram of Clocked RS Flip-Flop:
In the time period, t1-t2 EN=1, latch is enabled, since S=1 output Q=1

In t2-t3, EN=0 latch is disabled, output remains in previous state Q=1
In t3-t4 EN=1, latch is enabled, since R=1 Q=0
In t4-t5, EN=1,latch is enabled, since S=1 Q=1
In t5-t6, EN=1 latch is enabled, since R=0 and S=0 Q= last state i.e, Q=1
In t6-t7, En=0 latch is disabled, Q=last state i.e. Q=1
In t7-t8, EN=1, latch is enabled, since S=0 R=0 Q=last state i.e. Q=1
3.18 Clocked D-Flip Flop: Logic Symbol
Operation:
 When EN=0, flip flop is disabled, irrespective of D input, flip flop remains in previous
state(Q=Last state)
 When EN=1, flip-flop is transparent i.e., output depends on D (when D=0 Q=0, When
D=1 Q=1)
Truth table of D-Flip-Flop: Timing Diagram of Clocked D-Flip-Flop:

3.19 Positive Edge-Triggered RS Flip-Flop:
Logic Diagram: Symbol:
The Clock (c) is applied to positive pulse forming circuit, positive pulses are then applied
to gated RS Flip-Flop. The small triangle inside the symbol indicates that Q changes during
positive edge of the clock.
Operation:
Case 1: When C=0 , output of both And gates are 0, hence flip-flop output Qn+1=Last state.
Case 2: When C=1 S=0 R=1, output of upper AND gate is 0, and lower AND gate output is 1,
hence flip flop output Qn+1=0
Case3: When C=1 S=1 R=0, output of upper AND gate is 1, and lower AND gate output is 0,
hence flip flop output Qn+1=1
Case 4: When C=1 S=1 R=1, output of upper AND gate is 1, and lower AND gate output is 1,
hence flip flop output Qn+1=forbidden
Truth Table of Positive Edge-Triggered RS Flip-Flop:
Timing Diagram of positive Edge Triggered RS Flip-Flop:
Negative –Edge Triggered RS Flip-Flop:

Problem: Explain the following timing waveform of negative edge triggered RS Flip-Flop

3.20 Positive Edge triggered D-Flip Flop:
D Flip-Flop has only one input (D) ,when clock C=0 the output Q remains in the last
state, when Clock C is positive going( ) output Q depends on D
Case1: when C=0 , outputs of both AND gates are zero, hence Qn+1 remains in the last state
Case 2: When C=1, D=0, output of upper AND gate =0 and output of Lower AND gate=1 hence
Flip-flop output Qn+1=0
Case3: When C=1, D=1, output of upper AND gate =1 and output of Lower AND gate=0, hence
Flip-flop output Qn+1=1
Truth table of positive-Edge Triggered D-Flip Flop: Symbol
Timing Diagram of Positive Edge Triggered D Flip-Flop:

Negative Edge Triggered D Flip-Flop:
Truth Table
0
Timing Diagram of Negative –Edge triggered Flip Flop
3.21 Positive Edge Triggered JK flip Flop:
In Positive-Edge Triggered JK Flip-Flop, inputs are J and K the output Q is fed back to
the Lower AND gate, and output Q is fed back to upper AND gate.
Operation:
Case1: when C=0, outputs of both AND gates are 0 hence, the output Qn+1 remains in last state.
Case2: When C is 1, J=0 K=0 both AND gate outputs are 0, hence Flip flop output Qn+1 remains
in last state Qn
CLk D Qn+1
0 ×
0
1
Qn (Last state)
0
1

Case3:When C is 1, J=0 K=1, Qn=1 upper AND gate output is zero and Lower AND gate output
is 1, hence Flip flop output Qn+1 is 0
Case4: When C is 1, J=1 K=0, Qn=0 upper AND gate output is 1 and Lower AND gate output is
0, hence Flip flop output Qn+1 is 1
Case 5: When C=1, J=1, K=1 the output Qn+1=Qn (outputs Toggle)
Truth Table of Positive Edge triggered JK Flip-Flop: Symbol:
Timing Diagram of Positive Edge-Triggered J K Flip-Flop:

Important Questions
1. Implement the following function using 8:1 multiplexer f(a,b,c,d)= ∑m(0,1,5,6,8,10,12,15)
2. Implement the following function using 8:1 mux f(a,b,c,d)= ∑m(1,3,5,6,7,9,10,13,15)
3. Explain the operation of Nibble-Multiplexer
4. Show how 4-to-1 Multiplexer can be obtained using only 2-to-1 multiplexer.
5. Realize Y=AꞋ
B+BꞋ
CꞋ
+ABC using 8 to 1 multiplexer, and can it be realized with 4to1
multiplexer
6. show how 8 to 1 multiplexer can be obtained using only 2 to 1 multiplexer
7. Show how 8 to 1 multiplexer can be obtained using 4 to 1 mux and 2 to 1 multiplexer
8. Design 32 to 1 multiplexer using 16 to 1 multiplexer and 2 to 1 multiplexer
9.Design 16 to 1 multiplexer using 4 to 1 multiplexer and 2 to 1 multiplexer
10. Design 16 to 1 multiplexer using 8 to 1 multiplexer and 2 to 1 multiplexer
11. Explain 8 to 1 multiplexer operation with neat diagram
12. Explain 1 to 16 De-multiplexer operation with neat diagram
13. Design 1 to 32 DE-multiplexer using 1 to 16 DE multiplexer
14. Explain the operation of 1 of 16 Decoder with neat diagram.
15. Show how using a 3-to-8 Decoder and multi-input OR gates following Boolean Expressions
can be realized simultaneously.F1(A,B,C)=Σm(0,4,6) F2(A,B,C)=Σm(0,5)
F3(A,B,C)=Σm(1,2,3,7)
16. Implement Full-adder using 3 to 8 Decoder.
17. Explain BCD to Decimal Decoder with neat diagram
18. Explain seven Segment Decoder.
19. Explain Decimal-BCD Encoder with neat diagram
20. Explain the operation of Odd Parity Generator.
21. Explain 4-input 4-output programmable Array Logic
22. Implement the following Boolean functions using PAL
Y3 = AꞋ
BCꞋ
D + AꞋ
BCDꞋ
+AꞋ
BCD +ABCDꞋ
Y2= AꞋ
BCDꞋ
+ AꞋ
BCD +ABCD
Y1=AꞋ
BCꞋ
+ AꞋ
BC +ABꞋ
C +ABCꞋ
Y0 = ABCD
23. Implement 7 segment display using PLA
24. Write HDL code to realize 2 to 1 multiplexer in data flow model and behavioral model
25. Write HDL code to realize 4 to 1 multiplexer using CASE statement.
26. Write HDL code for 4 to 1 multiplexer using conditional assignment
27.What is magnitude Comparator. Explain 1-bit magnitude comparator.
28. Explain n-bit magnitude comparator
29.Differentiate between combinational and sequential circuits.
30.With block diagram and truth table, explain the working of positive-edge triggered D-
FLipFLop.
31. With block diagram and truth table, explain the working of positive-edge triggered J K
FLipFLop.

32. Explain the working principle of Gated –RS Flip Flop
33. Explain Full-Adder and controlled Inverter circuits.
34. Explain the following timing waveform of negative edge triggered RS Flip-Flop
35. Draw PLA circuit and realize the Boolean functions
X=AꞋ
BꞋ
C + ABꞋ
CꞋ
+ BꞋ
C
Y= AꞋ
BꞋ
C+ ABꞋ
CꞋ
Z= BꞋ
C
36. Define Race-Around condition.
In JK-Flip-Flop, when J=1 and K=1 and clock= outputs Q and Q toggle, this
phenomenon is called as Race-Around Condition.

15CS32 ADE Module 3

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15CS32 ADE Module 3