2 x4 decoder using switch level(Alok singh kanpur)
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This document describes a student project to design a 2-to-4 decoder using switch level modeling in Verilog. It includes the student's name and registration details, an overview of switch level modeling, descriptions of basic logic gates like NOT, NAND using PMOS and NMOS transistors, the structure of a decoder, a block diagram and truth table for the decoder design, the Verilog code for the decoder module using basic gates, and a test bench module to simulate the decoder.
![MAIN PROGRAM DECODER:-
module decoder(a,b,i);
input a,b;
output [3:0]i;
wire abar,bbar;
notgate1 z1(a,abar);
notgate1 z2(b,bbar);
andgate z3(abar,bbar,i[0]);
andgate z4(abar,b,i[1]);
andgate z5(a,bbar,i[2]);
andgate z6(a,b,i[3]);
endmodule](https://image.slidesharecdn.com/2x4decoderusingswitchlevelaloksinghkanpur-180420191510/85/2-x4-decoder-using-switch-level-Alok-singh-kanpur-13-320.jpg)
![TEST BENCH:-
module decoder_test();
reg a,b;
wire [3:0]i;
decoder d1(a,b,i);
initial
begin
a=1'b0;b=1'b0;
#5 a=1'b0;b=1'b1;
#5 a=1'b1;b=1'b0;
#5 a=1'b1;b=1'b1;
#5 $stop;
end
endmodule](https://image.slidesharecdn.com/2x4decoderusingswitchlevelaloksinghkanpur-180420191510/85/2-x4-decoder-using-switch-level-Alok-singh-kanpur-14-320.jpg)
2 x4 decoder using switch level(Alok singh kanpur)
- 1. NAME OF STUDENT –Alok Singh KANPUR (ALOK.LPU@YAHOO.COM) Registration Number-11504455 Roll Number-26 SECTION –E1508 GROUP -2 Course Code: ECE-419 PROJECT TOPIC-2:4 DECODER USING SWITCH LEVEL MODELLING Under the Guidance of (Mr sandeep dhariwal Assistant Professor)
- 3. Switch Level Modeling:- The switch level of modeling provides a level of abstraction between the logic and analog- levels of abstraction, describing the of transmission gates which are abstractions of individual MOS and CMOS transistors. The switch transistors are modeled as being either on or off, conducting or not conducting. Further, the values carried by the interconnections are abstracted the whole range of analog voltages or currents to small number of discrete values. These values are referred to as signal strengths.
- 4. GATES USING PMOS AND NMOS NOT GATE NAND GATE
- 6. DECODER In digital electronics, a binary decoder is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of outputs. They are used in a wide variety of applications, including data DE multiplexing, seven segment displays, and memory address decoding.
- 8. BLOCK DIAGRAM USING BASIC GATES:-
- 11. PROGRAM:- module notgate1(x,y); input x; output y; supply0 gnd; supply1 vdd; pmos x1(y,vdd,x); nmos x2(y,gnd,x); endmodule
- 12. NAND GATE:- module andgate(a,b,y); input a,b; output y; wire w,w1; supply0 gnd; supply1 vdd; pmos y1(w,vdd,a); pmos y2(w,vdd,b); nmos y3(w1,gnd,b); nmos y4(w,w1,a); notgate1 y5(w,y); endmodule
- 13. MAIN PROGRAM DECODER:- module decoder(a,b,i); input a,b; output [3:0]i; wire abar,bbar; notgate1 z1(a,abar); notgate1 z2(b,bbar); andgate z3(abar,bbar,i[0]); andgate z4(abar,b,i[1]); andgate z5(a,bbar,i[2]); andgate z6(a,b,i[3]); endmodule
- 14. TEST BENCH:- module decoder_test(); reg a,b; wire [3:0]i; decoder d1(a,b,i); initial begin a=1'b0;b=1'b0; #5 a=1'b0;b=1'b1; #5 a=1'b1;b=1'b0; #5 a=1'b1;b=1'b1; #5 $stop; end endmodule