![Microprogram Example
19
Symbol OP-code Description
ADD 0000 AC AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC EA)
STORE 0010 M[EA] AC
EXCHANGE 0011 AC M[EA], M[EA] AC
I Opcode Address
Computer instruction format
15 14 11 10 0
Four computer instructions
EA is the effective address
F1 F2 F3 CD BR AD
Microinstruction Format
3 3 3
2 2
7
F1, F2, F3: Microoperation fields
CD: Condition for branching
BR: Branch field
AD: Address field](https://image.slidesharecdn.com/2024lecture10come321-241123085938-cae9ec3d/85/2024_lecture10__come321-19-320.jpg)
![Microinstruction Fields
20
F1 Microoperation Symbol
000 None NOP
001 AC AC + DR ADD
010 AC 0 CLRAC
011 AC AC + 1 INCAC
100 AC DR DRTAC
101 AR DR(0-10) DRTAR
110 AR PC PCTAR
111 M[AR] DR WRITE
F2 Microoperation Symbol
000 None NOP
001 AC AC - DR SUB
010 AC AC DR OR
011 AC AC DR AND
100 DR M[AR] READ
101 DR AC ACTDR
110 DR DR + 1 INCDR
111 DR(0-10) PC PCTDR
F3 Microoperation Symbol
000 None NOP
001 AC AC DR XOR
010 AC AC’ COM
011 AC shl AC SHL
100 AC shr AC SHR
101 PC PC + 1 INCPC
110 PC AR ARTPC
111 Reserved](https://image.slidesharecdn.com/2024lecture10come321-241123085938-cae9ec3d/85/2024_lecture10__come321-20-320.jpg)
![Fetch Routine
23
Fetch routine
- Read instruction from memory
- Decode instruction and update PC
Microinstructions for fetch routine:
AR PC
DR M[AR], PC PC + 1
AR DR(0-11), CAR(2-5) DR(12-15), CAR(0,1,6) 0
Symbolic microprogram for fetch routine:
ORG 64
PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
FETCH:
Binary microporgram for fetch routine:
Binary
address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000](https://image.slidesharecdn.com/2024lecture10come321-241123085938-cae9ec3d/85/2024_lecture10__come321-23-320.jpg)
2024_lecture10__come321..................................
- 1. COME321: Computer Organization (Fall 2024) Dr. Eng. Ghada Abozaid Assistant Professor in Computer Engineering Ghada.abozaid@aswu.edu.eg Electrical Engineering Dept .
- 3. Control Unit Implementation • Hardwire d • Microprogramm ed Instruction code Combinational Logic Circuits Memory Sequence Counter . . Control signals Control signals Next Address Generator (sequencer) CAR Control Memory CDR Decoding Circuit Memory . . CAR: Control Address Register CDR: Control Data Register Instruction code 3
- 4. 4 Microprogrammed Control Unit • Control signals – Group of bits used to select paths in multiplexers, decoders, arithmetic logic units • Control variables – Binary variables specify microoperations • Certain microoperations initiated while others idle • Control word – String of 1’s and 0’s represent control variables
- 5. 5 Microprogrammed Control Unit • Control memory – Memory contains control words • Microinstructions – Control words stored in control memory – Specify control signals for execution of microoperations • Microprogram – Sequence of microinstructions
- 6. Control Memory • Read-only memory (ROM) • Content of word in ROM at given address specifies microinstruction • Each computer instruction initiates series of microinstructions (microprogram) in control memory • These microinstructions generate microoperations to – Fetch instruction from main memory – Evaluate effective address – Execute operation specified by instruction – Return control to fetch phase for next instruction Contro l memor y (ROM) 6 Control word (microinstructio n) Addres s
- 7. • Control memory – Contains microprograms (set of microinstructions) – Microinstruction contains • Bits initiate microoperations • Bits determining address sequence for control memory • Control address register (CAR) – Specifies address of microinstruction Microprogrammed Control Organization Control word Next Address Generator (sequencer) CAR Control Memory (ROM) CDR External input 7
- 8. 8 Microprogrammed Control Organization • Next address generator (microprogram sequencer) – Determines address sequence for control memory • Typical Microprogram sequencer functions – Increment CAR by one – Loads an address from control memory to CAR – Load initial address into CAR to start control operations
- 9. 9 • Control data register (CDR)- or pipeline register – Holds microinstruction read from control memory – Allows execution of microoperations specified by control word simultaneously with generation of next microinstruction Microprogrammed Control Organization
- 10. 1 0 Microprogram Routines • Routine – Group of microinstructions stored in control memory • Each computer instruction has its own microprogram routine to generate microoperations that execute the instruction
- 11. Fetch routine – Routine to determine effective address (branch microinstruction conditioned on status bit – Microoperations to execute the fetched instruction • Each instruction has its own microprogram routine stored in a given location of control memory. • The transformation from instruction code bits to an address in control memory where routine is located is called mapping. Microprogram Routines
- 12. Microprogram Routines 12 • Subroutine – Sequence of microinstructions used by other routines to accomplish particular task • Example – Subroutine to generate effective address of operand for memory reference instruction • Subroutine register (SBR) – Stores return address during subroutine call
- 13. Address Sequencing 13 • Address sequencing capabilities required in control memory – Incrementing CAR – Unconditional or conditional branch, depending on status bit conditions – Mapping from bits of instruction to address for control memory –
- 14. Address Sequencing Instruction code Mapping logic Multiplexers Control memory (ROM) Subroutine Register (SBR) Branch logic Status bits Microoperations Control Address Register (CAR) Incrementer MUX select select a status bit Branch address
- 15. Conditional Branching 15 • Branching from one routine to another depends on status bit conditions • Status bits provide parameter info such as – Carry-out of adder – Sign bit of number – Mode bits of instruction • Info in status bits can be tested and actions initiated based on their conditions: 1 or 0 • Unconditional branch – Fix value of status bit to 1
- 16. Mapping of Instruction 16 • Each computer instruction has its own microprogram routine stored in a given location of the control memory • Mapping – Transformation from instruction code bits to address in control memory where routine is located
- 17. Mapping of Instruction 17 • Example – Mapping 4-bit operation code to 7-bit address OP-codes of Instructions ADD AND LDA 0000 0001 0010 Address 0000 0 00 0001 0 00 0010 0 00 Mapping bits 0 xxxx 00 ADD Routine AND Routine LDA Routine Control memory
- 18. Microprogram Example Computer Configuration MUX AR 10 0 PC 10 0 Address Memory 2048 x 16 MUX DR 15 0 Arithmetic logic and shift unit AC 15 0 SBR CAR 6 0 6 0 Control memory 128 x 20 Control unit
- 19. Microprogram Example 19 Symbol OP-code Description ADD 0000 AC AC + M[EA] BRANCH 0001 if (AC < 0) then (PC EA) STORE 0010 M[EA] AC EXCHANGE 0011 AC M[EA], M[EA] AC I Opcode Address Computer instruction format 15 14 11 10 0 Four computer instructions EA is the effective address F1 F2 F3 CD BR AD Microinstruction Format 3 3 3 2 2 7 F1, F2, F3: Microoperation fields CD: Condition for branching BR: Branch field AD: Address field
- 20. Microinstruction Fields 20 F1 Microoperation Symbol 000 None NOP 001 AC AC + DR ADD 010 AC 0 CLRAC 011 AC AC + 1 INCAC 100 AC DR DRTAC 101 AR DR(0-10) DRTAR 110 AR PC PCTAR 111 M[AR] DR WRITE F2 Microoperation Symbol 000 None NOP 001 AC AC - DR SUB 010 AC AC DR OR 011 AC AC DR AND 100 DR M[AR] READ 101 DR AC ACTDR 110 DR DR + 1 INCDR 111 DR(0-10) PC PCTDR F3 Microoperation Symbol 000 None NOP 001 AC AC DR XOR 010 AC AC’ COM 011 AC shl AC SHL 100 AC shr AC SHR 101 PC PC + 1 INCPC 110 PC AR ARTPC 111 Reserved
- 21. Microinstruction Fields 21 CD Condition Symbol Comments 00 Always = 1 U Unconditional branch 01 DR(15) I Indirect address bit 10 AC(15) S Sign bit of AC 11 AC = 0 Z Zero value in AC BR Symbol Function 00 JMP CAR AD if condition = 1 CAR CAR + 1 if condition = 0 CAR AD, SBR CAR + 1 if condition = 1 CAR CAR + 1 if condition = 0 CAR SBR (Return from subroutine) CAR(2-5) DR(11-14), CAR(0,1,6) 0 01 CALL 10 RET 11 MAP
- 22. one of {Symbolic address (label), NEXT, empty (seven 0s)} 21 Symbolic Microinstruction Sample Format Label: Micro-ops CD BR AD Labe l may be empty or may specify symbolic address terminated with colon Micro- ops consists of 1, 2, or 3 symbols separated by commas NOP for no microoperation (nine 0s) CD one of {U, I, S, Z} U: Unconditional Branch I: Indirect address bit S: Sign of AC Z: Zero value in AC BR one of {JMP, CALL, RET, MAP} AD
- 23. Fetch Routine 23 Fetch routine - Read instruction from memory - Decode instruction and update PC Microinstructions for fetch routine: AR PC DR M[AR], PC PC + 1 AR DR(0-11), CAR(2-5) DR(12-15), CAR(0,1,6) 0 Symbolic microprogram for fetch routine: ORG 64 PCTAR U JMP NEXT READ, INCPC U JMP NEXT DRTAR U MAP FETCH: Binary microporgram for fetch routine: Binary address F1 F2 F3 CD BR AD 1000000 110 000 000 00 00 1000001 1000001 000 100 101 00 00 1000010 1000010 101 000 000 00 11 0000000
- 24. Symbolic Microprogram 24 • Control memory: 128 20-bit words • First 64 words: Routines for 16 machine instructions • Last 64 words: Used for other purpose (e.g., fetch routine and other subroutines) • Mapping: OP-code XXXX into 0XXXX00, first address for 16 routines are 0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60 Label Microops CD BR AD ORG 0 ADD: NOP I CALL INDRCT READ U JMP NEXT ADD U JMP FETCH ORG 4 BRANCH: NOP S JMP OVER NOP U JMP FETCH OVER: NOP I CALL INDRCT ARTPC U JMP FETCH ORG 8 STORE: NOP I CALL INDRCT ACTDR U JMP NEXT WRITE U JMP FETCH ORG 12 EXCHANGE: NOP I CALL INDRCT READ U JMP NEXT ACTDR, DRTAC U JMP NEXT WRITE U JMP FETCH ORG 64 FETCH: PCTAR U JMP NEXT READ, INCPC U JMP NEXT DRTAR U MAP INDRCT: READ U JMP NEXT DRTAR U RET Partial Symbolic Microprogram
- 25. Design of Control Unit 25 microoperation fields F1 F2 F3 3 x 8 decoder 7 6 5 4 3 2 1 0 3 x 8 decoder 7 6 5 4 3 2 1 0 3 x 8 decoder 7 6 5 4 3 2 1 0 Arithmetic logic and shift unit AND ADD DRTA C AC Load From From PC DR(0-10) Select 0 1 Multiplexers AR Load Clock AC DR DRTA R PCTA R
- 26. 11/23/2024 26
- 27. 11/23/2024 27