22EC502-MICROCONTROLLER AND INTERFACING-8051 MICROCONTROLLER.pdf

RMK COLLEGE OF ENGINEERING AND TECHNOLOGY
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
S. Rajalakshmi M.E (PhD)
AP/ECE

22EC502 – MICROCONTROLLER AND
INTERFACING
(Theory Course with Laboratory Component)

UNIT-2 INTRODUCTION OF 8051 MICROCONTROLLER
1. Overview of 8051 Microcontroller
2. 8051 Architecture
3. Special Function Registers (SFRs)
4. I/O Ports
5. Memory Organization
6. Addressing Modes
7. Instruction set of 8051
LIST OF EXPERIMENTS
3. One’s and two’s complement of a number using 8051
4. Block data transfer using 8051

Microprocessor Based System
CPU
External RAM, ROM, I/O
(No internal RAM, ROM, I/O ports in the CPU)

Microcontroller
• A smaller computer on a CHIP
• On-chip RAM, ROM, I/O Ports, Timer, Serial
Controller…
• Example: Motorola’s 6811, Intel’s 8051, Atmel 32

Microprocessor vs. Microcontroller
Microprocessor
• CPU is stand-alone, RAM,
ROM, I/O, timer are separate
• Designer can decide on the
amount of ROM, RAM and I/O
ports.
• Expensive
• Versatility
• General-purpose
Microcontroller
• CPU, RAM, ROM, I/O and
timer are all on a single chip
• Fixed amount of on-chip ROM,
RAM, I/O ports
• Not Expensive
• Single-purpose
• Special Purpose.

8051 Microcontroller
• Intel introduced 8051, referred as MCS- 51, in
1981.
• The 8051 is an 8-bit processor
– The CPU can work on only 8 bits of data at a time
• The 8051 became widely popular after allowing
other manufactures to make and market any flavor
of the 8051.

8051 Family
• The 8051 is a subset of the 8052
• The 8031 is a ROM-less 8051
– Add external ROM to it
– You lose two ports, and leave only 2 ports for I/O operations

Features of 8051
8 bit Processor
4KB Internal ROM
128 Bytes Internal RAM
Four 8 BIT I/O PORTS (32 I/O LINES)
Two 16 Bit Timers/Counters
On Chip Full Duplex UART for Serial Communication
5 Vector Interrupts ( 2 External, 3 Internal
Timer0,Timer1,Serial)
On Chip Clock Oscillator
16 bit Address bus
64k External Code Memory
64k External Data Memory
16-bit program counter to access external Code Memory and
16 bit Data Pointer to access external Data Memory
128 user defined flags
32 General Purpose Registers each of 8 bits

•Accumulator: (Acc)
Acc is an 8 bit special function register. It acts an operand register.
Result is temporarily stored in this register. It is used in parallel I/O
transfer.
• B Register :
B register is 8 bit SFR. It is used during multiply and divide operations.
For other operations , it can be used as a scratchpad register.
• Stack Pointer ( SP): It is 8 bit register. It is used to point the stack
memory. The stack may reside in anywhere in on-chip memory. It is
incremented before data is stored during PUSH & CALL instructions.
After reset SP is initialized to 07h. This causes the stack begin at
location 08h.
• Data Pointer (DPTR) : It is 16 bit register. It may be manipulated as a
16 bit register or as two independent 8 bit registers. Its function is to
hold a 16 bit address. This register is used for external reference.

Port 0 to Port 3 :
•Each port is a 8-bit bidirectional I/O port.
•Each contains separate address.
•Using this address,u ser can communicate with these ports.
•Each port contains latch, output driver & input buffer.
• Serial Data Buffer : Serial data buffer contains two independent
registers of a transmit buffer register and a receiver buffer register.
– Transmit buffer is a parallel in and Serial out register.
– Receiver buffer is a Serial in and parallel out register.
– When data is moved to SBUF, it goes to transmit buffer .
– When data is moved from SBUF, it comes from the receive
buffer.
• Timer Registers : Register pairs (TH0,TL0) & (TH1,TL1) are the
two 16 bit counting registers for Timer/Counter 0 and 1 respectively.

Control Registers :
The special function registers IP,IE , TMOD, TCON SCON and PCON
contain control and status information for interrupts, timer/counters and
serial port.
• Timing & Control Unit :
This unit derives an necessary timing and control signals required for
the internal operations of the circuit. It derives control signals required
for controlling the external system bus. The interrupt, serial port and
timer circuits are controlled by the control signals generated by timing
& control unit.
• Oscillator :
This circuit generates the basic timing clock signal for the operation of
the circuit using crystal oscillator.
• Instruction Register:
This register decodes the opcode of an instruction to be executed and
gives information to the timing & control unit, and to generate
necessary signals for the execution of the instruction.

EPROM & ProgramAddress Register :
These blocks provide an onchip EPROM and a Mechanism to
internally address it.
• RAM & RAM address register : These blocks provide an onchip
RAM and a mechanism to internally address it.
• ALU : The Arithmetic And Logic Unit performs 8 bit arithmetic and
logical operations over the operands held by the temporary registers
TMP 1 and TMP 2. User cannot access these temporary registers.
• SFR Register Banks : It is a set of registers, which can be addressed
using their respective addresses which lie in the range 80h to FFh.

Program Status Word [PSW]
C AC F0 RS1 RS0 OV F1 P
Register Bank Select
Carry
Auxiliary Carry
User Flag 0
Parity
User Flag 1
Overflow
Program Status Word (PSW) : PSW
register is 8 bit SFR. It contains
program status information. It is also
used to select any one of the required
register bank.

Carry Flag
•This flag is set whenever there is a carry out from the D7 bit.
• This flag bit is affected after an 8-bit addition or subtraction.
•It can also be set to 1 or 0 directly by an instruction such as “SETB
C” and “CLR C” where “SETB C” stands for “set bit carry” and “CLR
C” for “clear carry”.
The carry flag has two functions.
• It is used as the carry-out in 8-bit addition/subtraction.
For example, if the accumulator contains FDH and we add 3 to the
contents of the accumulator (ADD A, #3), the accumulator will then
contain zero and the carry flag will be set. It is also set if a subtraction
causes a borrow into bit 7.
In other words, if a number is subtracted from another number smaller
than it, the carry flag will be set. For example, if A contains 3DH and
R3 contains 4BH, the instruction SUBB A, R3 will result in the carry
bit being set (4BH is greater than 3DH).
• The carry flag is also used during Boolean operations.
For example AND the contents of bit 3DH with the carry flag, the
result being placed in the carry flag -ANL C, 3DH Register

Parity Bit :
The parity bit is automatically set or cleared in every machine cycle to
ensure even parity with the accumulator.
The number of 1-bits in the accumulator plus the parity bit is always
even.
In other words, if the number of 1s in the accumulator is odd parity bit is
set to 1.
If the number of 1s in the accumulator is even parity bit is set to 0.
For example, if the accumulator holds the number 05H, this is
0000 0101 in binary => the accumulator has an even number of 1s,
therefore the parity bit is cleared.
If the accumulator holds the number F2H, this is 1111 0010 => the
accumulator has an odd number of 1s, therefore the parity bit is set to
make the overall number of 1s even.

AC, the auxiliary carry flag
•If there is a carry from D3 to D4 during an ADD or SUB operation,
this bit is set; otherwise, it is cleared.
•This flag is used by instructions that perform BCD (binary coded
decimal) arithmetic.
OV, the overflow flag
•This flag is set whenever the result of a signed number operation is
too large, causing the high-order bit to overflow into the sign bit. In
general, the carry flag is used to detect errors in unsigned arithmetic
operations.
•The overflow flag is only used to detect errors in signed arithmetic
operations
Flag 0 :
Flag 0 is a general-purpose flag available to the programmer.
Flag 1 :
Flag 1 is a general-purpose flag available to the programmer.

Register Bank Select Bits
• Bits 3 and 4 of the PSW are used for selecting the register bank.
Since there are four register banks, two bits are required for selecting
a bank, as detailed below.
RS1 RS0 Register Bank Address
0 0 Register Bank 0 00H - 07H
0 1 Register Bank 1 08H - 0FH
1 0 Register Bank 2 10H - 17H
1 1 Register Bank 3 18H - 1FH

MEMORY ORGANISATION
• The 8051 architecture provides both on chip memory as well as off chip
memory expansion capabilities.
• It supports several distinctive „physical‟ address spaces, functionally EA
separated at the hardware level by different addressing mechanisms, read
and write controls signals or both.
• The 8051 has on chip memory of 4 Kbytes of internal Program Memory
and 128 bytes of internal Data memory.
• It can access upto 64 K program memory and 64Kdata memory

The 3 different address spaces of 8051
i) 64 Kbyte program memory
ii) 64 Kbyte external data memory
ii) 256 byte internal data memory.
Internal Data Memory (256bytes) is divided into two physically separate
and distinct blocks.
i) 128 Bytes Internal RAMArea.
This area is further divided into three.
a) 4 Register banks : [each bank has eight 8 bit registers] ( address
range 00 – 1Fh)
b) 16 bytes bit addressable locations : ( address range 20h – 2Fh)
c) 80 bytes byte addressable locations ( address range 30h – 7Fh)
ii) 128 Bytes SFRArea ( address range 80h – 0FFh )

8051 Memory Structure
27
External
EXT INT
SFR
128
External
Data Memory
64K
EA' = 0 EA' = 1
Program Memory
64K
4K
60K
Internal

EA' = 0 EA' = 1
Program Memory of 8051
OR

Internal RAM Structure
Direct &
Indirect
Addressing
Direct
Addressing
Only
SFR [ Special Function
Registers]
128 Byte Internal RAM

8051 Stack
• The stack is a section of RAM used by the CPU to
store information temporarily.
– This information could be data or an address
• The register used to access the stack is called the SP
(stack pointer) register
– The stack pointer in the 8051 is only 8 bit wide, which
means that it can take value of 00 to FFH
– When the 8051 is powered up, the SP register contains
value 07
– RAM location 08 is the first location begin used for the
stack by the 8051

8051 Stack
• The storing of a CPU register in the stack is called a
PUSH
– SP is pointing to the last used location of the stack
– As we push data onto the stack, the SP is incremented by
one
– This is different from many microprocessors
• Loading the contents of the stack back into a CPU
register is called a POP
– With every pop, the top byte of the stack is copied to the
register specified by the instruction and the stack pointer
is decremented once

•Special Function Registers (SFRs) consists of a special control table
used for running and monitoring the operation of the microcontroller.
• Each of these registers as well as each bit they include, has its name,
address in the scope of RAM and precisely defined purpose such as
timer control, interrupt control, serial communication control etc..
•8051 microcontrollers, has only 21 such registers..
SPECIAL FUNCTION REGISTERS

ACCUMULATOR
B-REGISTER
B - REG F0H
SPECIAL FUNCTION REGISTERS

DATA POINTER (DPTR)
STACK POINTER

I/O Port Registers (P0, P1, P2 and P3)

PCON (Power Control)
Peripheral Control Registers

Serial Port Mode Selection Bit

TMOD (Timer Mode)
Its lower 4 bits are used for Timer0 and the upper 4 bits are used for Timer1
Bit 7,3 – GATE:
1 = Enable Timer/Counter only when the INT0/INT1 pin is high and TR0/TR1 is set.
0 = Enable Timer/Counter when TR0/TR1 is set.
Bit 6,2 - C/(Counter/Timer): Timer or Counter select bit
1 = Use as Counter
0 = Use as Timer
Bit 5:4 & 1:0 - M1:M0: Timer/Counter mode select bit

IE (Interrupt Enable)
8052 only
1

Peripheral Data Registers
SBUF (Serial Data Buffer)
TL0/TH0 (Timer 0 Low/High)

8051AddressingModes
➢The CPU can access data in various ways, which are
calledaddressingmodes
1. Immediate AddressingMode
2. RegisterAddressingMode
3. DirectAddressingMode
4. Register IndirectAddressingMode
5. IndexedAddressing Mode

ImmediateAddressingMode
⚫The source operand is a constant.
⚫The immediate data must be preceded by the pound sign, “#”
⚫Can load information into anyregisters,including 16-bit
DPTR register
⚫ DPTR can also be accessed as two 8-bit registers, the high byte DPH
and low byte DPL

RegisterAddressingMode
⚫Use registers to hold the data to be manipulated.
• The source and destination registers must match in size.
MOV DPTR,A will give an error
• The movement of data between Rn registers is not allowed
MOV R4,R7 is invalid

Bit Addressable & Byte Addressable

DirectAddressingMode
⚫It is most often used the direct addressing mode toaccess
RAM locations 30 – 7FH.
⚫The entire 128 bytes of RAM can be accessed.
⚫Contrast this with immediate addressing mode, there is no
“#” sign in the operand.

RegisterIndirectAddressing Mode
⚫A registeris used as a pointer to the data.
⚫Only register R0and R1 are used for this purpose.
⚫R2– R7cannot be used to hold the address of an operand
located in RAM.
⚫When R0and R1hold the addresses of RAM locations, they
must be preceded by the “@” sign.

IndexedAddressing Mode
⚫Used in accessing data elements of look-up table
entries located in program ROM space
⚫External Memory is accessed.
⚫There are only two commands that use External Direct
addressing mode:
⚫MOVX A, @A+DPTR
⚫MOVC A, @A+DPTR
⚫DPTR must first be loaded with the address of external
memory.

1. Data Transfer Instructions
2. Arithmetic Instructions
3. Logic Instructions
4. Bit-oriented Instructions
5. Branch Instructions
❖ Dependingon operationtheyperform,all instructions
aredividedin severalgroups:

1.Data TransferInstructions
Mnemonic Description
MOV A,Rn Moves the register to the accumulator
MOV A,direct Moves the direct byte to the accumulator
MOV A,@Ri Moves the indirect RAM to theaccumulator
MOV A,#data Moves the immediate data to theaccumulator
MOV Rn,A Moves the accumulator to the register
MOV Rn,direct Moves the direct byte to the register
MOV Rn,#data Moves the immediate data to theregister
MOV direct,A Moves the accumulator to the directbyte
MOV direct,Rn Moves the register to the directbyte
MOV direct,direct Moves the direct byte to the directbyte
MOV direct,@Ri Moves the indirect RAM to the directbyte
MOV direct,#data Moves the immediate data to the directbyte
MOV @Ri,A Moves the accumulator to the indirectRAM

MOV @Ri,direct Movesthe directbyte to the indirect RAM
MOV @Ri,#data Movesthe immediate data to the indirect RAM
MOV DPTR,#data Movesa 16-bit data to the data pointer
MOVCA,@A+DPTR
Movesthe code byte relative to the DPTR to the accumulator
(address=A+DPTR)
MOVCA,@A+PC Movesthe code byte relative to the PC to the accumulator (address=A+PC)
MOVX A,@Ri Movesthe external RAM (8-bit address) to the accumulator
MOVX A,@DPTR Moves the external RAM (16-bit address) to the accumulator
MOVX @Ri,A Moves the accumulator to the external RAM (8-bit address)
MOVX @DPTR,A Moves the accumulator to the external RAM (16-bit address)
PUSH direct Pushes the directbyte onto the stack
POP direct Popsthe directbyte from the stack/td>
XCH A,Rn Exchanges the register with the accumulator
XCH A,direct Exchangesthe direct byte with the accumulator
XCH A,@Ri Exchanges the indirect RAM with the accumulator

ADD A,Rn Adds the register to the accumulator
ADD A,direct Adds the direct byte to the accumulator
ADD A,@Ri Adds the indirect RAM to the accumulator
ADD A,#data Adds the immediate data to the accumulator
ADDC A,Rn Adds the register to the accumulator with a carry flag
ADDC A,direct Adds the direct byte to the accumulator with a carry flag
ADDC A,@Ri Adds the indirect RAM to the accumulator with a carry flag
ADDC A,#data Adds the immediate data to the accumulator with a carry flag
SUBB A,Rn Subtracts the register from the accumulator with a borrow
SUBB A,direct Subtracts the direct byte from the accumulator with a borrow
2. Arithmetic Instructions

SUBB A,@Ri Subtracts the indirect RAM from the accumulator with a borrow
SUBB A,#data Subtracts the immediate data from the accumulator with a borrow
INC A Increments the accumulator by 1
INC Rn Increments the register by 1
INC Rx Increments the direct byte by 1
INC @Ri Increments the indirect RAM by 1
DEC A Decrements the accumulator by 1
DEC Rn Decrements the register by 1
DEC Rx Decrements the direct byte by 1
DEC @Ri Decrements the indirect RAM by 1
INC DPTR Increments the Data Pointer by 1
MUL AB Multiplies A and B
DIV AB Divides A by B
DAA Decimal adjust accumulator

5/30/2014 8051by Vijay Kumar K 140
ANL A,Rn AND register to accumulator
ANL A,direct AND direct byte to accumulator
ANL A,@Ri AND indirect RAM to accumulator
ANL A,#data AND immediate data to accumulator
ANL direct,A AND accumulator to direct byte
ANL direct,#data AND immediae data to directregister
ORL A,Rn OR register to accumulator
ORL A,direct OR direct byte to accumulator
ORL A,@Ri OR indirect RAM to accumulator
ORL direct,A OR accumulator to direct byte
ORL direct,#data OR immediate data to directbyte
3.LogicInstructions

XRL A,Rn Exclusive OR register to accumulator
XRL A,direct Exclusive OR direct byte to accumulator
XRL A,@Ri Exclusive OR indirect RAM to accumulator
XRL A,#data Exclusive OR immediate data to accumulator
XRL direct,A Exclusive OR accumulator to direct byte
XORL direct,#data Exclusive OR immediate data to direct byte
CLR A Clears the accumulator
CPL A Complements the accumulator (1=0, 0=1)
SWAPA Swaps nibbles within the accumulator
RL A Rotates bits in the accumulator left
RLC A
Rotates bits in the accumulator left through
carry
RR A Rotates bits in the accumulator right
RRC A Rotates bits in the accumulator right throughcarry

CLR C Clears the carry flag
CLR bit Clears the direct bit
SETB C Sets the carry flag
SETB bit Sets the direct bit
CPL C Complements the carry flag
CPL bit Complements the direct bit
ANL C,bit AND direct bit to the carry flag
ANL C,/bit AND complements of direct bit to the carry flag
ORL C,bit OR direct bit to the carry flag
ORL C,/bit OR complements of direct bit to the carry flag
MOV C,bit Moves the direct bit to the carry flag
MOV bit,C Moves the carry flag to the direct bit
4. Bit-oriented Instructions

ACALL addr11 Absolute subroutine call
LCALL addr16 Long subroutine call
RET Returns from subroutine
RETI Returns from interrupt subroutine
AJMP addr11 Absolute jump
LJMP addr16 Long jump
SJMP rel
Short jump (from –128 to +127 locations relative to the following
instruction)
JC rel Jump if carry flag is set. Short jump.
JNC rel Jump if carry flag is not set. Short jump.
JB bit,rel Jump if direct bit is set. Short jump.
5.BranchInstructions

JBC bit,rel Jump if direct bit is set and clears bit. Shortjump.
JMP @A+DPTR Jump indirect relative to theDPTR
JZ rel Jump if the accumulator is zero. Shortjump.
JNZ rel Jump if the accumulator is not zero. Shortjump.
CJNE A,direct,rel
Compares direct byte to the accumulator and jumpsif
not equal. Short jump.
CJNE A,#data,rel
Compares immediate data to the accumulatorand
jumps if not equal. Short jump.
CJNE Rn,#data,rel
Compares immediate data to the register and jumpsif
not equal. Short jump.
CJNE @Ri,#data,rel
Compares immediate data to indirect registerand
jumps if not equal. Short jump.
DJNZ Rn,rel Decrements register and jumps if not 0. Shortjump.
DJNZ Rx,rel Decrements direct byte and jump if not 0. Shortjump.
NOP No operation

Here is a list of the operands and their meanings:
❖A- accumulator;
Rn- is one of working registers (R0-R7) in the currently active RAM memory bank;
❖Direct- is any 8-bit address register of RAM. It can be any general-purpose register or a SFR
(I/O port, control register etc.);
❖@Ri- is indirect internal or external RAM location addressed by register R0 or R1;
❖#data- is an 8-bit constant included in instruction (0-255);
❖#data16- is a 16-bit constant included as bytes 2 and 3 in instruction (0-65535);
❖addr16- is a 16-bit address. May be anywhere within 64KB of program memory;
❖addr11- is an 11-bit address. May be within the same 2KB page of program memory as the
first byte of the following instruction;
❖rel- is the address of a close memory location (from -128 to +127 relative to the first byte of
the following instruction). On the basis of it, assembler computes the value to add or subtract
from the number currently stored in the program counter;
❖bit- is any bit-addressable I/O pin, control or status bit; and
❖C - is carry flag of the status register (register PSW).
Description of all 8051instructions

The 8051 has four important ports.
•Port 0
•Port 1
• Port 2
• Port 3
These ports allow the microcontroller to connect with
the outside world.
The four ports of 8051 microcontrollers have certain
specific functions and corresponding features.
I/O PORTS

•Each port has 8 pins. Thus the four ports jointly comprise 32
pins.
•All ports are bidirectional.
•They are constructed with a D type output latch. They have
output drivers and input buffers.
•We can modify their functions using software and hardware
that they connect to.
•All the ports are configured as input ports on Reset.
•To configure ports as an input port 1 must be written to that
port
•To configure it as an output port 0 must be written to it.
I/O PORTS - Features

• Address is 80H
• Construction: Port 0 has a D-type latch, unidirectional buffer, and 2
FETs at each pin. It does not have an internal pull-up resistor.An
external pull-up resistor is needed when Port 0 is defined as an output
port.
• Port 0 of the 8051 has two main functions:
•To be used as a simple input-output port
•To access external memory in conjunction with Port 2
PORT 0

Functions of Port 0 Simple I/O port:
•When we use Port 0 as an input port, the internal latch should know that it‟s being
used for input, and thus, a digital 1 (FFH) is written at the port address of 80H.
•To configure port 0 as an input port the internal bus writes 1 to the D flip flop and
the control pin is set to 0 (Upper FET is OFF).
•
•The mux is connected to Q'(0) of the D flip flop as the control pin is 0. Due to
this, the pin is connected to the input buffer which can be read to get the input
data.
This turns off the transistors causing the pin to float in high impedance state
connecting it to the input buffer. We can read data from „Read Pin Data‟/‟Read
Latch Bit.‟
•When we use Port 0 as an output port, the latch programmed to 0 will turn on.
Consequently, the FET will connect to GND.
•We will require an external pull up resistor(10k Ohm) here to give a logic „1‟for
using Port 0 as an output port.

To write a 1 to the external device the microcontroller writes 1 to the
D flip flop which drives the pin to a high impedance state as it is not
connected to either VCC or ground.
Access external memory:
When the 8051 wants to access external memory, the address for the
memory generates due to Port 0 and Port 2.
We get the lower half of the address from Port 0 and the upper half from
Port 2.
This is done using ALE pulses, which help to latch the address to the
external bus. Once done, the Port 0 goes back to being an input port to
read data from that memory.

Features of Port 1:
•Address is 90H
•Construction: Port 1 has one D latch, two unidirectional buffers, 1 FET,
and one internal pull-up resistor at each pin.
•It has only one function – to act as an Input-Output port.
Function of Port 1
•When Port 1 is functioning in the capacity of an input port, a digital „1‟
(FFH) is written to the latch. At 90H. This turns off the transistor, and
the pin floats in a high impedance state. Consequently, it connects to the
input buffer.
•When Port 1 is functioning in the capacity of an output port, the latch is
given a „LOW‟signal (00H). This turns the FET (Field Effect Transistor)
o. The pull-up resistor is OFF, and the port is used as an output port.

Features of Port 2
•Address is 10H
•Construction: Port 2 has a D type latch, 1 FET, an internal pull-up
resistor, two unidirectional buffers, and a Control Logic block.
•Its main functions are kind of similar to those of Port 0. It can be used as
an input-output port. And can access external memory in conjunction
with Port 0.
Functions of Port 2
I/O port:
Quite similar to Port 0. The only difference here is that in Port 2, we use
one FET with an internal pull-up resistor instead of the two FETs we saw
in Port 0.
MemoryAccess:
Port 2 is used in conjunction with Port 0 to generate the upper address of
the external memory location that needs to be accessed. However, one
key difference is that it doesn‟t need to turn around and get a 1 in the
latch immediately for input as in Port 0. It can remain stable.

Features of Port 3
•Address is B0H
•Construction: The third Port of 8051 has a D-type latch. In addition to
that, it has three unidirectional buffers. A FET with an internal pull-up
resistor.
•Additionally, it also has a NAND gate connected to the FET.
Port 3 performs two main functions,
•I/O port
•Alternate SFR function
Functions of Port 3
I/O port:
PORT 3 also acts as a bidirectional Input / Output PORT with internal
pull-ups.

Show how the flag register is affected by the following instruction.
MOVA,#0F5H ;A=F5 hex
ADDA,#0BH ;A=F5+0B=00
F5 H 1111 0101
+ 0BH + 0000 1011
100H 0000 0000
CY =1, since there is a carry out from D7
PF =1, because the number of 1s is zero (an even number), PF is set to 1.
AC =1, since there is a carry from D3 to D4
ASSEMBLY LANGUAGE PROGRAMMING

Assume that RAM locations 40 – 44H have the following values. Write a
program to find the sum of the values. At the end of the program, register A
should contain the low byte and R7 the high byte.
40 = (7D)
41 = (EB)
42 = (C5)
43 = (5B)
44 = (30)
Solution:
MOV
MOV
CLR
R0,#40H
R2,#5
A
;load pointer
;load counter
;A=0
MOV R7,A ;clear R7
AGAIN: ADD A,@R0 ;add the byte ptr to by R0
JNC NEXT ;if CY=0 don’t add carry
INC R7 ;keep track of carry
NEXT: INC R0 ;increment pointer

Assume that register A has packed BCD, write a program to convert
packed BCD to two ASCII numbers and place them in R2 and R6.
;A=29H, packedBCD
;keep a copy of BCD data
;mask the upper nibble(A=09)
;make it an ASCII,A=39H(‘9’)
;save it
;A=29H, get the original
A,#0F0H ;mask the lower nibble
RR A ;rotate right
RR A ;rotate right
RR A ;rotate right
RR A ;rotate right
MOV A,#29H
MOV R2,A
ANL A,#0FH
ORL A,#30H
MOV R6,A
MOV A,R2
data
ANL
ORL
MOV R2,A
A,#30H ;A=32H, ASCII char. ’2’
;save ASCII char in R2
SWAP A

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