8085 branching instruction
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The document summarizes the branch group instructions of the 8085 microprocessor. It describes jump instructions like JMP, conditional jump instructions, and the PCHL instruction. It also covers CALL and return instructions like CALL, RET, and conditional call and return instructions. Finally, it discusses restart instructions like RST that can be used as software interrupts to transfer program execution to specific restart locations.
8085 branching instruction
- 1. Prashant Sharma, Lecturer, ET&T, MMGGP, Rajnandgaon (C.G.) Page 1 Instruction Set of 8085 microprocessor a) Data Transfer Group b) Arithmetic Group c) Logical Group d) Branching/Loop Group e) Stack and Machine Control Group Notation used in Instruction and opcode Notations Meaning M Memory location pointed by HL register pair R 8-bit register RP 16-bit register pair RS Source register RD Destination register Addr 16-bit address X 8-bit data d)Branch Group Microprocessor executes machine codes in sequential manner. If microprocessor go to a different memory location it uses branching instructions. Branch group instructions are classified in three categories: 1. Jump Instructions: (i) JMP address (Unconditional Jump Instructions) (ii) Conditional Jump Instructions (iii) PCHL 2. Call and Return Instructions: (i) CALL address (ii) Conditional Call Instructions (iii) RET (iv) Conditional RET Instructions 3. Restart Instructions: (i) RST N
- 2. Prashant Sharma, Lecturer, ET&T, MMGGP, Rajnandgaon (C.G.) Page 2 1. Jump Instructions: (i) JMP address (Unconditional Jump Instructions) Description - Unconditional jump to the address specified along with the instruction. Operation - Address -----> PC No. of Bytes- 3 Flags - No flags are modified. Example - JMP 2050 H Before Execution After Execution Address Instruction 2039 - 2041 - 2043 JMP 2050 2046 - 2048 - 2050 - When JMP 2050 H instruction is executed, microprocessor will jump at address 2050 H and starts executing instruction from 2050 H onwards. (ii) Conditional Jump Instructions Description - Conditional jump instructions check the condition and then jump if condition is true. If condition is false microprocessor continue the next instruction after it. JC addr - Jump, if carry flag is set. JNC addr - Jump, if carry flag is not set (reset). JZ addr - Jump, if zero flag is set. JNZ addr - Jump, if zero flag is not set (reset). JP addr - Jump, if positive i.e. sign flag is reset. JM addr - Jump, if minus i.e. sign flag is set. JPE addr - Jump, if parity even i.e. parity flag is set. JPO addr - Jump, if parity odd i.e. parity flag is reset. Address Instruction 2039 - 2041 - 2043 JMP 2050 2046 - 2048 - 2050 -
- 3. Prashant Sharma, Lecturer, ET&T, MMGGP, Rajnandgaon (C.G.) Page 3 Operation - If condition is true, address -----> PC If condition is false, PC = PC + 3 No. of Bytes - 3 Flags - No flags are modified, only flags are checked. Example - JC 2050 H I. When condition is false. Before Execution After Execution When condition is false (carry flag is reset) program control is not transferred to 2050 H instead it will execute the next instruction after JC 2050 H. II. When condition is true. Before Execution After Execution When condition is true (carry flag is set) program control is transferred to 2050 H and it will execute the next instruction from 2050 H onwards. Address Instruction 2039 - 2041 - 2043 JC 2050 2046 - 2048 - 2050 - Address Instruction 2039 - 2041 - 2043 JC 2050 2046 - 2048 - 2050 - Address Instruction 2039 - 2041 - 2043 JC 2050 2046 - 2048 - 2050 - Address Instruction 2039 - 2041 - 2043 JC 2050 2046 - 2048 - 2050 -
- 4. Prashant Sharma, Lecturer, ET&T, MMGGP, Rajnandgaon (C.G.) Page 4 (iii) PCHL Description - Load program counter with content of HL register pair. Operation - HL -----> PC No. of Bytes- 1 Flags - No flags are modified. Example - PCHL Before Execution After Execution HL = 2040 H HL = 2040 H PC = 3000 H PC = 2040 H 2. CALL and Return instructions: (i) CALL Address (Unconditional CALL subroutine) Description - When this instruction is executed the program sequence is transferred to the address specified in the instruction. This instruction is used to call a subroutine. Operation - PCH -----> (SP-1), PCL -----> (SP-2), (SP-2) -----> SP No. of Bytes- 3 Flags - No flags are modified. Example - CALL 2050 H Before Execution After Execution SP = 27FF H SP -1 = 27FE H = 09H SP = 27FD H PC = 2006 H SP -2 = 27FD H = 20H PC = 2050 H Address Instruction 2000 - 2002 - 2004 - 2006 CALL 2050 H 2009 - 200B - Address Instruction 2000 - 2002 - 2004 - 2006 CALL 2050 H 2009 - 200B - Subroutine 2050H
- 5. Prashant Sharma, Lecturer, ET&T, MMGGP, Rajnandgaon (C.G.) Page 5 (ii) Conditional CALL Instructions Description - Conditional call instructions check the condition and then jump if condition is true. If condition is false microprocessor continue the next instruction after it. CC addr - Call, if carry flag is set. CNC addr - Call, if carry flag is not set (reset). CZ addr - Call, if zero flag is set. CNZ addr - Call, if zero flag is not set (reset). CP addr - Call, if positive i.e. sign flag is reset. CM addr - Call, if minus i.e. sign flag is set. CPE addr - Call, if parity even i.e. parity flag is set. CPO addr - Call, if parity odd i.e. parity flag is reset. Operation - If condition is true, PCH -----> (SP-1), PCL -----> (SP-2), (SP-2) -----> SP, Address -----> PC If condition is false, PC = PC + 3 No. of Bytes - 3 Flags - No flags are modified, only flags are checked. Example - CZ 2050 H I. When condition is false. Before Execution After Execution II. Address Instruction 2000 - 2002 - 2004 - 2006 CZ 2050 H 2009 - 200B - Address Instruction 2000 - 2002 - 2004 - 2006 CZ 2050 H 2009 - 200B - Subroutine 2050H
- 6. Prashant Sharma, Lecturer, ET&T, MMGGP, Rajnandgaon (C.G.) Page 6 SP = 27FF H SP = 27FF H PC = 2006 H PC = 2009 H When condition is false (zero flag is reset) program control is not transferred to 2050 H instead it will execute the next instruction after CZ 2050 H. II. When condition is true. Before Execution After Execution SP = 27FF H SP -1 = 27FE H = 09H SP = 27FD H PC = 2006 H SP -2 = 27FD H = 20H PC = 2050 H When condition is true (zero flag is set) program control is transferred to 2050 H and it will execute the next instruction from 2050 H onwards. (iii) RET (Return from subroutine) Description- When this instruction is executed the program sequence is transferred from the subroutine to the calling program. Main Program Subroutine Address Instruction 2000 - 2002 - 2004 - 2006 CZ 2050 H 2009 - 200B - Address Instruction 2000 - 2002 - 2004 - 2006 CZ 2050 H 2009 - 200B - Subroutine 2050H CALL SUBROUTINE NEXT INSTRUCTUION HLT RET
- 7. Prashant Sharma, Lecturer, ET&T, MMGGP, Rajnandgaon (C.G.) Page 7 Operation - (SP)-----> PCL (SP+1)-----> PCH, (SP+2) -----> SP No. of Bytes- 1 Flags - No flags are modified. Example - RET Before Execution After Execution SP = 27FD H SP = 27FD H = 09H SP = 27FF H PC = 2058 H SP+1 = 27FE H = 20H PC = 2009 H SP+2 = 27FF H When RET instruction is executed, it will take return address from stack (27FD H & 27FE H) and load in program counter. So next instruction will be from 2009 H. (iv) Conditional RET Instructions (Return from subroutine) Description- Conditional RET instructions check the condition and then jump if condition is true. If condition is false microprocessor continue the next instruction after it. RC - Return from subroutine, if carry flag is set. RNC - Return from subroutine, if carry flag is not set (reset). RZ - Return from subroutine, if zero flag is set. RNZ - Return from subroutine, if zero flag is not set (reset). RP - Return from subroutine, if positive i.e. sign flag is reset. RM - Return from subroutine, if minus i.e. sign flag is set. Address Instruction 2000 - 2002 - 2004 - 2006 CALL 2050 H 2009 Next Instruction 200B - Address Instruction 2000 - 2002 - 2004 - 2006 CALL 2050 H 2009 Next Instruction 200B - Subroutine 2050H ----- 2058H RET
- 8. Prashant Sharma, Lecturer, ET&T, MMGGP, Rajnandgaon (C.G.) Page 8 RPE - Return from subroutine, if parity even i.e. parity flag is set. RPO - Return from subroutine, if parity odd i.e. parity flag is reset. Operation - If condition is true, SP -----> PCL, (SP+1) -----> PCH, (SP+2) -----> SP, If condition is false, PC = PC + 1 No. of Bytes - 1 Flags - No flags are modified, only flags are checked. Example - RZ When this instruction is executed microprocessor checks the zero flag and if it is set then program sequence is transferred to the main program otherwise program sequence continue the subroutine. 4. RST N (Restart instructions) Description - This instructions are equivalent to 1 byte CALL instruction at restart location. These instructions can be used as software interrupts in a program to transfer program execution to one of the 8 locations depending on which RST instruction is executed. Instructions Restart Locations RST 0 0000 RST 1 0008 RST 2 0010 RST 3 0018 RST 4 0020 RST 5 0028 RST 6 0030 RST 7 0038
- 9. Prashant Sharma, Lecturer, ET&T, MMGGP, Rajnandgaon (C.G.) Page 9 Operation PCH -----> (SP-1), PCL -----> (SP-2), (SP-2) -----> SP Restart Address ----------> PC No. of Bytes- 1 Flags - No flags are modified. Example - RST 3 This instruction is equivalent to CALL 0018 H, the PC contents are stored on to stack and program sequence is transferred to address 0018 H.