A synchronization technique for single-phase grid applications

International Journal of Power Electronics and Drive Systems (IJPEDS)
Vol. 13, No. 4, December 2022, pp. 2181~2189
ISSN: 2088-8694, DOI: 10.11591/ijpeds.v13.i4.pp2181-2189  2181
Journal homepage: http://ijpeds.iaescore.com
A synchronization technique for single-phase grid applications
Issam A. Smadi, Saher A. Albatran, Taher Q. Ababneh
Department of Electrical Engineering, Faculty of Engineering, Jordan University of Science and Technology, Irbid, Jordan
Article Info ABSTRACT
Article history:
Received Jun 26, 2022
Revised Aug 23, 2022
Accepted Sep 15, 2022
The utility grid disturbances like DC offset and harmonic components can
severely affect the estimated variables from the phase-locked loop (PLL),
resulting in poor performance of the system relying on it. Therefore, there is
an emerging need for well-designed PLL algorithms ensuring robust response
against different operating conditions. This paper proposes a simple single-
phase PLL algorithm with inherent DC offset and specific harmonic orders
rejection capability. Utilizing adaptive time-delay fictitious signal generation.
A full mathematical model of the proposed PLL has been provided. The
proposed PLL is compared with other filter-based single-phase PLLs, to
validate its simplicity and excellent performance.
Keywords:
DC offset rejection
Harmonic rejection
Orthogonal signal generation
Phase-locked loop
Time-delay phase locked loop This is an open access article under the CC BY-SA license.
Corresponding Author:
Issam A. Smadi
Electrical Engineering Department, Faculty of Engineering, Jordan University of Science and Technology
Irbid 22110, Jordan
Email: iasmadi@just.edu.jo
1. INTRODUCTION
The major improvements in the power electronics field have brought new applications in power
generation and storing technologies, reshaping the conventional utility power grid. Traditionally the power grid
was a hierarchical unidirectional system; composed of bulk generation units, feeding distributed loads
passively [1]. Nowadays, distributed generation units (DGs) and smart grids (SGs) are rapidly taking place in
the power grid, as they maximize the benefits of the renewable energy-based generation systems (RESs) and
allow active operation and management of power resources [2].
However, there are serious technical challenges to the reliable and efficient operation of the described
active grid; these challenges arise from the fluctuated nature of RESs and the conditions of the grid signal,
which can affect the power quality and the dynamic stability of the overall system. Consequently, there is a
need for well-designed control systems to ensure smooth operation under different scenarios [3]−[5]. An
essential part of any control scheme is the synchronization system, responsible for detecting the grid signal
parameters (amplitude, frequency, and phase) to be used in the control process. For this purpose, there are
different techniques discussed in the literature which can be classified into; filtering based techniques (such as,
Fourier transform filter, Kalman filter, moving average filter (MAF), and notch filters), zero-crossing detection
based -techniques (ZCD), frequency-locked loop (FLL), and phase-locked loop (PLL) [4]−[15].
The PLL is the most commonly used technique because of its simple implementation and superior
dynamic performance over the other techniques. In general, the PLL is a non-linear system composed of three
main parts; a phase detector (PD) which is responsible for generating the error signal that is proportional to the
signal’s frequency, loop filter (LF) commonly a PID controller, used to minimize the error and determines the
dynamics of the PLL, and a voltage-controlled oscillator which reproduces the estimated signal [16].

 ISSN: 2088-8694
Int J Pow Elec & Dri Syst, Vol. 13, No. 4, December 2022: 2181-2189
2182
In three-phase applications, the synchronous reference frame PLL (SRF-PLL) is considered the
prevalent type, where the PD is a simple Park transformation that generates an error signal (phase difference),
then a PID controller forces this error to zero resulting in phase locking between the input signal and the direct
component (d-axes). In single-phase applications, there are two main classes distinguished by their phase
detectors, the first class is power based PLLs (p-PLLs); which have product type phase detector, and the second
class is quadrature signal generation PLLs (QSG-PLLs), which employs the conventional SRF-PLL by
producing fictitious orthogonal signal along with Clark transformation [17]. The latter has the advantage of a
flexible phase detector which can be modeled mathematically in many ways to deal with different operation
conditions. A well-known example is the conventional time delay PLL (TD-PLL), where a delay operator (of
Tn/4, Tn: fundamental period) is used to generate the fictitious signal, followed by the Clark transformation
block, then the output enters the conventional SRF-PLL, in this type of PLL the signal is assumed to be a pure
signal with no disturbances [18]. In practice, disturbances (harmonics, DC injections) in utility grid voltage
signals are inevitable; it is a byproduct of the expanding use of renewable energy sources and associated power
converter interfaces. The DC components are imposed in the signal by grid faults [19], (A/D) conversions [20],
measurement devices [21], DC injections from DGs [22], and half-wave rectification [23]; moreover, the
harmonic components are mainly brought to the grid voltage signal by the power converter (PC) interfaces. As
a result, fundamental frequency oscillations and offset errors appear on PLL output [24], leading to instability
issues in the control system of the PCs and violations of the standard recommended injected current [25],
determined by IEC 61727-2004 [26] and IEE 1547-2004 [27] standards.
Extensive work has been done in the literature to eliminate the disturbances imposed on the grid
signal. There are mainly two approaches to achieve good elimination capability, the first, using pre-loop and
in-loop filters. Golestan et al. [28] modified the conventional TD-PLL discussed in Golestan et al. [29] by
applying a pre-loop MAF filter, which can eliminate the DC-injection and higher order harmonics with proper
tuning of the MAF window length. However, due to complex frequency-adaptive implementation, this
approach suffers from complexity when frequency drifts occur. Gautam et al. [30] presented an improvement
on the same idea; this time, two in-loop MAFs have been used along with a phase lead compensator (PLC);
the resultant comb-filter has the advantages of an excellent elimination capability and overcomes the problem
of slow dynamic performance of the original MAF based technique. Liu et al. [31] presented a single-phase
PLL based on second order generalized integrator (SOGI) along with all-pass filter. Despite the excellent
rejection capability, this structure has a slow dynamic response. The second approach to deal with the
impurities of the grid signal, using the delay signal cancellation (DSC) concept. A delayed version of the
contaminated signal is produced, then the DC-injection can be removed by simple subtraction. Smadi and
Fawaz [32] presented a simple single-phase PLL structure, with the same idea, using two delay operators; one
of arbitrary length used to remove the DC offset before entering the loop, the other is of one fourth the nominal
grid period to generate the orthogonal signal needed for Park’s transformation.
This paper proposes a simple single-phase PLL with inherent DC offset rejection capability. The idea
of a balanced three phase set is used to estimate the DC-injection, then remove it using simple subtraction.
Besides, the proposed structure has the advantage of modularity with the conventional harmonics elimination
techniques developed in the three-phase PLLs. The structure of the paper is as follows: section 2 introduces a
full analysis of the proposed method. In section 3, simulation results and performance comparison with other
single-phase PLL have been proposed. Finally, the concluding remarks are summarized in section 4.
2. THE PROPOSED PLL STRUCTURE
2.1. Mathematical model of the proposed PLL
Figure 1 shows a schematic diagram for the proposed technique. The grid voltage signal is assumed
to be contaminated with DC offset. The DC offset elimination block comprises two-time delay operators with
(𝑇 3
⁄ and 2𝑇/3) lengths estimated from the loop PLL. Here, the time delay lengths are restricted to these values
as the DC offset estimation essentially depends on creating a set of balanced three phasors. The mathematical
representation of the DC offset elimination block can be given by (1).
𝑣𝑎 = 𝑣𝑔 = 𝑣𝑚 cos(𝜔𝑔𝑡 + 𝜙) + 𝑉𝑑𝑐
𝑣𝑏 = 𝑣𝑔(𝑡 − 𝜏𝐵) = 𝑣𝑚 cos(𝜔𝑔(𝑡 − 𝜏𝐵) + 𝜙) + 𝑉𝑑𝑐
𝑣𝑐 = 𝑣𝑔(𝑡 − 𝜏𝐶) = 𝑣𝑚 cos(𝜔𝑔(𝑡 − 𝜏𝐶) + 𝜙) + 𝑉𝑑𝑐 (1)
where 𝑣𝑚 is the voltage magnitude, 𝑉𝑑𝑐 is the DC offset imposed on the signal, (𝜔𝑔 = 2𝜋𝑓𝑔) is the nominal
angular frequency, 𝜙 is the phase angle, (𝜃 = 𝜔𝑔𝑡 + 𝜙), and (𝜏𝐵 and 𝜏𝐶) are adaptively extracted time delay
lengths. At steady-state, (1) represents a set of balanced three phasors, then the estimated DC offset value can
be represented as:

Int J Pow Elec & Dri Syst ISSN: 2088-8694 
A synchronization technique for single-phase grid applications (Issam A. Smadi)
2183
𝑉
̂𝑑𝑐 =
𝑣𝑚
3
(cos(𝜃) + cos (𝜃 −
2𝜋
3
𝑇
̂
𝑇𝑛
) + cos (𝜃 −
4𝜋
3
𝑇
̂
𝑇𝑛
))
⏟
=0
+
3𝑉𝑑𝑐
3
(2)
where 𝑇
̂, is the estimated time period from the loop, and 𝑇𝑛 is the nominal period of the grid signal. The first
term in (2) will diminish to zero, leaving the estimated DC offset equal to the real one. A simple subtraction is
then used to eliminate the DC value from the original three-phase set before entering the PLL, resulting in:
𝑣
̂𝑎 = 𝑣𝑎 − 𝑣
̂𝑑𝑐 =
𝑣𝑚
3
(2 cos(𝜃) − cos(𝜃 − 𝜔𝑔𝜏𝐵 ) − cos(𝜃 − 𝜔𝑔𝜏𝐶 ))
𝑣
̂𝑏 = 𝑣𝑏 − 𝑣
̂𝑑𝑐 =
𝑣𝑚
3
(− cos(𝜃) + 2 cos(𝜃 − 𝜔𝑔𝜏𝐵 ) − cos(𝜃 − 𝜔𝑔𝜏𝐶 ))
𝑣
̂𝑐 = 𝑣𝑐 − 𝑣
̂𝑑𝑐 =
𝑣𝑚
3
(− cos(𝜃) − cos(𝜃 − 𝜔𝑔𝜏𝐵 ) + 2 cos(𝜃 − 𝜔𝑔𝜏𝐶 )) (3)
Before entering the PLL, Clark’s and Park’s transformations are applied, and the general form for
both are given in the following equations:
[
𝑣
̂𝛼
𝑣
̂𝛽
] = [
2
3
−
1
3
−
1
3
0
1
√3
−
1
√3
] [
𝑣
̂𝑎
𝑣
̂𝑏
𝑣
̂𝑐
] (4)
[
𝑣
̂𝑑
𝑣
̂𝑞
] = [
cos(𝜃
̂) sin(𝜃
̂)
− sin(𝜃
̂) cos(𝜃
̂)
] [
𝑣
̂𝛼
𝑣
̂𝛽
] (5)
𝑣
̂𝑑 =
𝑣𝑚
3
cos(𝜃
̂) (2 cos(𝜃) − cos(𝜃 − 𝜔𝑔𝜏𝐵 ) − cos(𝜃 − 𝜔𝑔𝜏𝐶 ))
+
𝑣𝑚
√3
sin(𝜃
̂) (cos(𝜃 − 𝜔𝑔𝜏𝐵 ) − cos(𝜃 − 𝜔𝑔. 𝜏𝐶 )) (6)
𝑣
̂𝑞 = −
𝑣𝑚
3
sin(𝜃
̂) (2 cos(𝜃) − cos(𝜃 − 𝜔𝑔𝜏𝐵 ) − cos(𝜃 − 𝜔𝑔𝜏𝐶 ))
+
𝑣𝑚
√3
cos(𝜃
̂) (cos(𝜃 − 𝜔𝑔𝜏𝐵 ) − cos(𝜃 − 𝜔𝑔𝜏𝐶 )) (7)
where, (𝑣
̂𝛼, 𝑣
̂𝛽) are the resultant fixed frame components, (𝑣
̂𝑑, 𝑣
̂𝑞) are the resultant rotating reference frame
components. (𝜃,𝜃
̂) are the actual and estimated angles, respectively.
Figure 1. The proposed single-phase PLL
The last two equations can be used to extract the small-signal model of the proposed structure, which
helps in designing the loop-filter gains used in the PLL. For this purpose, first we apply the trigonometric
identities in (8) when necessary to simplify the equations, then linearize the non-linear terms, following the
linear approximation assumptions for the (cos, sin) functions; cos(𝛥) ≅ 1, and sin(∆) ≅ ∆, and Taylor’s series
expansion for the non-linear terms (𝜔𝑔𝜏𝐵), and (𝜔𝑔𝜏𝐶) in [33].
sin(𝑎) cos(𝑏) =
1
2
(sin(𝑎 + 𝑏) + sin(𝑎 − 𝑏) )
cos(𝑎) cos(𝑏) =
1
2
(cos(𝑎 + 𝑏) + cos(𝑎 − 𝑏) )
sin(𝑎 + 𝑏) = sin(𝑎) cos(𝑏) + cos(𝑎) sin(𝑏)
sin(𝑎 − 𝑏) = sin(𝑎) cos(𝑏) − cos(𝑎) sin(𝑏)

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cos(𝑎 + 𝑏) = cos(𝑎) cos(𝑏) − sin(𝑎) sin(𝑏)
cos(𝑎 − 𝑏) = cos(𝑎) cos(𝑏) + sin(𝑎) sin(𝑏) (8)
The resulting equations can be given as:
𝑣
̂𝑑 = 𝑣𝑚 (− sin(𝜃
̂ + 𝜃) [
𝑇
6
(𝛥𝜔𝑔 − 𝛥𝜔
̂𝑔)] − cos(𝜃
̂ + 𝜃) [
√3𝑇
18
̂𝑔)])
⏞
𝐷(𝑡)
+𝑣𝑚 −
𝑇𝑣𝑚
3
̂𝑔)(𝛥𝜃
̂ − 𝛥𝜃)
⏞
𝑁(𝑡)
𝑣
̂𝑞 = 𝑣𝑚 (sin(𝜃
̂ + 𝜃) [
√3
6
.
𝑇
3
̂𝑔)]) − cos(𝜃
̂ + 𝜃) [
𝑇
6
̂𝑔)]
⏞
𝐷(𝑡)
−𝑣𝑚 (
𝑇
3
̂𝑔) − (𝛥𝜃
̂ − 𝛥𝜃))
(9)
where (𝛥𝜔𝑔, 𝛥𝜔
̂𝑔 ) are the actual and estimated frequency variations. The double frequency term appearing in
both components will diminish to zero as the steady-state occurs, where (𝛥𝜔𝑔 = 𝛥𝜔
̂𝑔), so it can be dropped
from the equations. For the direct component (𝑁(𝑡)), will also reach zero in steady-state. The steady-state
representation can then be approximated to:
𝑣
̂𝑑 = 𝑣𝑚
𝑣
̂𝑞 = −𝑣𝑚 (
𝑇
3
̂𝑔) − (𝛥𝜃
̂ − 𝛥𝜃)) (10)
The small-signal model can be deduced from the quadrature component as follows:
𝑣
̂𝑞 = 𝑣𝑚 (
3∆𝜃 − ∆𝜔𝑔𝑇
3
− ∆𝜃
̂ −
∆𝜔
̂𝑔𝑇
3
)
𝐿𝑎𝑝𝑙𝑎𝑐𝑒 𝑇𝑟𝑎𝑛𝑠𝑓𝑟𝑜𝑚
⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗ : 𝑣
̂𝑞(𝑠) = 𝑣𝑚 (
(2+𝑒−𝑇𝑠)
3
𝛥𝜃) − 𝛥𝜃
̂(𝑠) + ∆𝜔
̂𝑔(𝑠)
𝑇
3
(11)
Figure 2 shows a block-diagram of the small-signal model presented in (11). From the last figure, the closed-
loop transfer function can be given as:
∆𝜃
̂
∆𝜃
(𝑠) =
2+𝑒−𝑇𝑆
3
𝐾𝑝𝑠+𝐾𝑖
𝑠2+𝑣𝑚(𝐾𝑝−𝐾𝑖
𝑇
3
)𝑠+𝑣𝑚𝐾𝑖
(12)
Figure 2. Small-signal model of the proposed structure
This transfer function has a second-order characteristic equation so that the loop gains can be tuned
by proper selection of the natural frequency (𝜔𝑛), and the damping ratio (ϛ), setting:
2. Ϛ. 𝜔𝑛 = 𝑣𝑚 (𝐾𝑝 − 𝐾𝑖
𝑇
3
)
𝜔𝑛
2
= 𝑣𝑚𝐾𝑖 (13)
where (𝑇) is the nominal period of the grid signal and is assumed to be (𝑇=0.02s), (𝑣𝑚=1 p.u) because of the
normalization using division (𝑉
𝑞 = 𝑉
̂𝑞 𝑉
̂𝑑
⁄ ), or inverse tangent function. A typical value of the damping factor
is (ϛ = 0.707), and the natural frequency (𝜔𝑛 = 40πrad/s), yields; (𝐾𝑝 = 282.96, and 𝐾𝑖 = 15791.36). to validate

2185
the accuracy of the small-signal model, a phase-jump of (𝛥𝜃 = 200
) is applied to the actual PLL and the small-
signal model and the results are shown in Figure 3.
Figure 3. Small-signal model validation
2.2. Harmonic elimination in the proposed PLL
The harmonic rejection capability of the proposed PLL can be spotted from Figure 1; assuming that
the grid voltage signal is harmonically distorted (1) can be rewritten as:
𝑣𝑎 = 𝑣𝑔 = 𝑉𝑚1 cos(𝜔𝑔𝑡 + 𝜙1) + ∑ 𝑉𝑚ℎ cos(ℎ𝜔𝑔𝑡 + 𝜙ℎ)
ℎ + 𝑉𝑑𝑐
𝑣𝑏 = 𝑣𝑔(𝑡 − 𝜏𝐵) = 𝑉𝑚1 cos(𝜔𝑔(𝑡 − 𝜏𝐵) + 𝜙1) + ∑ 𝑉𝑚ℎ cos(ℎ𝜔𝑔(𝑡 − 𝜏𝐵) + 𝜙ℎ)
ℎ + 𝑉𝑑𝑐
𝑣𝑐 = 𝑣𝑔(𝑡 − 𝜏𝐶) = 𝑉𝑚1 cos(𝜔𝑔(𝑡 − 𝜏𝐶) + 𝜙1) + ∑ 𝑉𝑚ℎ cos(ℎ𝜔𝑔(𝑡 − 𝜏𝐶) + 𝜙ℎ)
ℎ + 𝑉𝑑𝑐 (14)
where 𝑉𝑚1, 𝜙1 are the fundamental voltage magnitude and phase angle, ℎ, 𝑉𝑚ℎ, and 𝜙ℎ are the harmonic order,
the hth
harmonic magnitude, and phase angle, respectively. 𝜃1 = 𝜔𝑔𝑡 + 𝜙1 , and 𝜃ℎ = ℎ𝜔𝑔𝑡 + 𝜙ℎ . The
estimated DC offset in (2) becomes:
𝑉
̂𝑑𝑐 =
𝑉𝑚1
3
(cos(𝜃1) + cos (𝜃1 −
2𝜋
3
𝑇
̂
𝑇𝑛
) + cos (𝜃 −
4𝜋
3
𝑇
̂
𝑇𝑛
))
+
1
3
∑ 𝑉𝑚ℎ[cos(𝜃ℎ)
ℎ + cos (𝜃ℎ − ℎ
2𝜋
3
𝑇
̂
𝑇𝑛
) + cos (𝜃ℎ − ℎ
4𝜋
3
𝑇
̂
𝑇𝑛
)] + 𝑉𝑑𝑐 (15)
Using (3), (14) and (15), the estimated DC-free voltage can be observed through only one phase as follows:
𝑣
̂𝑎 = 𝑉
𝑚1
cos(𝜃1) −
𝑉𝑚1
3
(cos(𝜃1) + cos (𝜃1 −
2𝜋
3
𝑇
̂
𝑇𝑛
) + cos (𝜃 −
4𝜋
3
𝑇
̂
𝑇𝑛
))
⏟
≅0 ;near synchronization
+
1
3
∑ 𝑉𝑚ℎ
ℎ (2 cos(𝜃ℎ) − cos (𝜃ℎ − ℎ
2𝜋
3
𝑇
̂
𝑇𝑛
) − cos (𝜃ℎ − ℎ
4𝜋
3
𝑇
̂
𝑇𝑛
))
⏟
Harmonics
(16)
Reaching the steady-state (i.e. 𝑇
̂ ≅ 𝑇𝑛), the second, and the last terms in (16) reach zero, leaving the DC-
free phase representation (𝑉
𝑚1
cos(𝜃1)), and the harmonic term. The harmonic term can be decomposed to:
Harmonics = cos(𝜃ℎ) (2 − cos (ℎ
2𝜋
3
𝑇
̂
𝑇𝑛
) − cos (ℎ
4𝜋
3
𝑇
̂
𝑇𝑛
))
− sin(𝜃ℎ) (sin (ℎ
2𝜋
3
𝑇
̂
𝑇𝑛
) + sin (ℎ
4𝜋
3
𝑇
̂
𝑇𝑛
)) (17)
The harmonic order in which the terms cancel each other can be extracted from: cos (ℎ
2𝜋
3
) =
cos (
4𝜋ℎ
3
) = 1 , and sin (
2𝜋ℎ
3
) = sin (
4𝜋ℎ
3
) = 0 , which are satisfied if and only if ℎ = 3𝑘, 𝑘 = 1,2,3 ….
Therefore, the triplen harmonics in the grid voltage are canceled out of the box without extra cost or burden.
Hence, the proposed PLL structure is inherently immune to the DC offset and the triplen-harmonics. The same
analysis can be applied to the other phases resulting in a set of harmonic-free balanced three phase voltages.
3. RESULTS AND DISCUSSION
3.1. Simulation results
In this section, the dynamic performance of the proposed PLL has been tested numerically under two
different operational scenarios. The 2% settling time criterion is used to assess the dynamic response, and the
results are shown in Figures 4 to 6 and summarized in Table 1. The first scenario: a contaminated grid signal
with (0.15 p.u) DC offset, and triplen harmonic components of (0.05 p.u for 3rd
,6th
,9th
,12th
), resulting in 10%
THD. At 0.1 sec a voltage amplitude reduction of 0.2 p.u is applied, then returned to 1p.u at 0.2 sec. a phase-

 ISSN: 2088-8694
2186
jump of 20° is applied at 0.3 sec, and finally, the DC offset is removed at 0.4 sec. The grid voltage is shown in
Figure 4, and the results are shown in Figure 5. The second scenario: a DC offset of 0.15 p.u is initially imposed
on the signal, a frequency-jump of +3Hz at 0.1 sec is applied. The frequency returned to its nominal at 0.2 sec,
and the DC offset was removed at 0.3 sec; no harmonic components were imposed during this test. The results
are shown in Figure 6.
Figure 4. Grid voltage under the first scenario
Figure 5. Estimated frequency and phase-error under the first scenario
Figure 6. Estimated phase and frequency errors under the second test
Table 1. Simulation results
Disturbance Amplitude
Jump of (±0.2p.u)
Phase-jump
Of (+20)
Frequency-jump
Of (±3Hz)
DC offset of 0.15 p.u
Imposing (or removal)
THD of (10%)
Of the grid
voltage
Test
(1)
Phase settling
time
Amplitude
settling time
34 ms
with a maximum
overshoot of ±2o
13 ms
with a maximum
overshoot of 0.79
p.u
45 ms with phase
swing (20o
) -(-10o
)
38 ms
with a maximum
overshoot of 1.12
p.u
−
−
38 ms with a maximum
overshoot of ±7o
.
overshoot of 1.2 p.u
THD of the
estimated
voltage
0.01%
Test
(2)
Phase settling
time
Frequency
settling time
−
−
−
−
38 ms with a
maximum
overshoot of ±8o
34 ms
overshoot of +6o
32 ms with maximum
overshoot less than 1Hz
−
−

2187
3.2. Performance comparison with other single-phase PLLS
In this section, the dynamic performance of the proposed PLL is compared with three PLL structures
proposed in [30], [34], and [35]; the first one is the conventional non frequency dependent time-delay PLL
(NTD-PLL), the second structure employs an in-loop MAF filter in the NTD-PLL to eliminate the DC offset
and harmonic components from the grid signal the third structure uses a comb-filter of MAF and PLC to
enhance the speed of response of the previous one. Three tests have been conducted with different operation
scenarios.
Test 1: a phase-jump of 20o
, with normal operating conditions. The results are shown in Figure 7.
Test 2: a frequency-jump of +3Hz, with normal operating conditions. The results are shown in Figure 8.
Test 3: a phase-jump of 20°, with the presence of 0.04 p.u DC offset and the same harmonics components in
the first scenario. The results are shown in Figure 9.
Figure 7. Comparison under Test 1
3.3. Discussion
Under the first test, the proposed PLL has (45 ms) phase settling time and a peak frequency of
(52.7 Hz); the remaining structures have (36 ms, 53.1 Hz) for the NTD-PLL, (132 ms, 50.8 Hz) for the MAF-
PLL, and (4 ms, 52.3 Hz) for the MAF-PLC-PLL. Under the second test, the readings are (34ms frequency
settling time, 7o
peak phase angle), (29 ms, 5.5o
), (103 ms, 25.1o
), (46 ms, 6.3o
) respectively, the third test has
the same readings as the first one, noticing that the conventional NTD-PLL does not have a rejection technique
for the DC offset nor the harmonics. Therefore, the harmonic analysis was only conducted for the other
structures resulting in a total harmonic distortion (THD) of 0.01% for the proposed PLL and less than 0.01%
for the MAF-PLL and MAF-PLC-PLL. The results of the previous tests show that the proposed PLL has a
competitive performance with other advanced structures, with the advantage of simple implementation, unlike
the filter-based technique. Although the harmonic rejection is limited only to the triplen harmonics in the

 ISSN: 2088-8694
2188
proposed method, unlike the structures in [30] and [34], it can be easily improved by employing an additional
pre-filtering stage for the remaining significant harmonic orders.
4. CONCLUSION
This paper uses a simple single-phase PLL with inherent DC offset and triplen harmonic rejection
capability, utilizing two time-delay operators only. The proposed orthogonal signal generation provides a
modulus PLL with the well-studied three-phase PLL filtering techniques making the elimination of the other
significant harmonic orders an easy task. Full mathematical derivation has been provided through this paper,
along with comparisons simulation study with advanced PLL algorithms proving the excellent response of the
proposed PLL.
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BIOGRAPHIES OF AUTHORS
Issam A. Smadi is an IEEE senior member. Received the B.Sc. degree in
electrical engineering from Al Balqa Applied University, Engineering Technology College,
Amman, Jordan, in 2000, the M.Sc. degree in electric power and control engineering from
the Jordan University of Science and Technology, Irbid, Jordan, in 2003, and the Ph.D. degree
in electrical and computer engineering from Yokohama National University, Yokohama,
Japan, in 2009. He is currently an Associate Professor with the Jordan University of Science
and Technology. His research interests include integrating renewable energy in power
systems, control in power electronics, dynamic state estimation, electric drives, power system
dynamics, and control. He can be contacted at email: iasmadi@just.edu.jo.
Saher A. Albartan is an IEEE senior member. Received the B.Sc. degree in
electric power engineering from Yarmouk University, Irbid, Jordan, in 2005, the M.Sc.
degree in electric power and control engineering from the Jordan University of Science and
Technology, Irbid, and the Ph.D. degree in electrical engineering from the Mississippi State
University, Mississippi State, MS, USA, in 2013. He is currently a Professor with the Jordan
University of Science and Technology. His research interests include control of power
electronics, pulse-width modulation, inverter topologies, power system operation, renewable
energy, filter design, and control. He can be contacted at email: saalbatran@just.edu.jo.
Taher Q. Ababneh was born in 1991. He received the B.Sc. degree in electrical
power engineering from Yarmouk University, Irbid, Jordan, in 2017. Currently, he is working
toward the Master's degree in electrical engineering, especially in power and control, at the
Jordan University of Science and Technology. His research interests include integrating
renewable energy in power systems, power system dynamics, and control. He can be
contacted at email: tqababneh17@eng.just.edu.jo.

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