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Analog and Digital Electronics Lab Manual

C
Chirag Shetty

This document provides details on 12 experiments conducted in an Analog and Digital Electronics Lab. The first experiment involves simulating clipping and clamping circuits using diodes. The second experiment involves simulating a relaxation oscillator using an op-amp and comparing the frequency and duty cycle to theoretical values. The third experiment involves simulating a Schmitt trigger using an op-amp and comparing the upper and lower trigger points. The remaining experiments involve simulating circuits such as a Wein bridge oscillator, power supply, CE amplifier, half/full adders, multiplexers, and counters. Procedures and calculations are provided for analyzing and verifying the output of each circuit simulation.

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Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 1 BENGALURU, INDIA Analog and Digital Electronics Lab B20CS0301 Third Semester ISE 2021-2022 SCHOOL OF COMPUTING AND INFORMATION TECHNOLOGY Name Srn Branch Semester Section Academic Year
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 2 CONTENTS SL.NO LAB EXPERIMENTS PAGE NO 1 To simulate a positive clipper, double ended clipper & positive clamper circuits using diodes. 3 2 To simulate a rectangular wave form generator (Opamp relaxation oscillator) and compare the frequency and duty cycle with the design specifications. 7 3 To simulate a Schmitt trigger using Op-amp and compare the UTP andLTP values with the given specification. 10 4 To simulate a Wien bridge Oscillator. 13 5 To determine the working of a power supply and observe the waveforms. 15 6. To build and simulate CE amplifier (RC coupled amplifier) for itsfrequency response and measure the bandwidth. 17 7. Realization of Half/Full adder and Half/Full Subtractors using logic gates. 19 8. Design and develop VHDL code to realize Full adder and Full Subtractors 21 9. Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the simplified logic expression using 8:1 multiplexer IC. 24 10. Design and develop the VHDL code for an 8:1 multiplexer. Simulate and verify it’s working. 26 11. Design and implement a ring counter using 4-bit shift register and demonstrate its working. 28 12. Design and develop the Verilog / VHDL code for switched tail counter. 29 IC Pin Configuration Sheet. 31
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 3 Experiment No. 1 CLIPPING & CLAMPING CIRCUITS Aim: To simulate a positive clipper, double ended clipper & positive clamper circuits using diodes. Theory: An electronic device that is used to evade the output of a circuit to go beyond the preset value (voltage level) without varying the remaining part of the input waveform is called asClipper circuit. An electronic circuit that is used to alter the positive peak or negative peak of the input signal to a definite value by shifting the entire signal up or down to obtain the output signal peaks at desired level is called as Clamper circuit. Components Required: 1) Diodes - D1N4007 - 2 Nos. 2) Resistor – 10K 3) Power supply VDC - 2 Nos. 4) Sinusoidal signal generator(VAC) 12V(PP), 1 KHz A) Positive clipping CIRCUIT DIAGRAM: Vsin= 12V(pp) 1KHz Vi VR=2V CRO Vo R=10KΩ D
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 4 WAVEFORMS: B) DOUBLE ENDED CLIPPER CIRCUIT DIAGRAM: VAC= 12V(pp) 1KHz R=10KΩ D1 D2 VR1=2V VR2=2V CRO Vi Vo Vin +6v Vout X X TRANSFER CHARACTERISTICS: +Vout -Vout +Vin -Vin t t
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 5 WAVEFORMS: 1. POSITIVE CLAMPING CIRCUIT Components/Apparatus required: 1) Diodes - D1N4007 2) Resistor – 1MΩ 3) Capacitor – 10uf 4) Power supply VDC 5) Sinusoidal signal generator(VAC) 12V(PP), 1 KHz Vin +6v t -6v +Vout x -Vin +Vin y -Vout Vout X Y t TRANSFER CHARACTERISTICS:
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 6 C) Positive clamping CIRCUIT DIAGRAM: WAVEFORMS: Procedure: 1. Follow the simulation steps given in Expt No 6 2. Use the available cursor on the simulated window to note down the clipped voltage level. 3. Repeat the above steps for the clamping circuits. Results: Quantity/Circuit Positive cilpper Double-ended clipper Clamper X Y --- --------- Vo VAC= 12V(pp) 1kHz R=1MΩ C =10uf D VR=2V CRO Vi Vin +6v 0 t -6v Vout x 0 t
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 7 Experiment No. 2 RELAXATION OSCILLATOR USING OP - AMP Aim: To simulate a rectangular wave form generator (Opamp relaxation oscillator) and compare the frequency and duty cycle with the design specifications Theory: The circuits generate rectangular waveform of specified frequency. Op-Amp is used as comparator which compares the voltage at non inverting terminal with capacitor voltage. When the voltage at the output is +βVsat, the capacitor charges to this voltage through R1 during which output remains at +βVsat. When the capacitor voltage exceeds +βVsat output switches to –βVsat and the capacitor starts discharging through R2 to –βVsat. When the capacitor voltage goes below –βVsat, the output again switches back to +βVsat. Thus oscillations are generated, and the time period of oscillation depends on R1, R2, R3, Rf and C. Components and Equipments required: 1) Op-Amp – μA741 2) Resistors - 1K, 2K, 10K, 20K. 3) Capacitor – 0.1uf 5) Power supply (±15V) DC voltage 6) Diodes – D1N4007 – 2Nos. CIRCUIT DIAGRAM: CALCULATION: β = 4 3 3 R R R  = k k k 10 10 10  = 0.5 For the above circuit D2 R2=2kΩ R1= 1kΩ D2 R4= 10kΩ R3= 10kΩ
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 8 TON = R1 C ln           1 1 = 1k * 0.1uf * 1.1 TON = 0.11mSec TOFF = R2 C ln           1 1 = 2k * 0.1uf * 1.1 TOFF = 0.22mSec Total time period T = TON + TOFF = 0.11mSec + 0.22mSec T = 0.33mSec Duty cycle (D) = T TON = sec 33 . 0 sec 11 . 0 m m = 0.33 *100 = 33% F = T 1 = sec 33 . 0 1 m = 3kHz WAVEFORMS: Procedure: 1. Follow the simulation steps given in Expt No 6. 2. Use the available cursor on the simulated window to measure the frequency and duty cycle and compare with the theoretical value. V +Vsat Vo +βVsat Vc 0 -βVsat -Vsat TON TOFF
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 9 Results: The practical time periods are measured and compared with theoretical values and tabulated as shown below: TON TOFF VoMAx Vo MIN Vc MAX Vc MIN Duty Cycle Theoretical value 0.11m Sec 0.22m Sec +Vsat = 12v –Vsat = - 12v +βVsat = 6v –βVsat =-6v 33% Practical Value
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 10 Experiment No.3 SCHMITT TRIGGER Aim: To simulate a Schmitt trigger using Op-amp and compare the UTP andLTP values with the given specification. Theory: A Schmitt trigger is a circuit which converts any slow varying waveform into a waveform having abrupt transitions. In the Schmitt trigger circuit op-amp is used as a comparator. A Schmitt trigger is characterized by two voltage levels : 1. UTP – Upper Trigger Point 2. LTP - Lower Trigger Point The circuits can be realized to have equal UTP and LTP values or with unequal values using a reference voltage. Components/ Apparatus Required: 1) OP-AMP - μA74l 2) Resistors l0KΩ, 3.3KΩ 3) Power supply l2V DC voltage – 2 no. 4) Sinusoidal signal generator(VAC) 12V, 1kHz. CIRCUIT DIAGRAM: VAC= 12Vpeak 1kHz R1=10kΩ R2=3.3kΩ VR=1.5V CRO Vi +12v 2 7 6 µA 741 3 4 -12v Vo
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 11 WAVEFOREMS: CALCULATIONS: For the above circuit: UTP = 2 1 2 R R R Vsat   + 2 1 1 R R R VR  = K K K V 3 . 3 10 3 . 3 * 12  + K K K V 3 . 3 10 10 * 5 . 1  UTP = 4.32v LTP = 2 1 2 R R R Vsat   + 2 1 1 R R R VR  = K K K V 3 . 3 10 3 . 3 * 12   + K K K V 3 . 3 10 10 * 5 . 1  LTP = -1.62v Vin +6v UTP t LTP -6v +Vsat Vout -Vsat t
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 12 Procedure: 1. Follow the simulation steps given in Expt No 6 2. Use the available cursor on the simulated window to measure the UTP and LTP values and compare with the theoretical values. Result: Theoretical UTP : ___________ Theoretical LTP : ___________ Practical UTP : _____________ Practical LTP : ____________
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 13 Experiment No.4 WEIN BRIDGE OSCILLATOR Aim: To simulate Wein Bridge Ocsillator circuit and verify the frequency generated. Theory: The Wien bridge oscillator is developed by Maxwien in the year 1981. The Wien bridge oscillator is based on the bridge circuit it consists of four resistors and two capacitors and it is used for the measurement of impedance.The feedback circuit is used by the Wien bridge oscillator and the circuit consists of a series RC circuit which is connected to the parallel RC circuit. The Wien bridge oscillator is also called as a Wheatstone bridge circuit. Components and Equipments required: 1) Op-Amp – μA741 2) Resistors - 1k,1k,10k,20k 3) Capacitor – 0.1uf(2 no.) 5) Power supply (±12V) DC voltage CIRCUIT DIAGRAM: CALCULATION: Frequency of Oscillation fo = C R * * * 2 1  = 1.59 K Hz Where R=1K, C=0.1uf 0 0 U1 uA741 3 2 7 4 6 1 5 + - V+ V- OUT OS1 OS2 R1 1k R2 1k R3 20k R4 10k C1 0.1uf C2 0.1uf V1 12V V2 12V
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 14 WAVEFORM: Procedure: 1. Follow the simulation steps given in Expt No 6 2. Use the available cursor on the simulated window to note down the frequency of oscillation. Results: Observations/ Quantity Time Period(T) Voltage(V) Theoretical: Practical:
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 15 Experiment No. 5 POWER SUPPLY Aim: To determine the working of a power supply and observe the waveforms. Theory: Regulated power supply is necessary in some electronic circuits especially in Amplifier circuits. Poorly regulated power may cause buzzing and unwanted noise in RF and amplifier circuits.Rectifier is an electronic circuit consisting of diodes which carries out the rectification process. Rectification is the process of converting an alternating voltage or current into corresponding direct (DC) quantity. The input to a rectifier is AC whereas its output is unidirectional pulsating DC.Although a half wave rectifier could technically be used, its power losses are significant compared to a full wave rectifier. As such, a full wave rectifier or a bridge rectifier is used to rectify both the half cycles of the ac supply (full wave rectification). The rectified voltage from the rectifier is a pulsating DC voltage having very high ripple content. But this is not we want, we want a pure ripple free DC waveform. Hence a filter is used. Different types of filters are used such as capacitor filter, LC filter, Choke input filter, π type filter. The figure shows a capacitor filter connected along the output of the rectifier and the resultant output waveform.The output voltage or current will change or fluctuate when there is a change in the input from ac mains or due to change in load current at the output of the regulated power supply or due to other factors like temperature changes. This problem can be eliminated by using a regulator. A regulator will maintain the output constant even when changes at the input or any other changes occur. Transistor series regulator, Fixed and variable IC regulators or a zener diode operated in the zener region can be used depending on their applications. IC’s like 78XX and 79XX (such as the IC 7805) are used to obtained fixed values of voltages at the output. Components and Equipment’s required: 1) Diodes-DIN4007( 1 Nos) 2) Resistor 0.5K,10k 3) Capacitor 470uf 4) Sinusoidal signal generator(Vsin) 12V(PP), 1 kHz 5) LM 7805 IC Circuit diagram: 0 V1 DC = 0 VOFF = 0 VAMPL = 12 FREQ = 1k AC = 12 D1 D1N4007 R1 0.5k C1 470uf U1 LM7805C 1 2 3 IN OUT GND R2 10k
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 16 Waveform: Procedure: 1. Use the available cursor on the simulated window to observe different waveform at various output points. Results:
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 17 Experiment No. 6 RC COUPLED AMPLIFIER Aim:To build and simulate CE amplifier (RC coupled amplifier) for itsfrequency response and measure the bandwidth. Theory: RC Coupled Amplifier is an audio frequency amplifier. It is an amplifier that couples input signal to the output by coupling capacitors and collector resistance. The amplifier is biased using voltage divider bias which provides highest stability. The 3db point helps on determining the Bandwidth of the amplifier. The Amplifier has a bypass capacitor which avoids negative feedback and thus increases the amplifier gain. Components and Equipment’s required: 1) Transistor (BJT) – Q2N2222 2) Resistors – 82K, 18K, 4.7K, 1K and 1000K 3) Capacitors – 0.1uf (2 each), 10uf(2 each), 47uf 4) Sinusoidal signal generator(VAC) 20mV(PP), 1 kHz 5) Power supply 10V (VDC) CIRCUIT DIAGRAM: VAC= 20mv(pp) , 1KHz CRO 82K 4.7K 10uf 10uf Q2N2222 10V 1000K 18K 1K 47uf
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 18 FREQUENCY RESPONSE: Procedure: 1. Create the schematic shown above using the following steps.  Double click on “capture CIS” icon on the desktop  Click on file – New – Project to create a new project  Name the project (Preferably same name as of the circuit)  Create the schematic on the schematic window by selecting the parts from the library and inter connecting them using wires.  The parts will have default values and are to be changed to the required design values  Place voltage markers on the input and output ends of the circuit 2. Apply parameters for simulation in the new simulation profile window and click on Run 3. Use the available cursor on the simulated window to note down the bandwidth Results: The response of the RC coupled amplifier is simulated and the Bandwidth is _________ Hz Vo In max Vo volts max Vo/ √2 0 fL fHFreq BW = fH - fL
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 19 Experiment No 7. HALF/FULL ADDER AND HALF/FULL SUBTRACTORS Aim:Realization of Half/Full adder and Half/Full Subtractors using logic gates. Components/Apparatus required: 1) AND, OR, NOT, EX-OR gates -02 Nos. each 2) Digital trainer kit. 3) Patch chords. 1) Half adder Circuit diagram: Truth Table 2) Full adder Circuitdiagram: Truth Table INPUT A INPUT B OUTPUT Sum OUTPUT Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 INPUT A INPUT B INPUT CIN OUTPUT S OUTPUT COUT 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 20 3) Half Subtractor Circuit diagram: Truth Table 4)FullSubtractor Circuit diagram: Truth Table Procedure: 1) Make connections as shown in the circuit diagram. 2) Connect input to +5v for logic 1 and to ground for logic 0 3) Verify the truth table. INPUT X INPUT Y OUTPUT D OUTPUT B 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 INPUT X INPUT Y INPUT Z OUTPUT D OUTPUT B 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 21 Experiment No. 8 VHDL CODE TO REALIZE FULL ADDER AND FULL SUBTRACTORS Aim: Design and develop VHDL code to realize Full adder and Full Subtractors. Steps in Using the Xilinx software for writing VHDL Code: 1. Double click on “Xilinx ISE 9.1i” icon on the desktop. 2. Click on File- New project. 3. Give a name (preferably same name as the experiment name) and click on next. 4. In the new project wizard select Family as “Automotive Spartan3” and simulator “ISE simulator (VHDL/Verilog)” and prefer language“VHDL”. Click on next. 5. Click on “New source” and next. 6. Enter the same file name as given in step 3 and select “VHDL module” click on next. 7. Enter the port name, direction and bus information given in the VHDLprogram under Entity. Click on next. 8. After ensuring the port definition clicks on finish if not go back to re-enter the values for step 7 and then click on next. 9. Click on finish to enter the editor window and enter the VHDL code. 10. Save the file and check for syntax (by expanding codes “synthesize-XST”) 11. Double click on “Create new source” and enter the file name. Select“Test Bench Waveform” and click on next - next – finish. 12. Select single clock/ combinational under “clock information” and clickon finish. 13. Select the inputs as high and low by clicking the mouse on the required inputs and save. 14. Select “Behavioral simulation” under sources and select “.tbw file” 15. Click on process and expand “Xlinx ISE simulator” and double click on simulate behavioral module to observe the output waveforms. 16. Use cursor to verify truth table / result Note: The above steps have to be used for all VHDL simulations. 1) VHDL code for Full adder: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityfull_adder is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end full_adder; architecture behavioural of full_adder is
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 22 begin sum<= a xor b xor c; carry<=((a xor b )and c) or (a and b) ; end behavioural; Output waveform: 2)VHDL code for Full Subtractor: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full_subtractor is port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; difference : out STD_LOGIC; borrow : out STD_LOGIC); end full_subtractor; architecture behavioural of full_subtractor is begin difference <= a xor b xor c; borrow <= ((not a) and b) or ((not(a xor b)) and c); end behavioural; Output Waveform:
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 23 OBSERVATIONS 1.) What are the errors encountered in conducting the experiment/compilation? 2.) Measures taken to fix the problem (circuit debug/logical errors)? 3.) Results ASSIGNMENT 1.) Realize the full adder using 3:8 decoder and verify the behavior. VIVA QUESTIONS 1.) The full adder realized in this experiment is a.) 4-bit adder b) 2-bit adder c) 3-bit adder d) 1-bit adder 2.) Draw the block diagram for 3-bit parallel adder. 3.) Write the 2’s compliment of the following numbers a.) 00001111 b.) 01011010 c.) 10111110 4.) Subtract 64 from 89 using 2’s compliment addition.
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 24 Experiment No. 9 8:1 MULTIPLEXER Aim: Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the simplified logic expression using 8:1 multiplexer IC Components/Apparatus required: 1) Multiplexer IC74151. 2) Digital IC Trainer Kit. 3) Patch Chords. TRUTH TABLE: IMPLEMENTATION TABLE: A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 D = 0 Y = 0 Y = 1 Y = 0 Y = 1 Y = 1 Y = 1 Y = 1 Y = 1 D = 1 Y = 1 Y = 1 Y = 0 Y = 0 Y = 1 Y = 0 Y = 1 Y = 0 Mux I/P I0 = D I1 = 1 I2 = 0 I3 = D I4 = 1 I5 = D I6 = 1 I7 = D A B C D Y 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 25 CIRCUIT DIAGRAM: PROCEDURE: 1. Convert any given Boolean Expression into Σm( ) notation. 2. Write the Implementation table for the given expression. 3. Find the inputs to be applied to the inputs of the Multiplexer. 4. Make connections as per the implementation table. 5. Apply the inputs using Switches on the Trainer kit and verify the output LEDs on the Trainer kit. 6. Verify the truth table 0 74LS04 1 2 74HC151 7 16 4 3 2 1 15 14 13 12 11 10 9 6 5 E VCC I0 I1 I2 I3 I4 I5 I6 I7 S0 S1 S2 Z Z Y +5V D GND 8 C B A I C 7 4 1 5 1
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 26 Experiment No.10 VHDL CODE FOR AN 8:1 MULTIPLEXER Aim: Design and develop the VHDL code for an 8:1 multiplexer. Simulate and verify it’s working. VHDL code for 8:1 MUX library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux8to1 is Port ( sel : in STD_LOGIC_vector(2 downto 0); din : in STD_LOGIC_vector(7 downto 0); dout : out STD_LOGIC); end mux8to1; architecture Behavioral of mux8to1 is begin process(sel,din(7), din(6), din(5), din(4), din(3), din(2), din(1), din(0)) begin casesel is when "000"=>dout<=din(7); when "001"=>dout<= din(6); when "010"=>dout<= din(5); when "011"=>dout<= din(4); when "100"=>dout<= din(3); when "101"=>dout<= din(2); when "110"=>dout<= din(1); when "111"=>dout<= din(0); when others=>null; end case; end process; end Behavioral;
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 27 Output waveform: OBSERVATIONS 1.) What are the errors encountered in conducting the experiment/compilation? 2.) Measures taken to fix the problem(circuit debug/logical errors) 3.) Results ASSIGNMENT 1.) Realize the Boolean Expression Y= πM(1,2,3,6,8,9,10,12,13,14) using 8:1 Multiplexer IC VIVA QUESTIONS 1.) Draw the block diagram of a 4:1 multiplexer and a 2:1 multiplexer. 2.) Realize a 8:1 multiplexer using two 4:1 multiplexer and a 2:1 multiplexer. 3.) A circuit with many inputs and only one output is called a ___________________ 4.) Write a VHDL code for 4:1 multiplexer.
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 28 Experiment No.11 RING COUNTER Aim: Design and implement a ring counter using 4-bit shift register and demonstrate its working. Components/Apparatus required: 1) Shift Register IC 7495 2) Digital IC Trainer Kit 3) Patch Chords CIRCUIT DIAGRAM: Procedure: Q0 Vcc Q3 Q2 Q1 Clk1 Clk2 14 13 12 11 10 9 8 I C 7 4 9 5 1 2 3 4 5 6 7 Ds D3 D2 D1 D0 M Gnd
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 29 Experiment No.12 VHDL code for switched tail counter Aim: Design and develop the Verilog / VHDL code for switched tail counter. VHDL code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityjohnson is Port ( clk : in STD_LOGIC; q :inout STD_LOGIC_VECTOR (3 to 0) :="0000"); endjohnson; architecture Behavioral of johnson is begin process(clk) begin if(clk'event and clk='0') then q(3)<= not(q(0)); fori in 3downto 1 loop q(i-1)<= q(i); end loop; end if; end process; end Behavioral; WAVEFORM: Clk q3 q2 q1 q0
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 30 Procedure: Follow the steps given for simulation of experiment 1b. OBSERVATIONS 1.) What are the errors encountered in conducting the experiment/compilation? 2.) Measures taken to fix the problem (circuit debug/logical errors) 3.) Results ASSIGNMENTS 1.) Modify the above ring counter circuit to Johnson counter. 2.) Modify the above VHDL code for a ring counter. VIVA QUESTIONS 1.) List the difference between ring counter and Johnson counter. 2.) List the different type of shift register. 3.) Draw the circuit of a 3-bit ring counter using JK-flip flop.
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 31 IC Pin Configuration Sheet: e IC 7400 2 I/P NAND GATE IC 7402 2 I/P NOR GATE IC 7404 NOT GATE IC 7408 2 I/P AND GATE IC 7410 3 I/P NAND GATE IC 7432 2 I/P OR GATE
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 32 IC 7410 3 I/P NAND GATE IC 74138 Decoder IC 7411 3 I/P AND GATE IC 7486 2 I/P EXOR GATE IC 7476 JK FLIP FLOP IC 7420 4 I/P NAND GATE IC 7427 3 I/P NOR GATE
Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 33 Components names of Analog Circuits Sl.No Component Name Library Part Code 1 Resistor Analog R 2 Capacitor Analog C 3 Sine wave Source Vsin 4 DC supply Source Vdc 5 Opamp Opamp uA741 6 Diode Diode D1N4007 7 Transistor Bipolar Q2N2222 8 Voltage Regulator Opamp LM7805C 9 Ground GND(0/Source) IC 74151 8:1 Mux IC uA741 OPAMP IC 555 Timer

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Analog and Digital Electronics Lab Manual

  • 1. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 1 BENGALURU, INDIA Analog and Digital Electronics Lab B20CS0301 Third Semester ISE 2021-2022 SCHOOL OF COMPUTING AND INFORMATION TECHNOLOGY Name Srn Branch Semester Section Academic Year
  • 2. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 2 CONTENTS SL.NO LAB EXPERIMENTS PAGE NO 1 To simulate a positive clipper, double ended clipper & positive clamper circuits using diodes. 3 2 To simulate a rectangular wave form generator (Opamp relaxation oscillator) and compare the frequency and duty cycle with the design specifications. 7 3 To simulate a Schmitt trigger using Op-amp and compare the UTP andLTP values with the given specification. 10 4 To simulate a Wien bridge Oscillator. 13 5 To determine the working of a power supply and observe the waveforms. 15 6. To build and simulate CE amplifier (RC coupled amplifier) for itsfrequency response and measure the bandwidth. 17 7. Realization of Half/Full adder and Half/Full Subtractors using logic gates. 19 8. Design and develop VHDL code to realize Full adder and Full Subtractors 21 9. Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the simplified logic expression using 8:1 multiplexer IC. 24 10. Design and develop the VHDL code for an 8:1 multiplexer. Simulate and verify it’s working. 26 11. Design and implement a ring counter using 4-bit shift register and demonstrate its working. 28 12. Design and develop the Verilog / VHDL code for switched tail counter. 29 IC Pin Configuration Sheet. 31
  • 3. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 3 Experiment No. 1 CLIPPING & CLAMPING CIRCUITS Aim: To simulate a positive clipper, double ended clipper & positive clamper circuits using diodes. Theory: An electronic device that is used to evade the output of a circuit to go beyond the preset value (voltage level) without varying the remaining part of the input waveform is called asClipper circuit. An electronic circuit that is used to alter the positive peak or negative peak of the input signal to a definite value by shifting the entire signal up or down to obtain the output signal peaks at desired level is called as Clamper circuit. Components Required: 1) Diodes - D1N4007 - 2 Nos. 2) Resistor – 10K 3) Power supply VDC - 2 Nos. 4) Sinusoidal signal generator(VAC) 12V(PP), 1 KHz A) Positive clipping CIRCUIT DIAGRAM: Vsin= 12V(pp) 1KHz Vi VR=2V CRO Vo R=10KΩ D
  • 4. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 4 WAVEFORMS: B) DOUBLE ENDED CLIPPER CIRCUIT DIAGRAM: VAC= 12V(pp) 1KHz R=10KΩ D1 D2 VR1=2V VR2=2V CRO Vi Vo Vin +6v Vout X X TRANSFER CHARACTERISTICS: +Vout -Vout +Vin -Vin t t
  • 5. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 5 WAVEFORMS: 1. POSITIVE CLAMPING CIRCUIT Components/Apparatus required: 1) Diodes - D1N4007 2) Resistor – 1MΩ 3) Capacitor – 10uf 4) Power supply VDC 5) Sinusoidal signal generator(VAC) 12V(PP), 1 KHz Vin +6v t -6v +Vout x -Vin +Vin y -Vout Vout X Y t TRANSFER CHARACTERISTICS:
  • 6. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 6 C) Positive clamping CIRCUIT DIAGRAM: WAVEFORMS: Procedure: 1. Follow the simulation steps given in Expt No 6 2. Use the available cursor on the simulated window to note down the clipped voltage level. 3. Repeat the above steps for the clamping circuits. Results: Quantity/Circuit Positive cilpper Double-ended clipper Clamper X Y --- --------- Vo VAC= 12V(pp) 1kHz R=1MΩ C =10uf D VR=2V CRO Vi Vin +6v 0 t -6v Vout x 0 t
  • 7. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 7 Experiment No. 2 RELAXATION OSCILLATOR USING OP - AMP Aim: To simulate a rectangular wave form generator (Opamp relaxation oscillator) and compare the frequency and duty cycle with the design specifications Theory: The circuits generate rectangular waveform of specified frequency. Op-Amp is used as comparator which compares the voltage at non inverting terminal with capacitor voltage. When the voltage at the output is +βVsat, the capacitor charges to this voltage through R1 during which output remains at +βVsat. When the capacitor voltage exceeds +βVsat output switches to –βVsat and the capacitor starts discharging through R2 to –βVsat. When the capacitor voltage goes below –βVsat, the output again switches back to +βVsat. Thus oscillations are generated, and the time period of oscillation depends on R1, R2, R3, Rf and C. Components and Equipments required: 1) Op-Amp – μA741 2) Resistors - 1K, 2K, 10K, 20K. 3) Capacitor – 0.1uf 5) Power supply (±15V) DC voltage 6) Diodes – D1N4007 – 2Nos. CIRCUIT DIAGRAM: CALCULATION: β = 4 3 3 R R R  = k k k 10 10 10  = 0.5 For the above circuit D2 R2=2kΩ R1= 1kΩ D2 R4= 10kΩ R3= 10kΩ
  • 8. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 8 TON = R1 C ln           1 1 = 1k * 0.1uf * 1.1 TON = 0.11mSec TOFF = R2 C ln           1 1 = 2k * 0.1uf * 1.1 TOFF = 0.22mSec Total time period T = TON + TOFF = 0.11mSec + 0.22mSec T = 0.33mSec Duty cycle (D) = T TON = sec 33 . 0 sec 11 . 0 m m = 0.33 *100 = 33% F = T 1 = sec 33 . 0 1 m = 3kHz WAVEFORMS: Procedure: 1. Follow the simulation steps given in Expt No 6. 2. Use the available cursor on the simulated window to measure the frequency and duty cycle and compare with the theoretical value. V +Vsat Vo +βVsat Vc 0 -βVsat -Vsat TON TOFF
  • 9. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 9 Results: The practical time periods are measured and compared with theoretical values and tabulated as shown below: TON TOFF VoMAx Vo MIN Vc MAX Vc MIN Duty Cycle Theoretical value 0.11m Sec 0.22m Sec +Vsat = 12v –Vsat = - 12v +βVsat = 6v –βVsat =-6v 33% Practical Value
  • 10. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 10 Experiment No.3 SCHMITT TRIGGER Aim: To simulate a Schmitt trigger using Op-amp and compare the UTP andLTP values with the given specification. Theory: A Schmitt trigger is a circuit which converts any slow varying waveform into a waveform having abrupt transitions. In the Schmitt trigger circuit op-amp is used as a comparator. A Schmitt trigger is characterized by two voltage levels : 1. UTP – Upper Trigger Point 2. LTP - Lower Trigger Point The circuits can be realized to have equal UTP and LTP values or with unequal values using a reference voltage. Components/ Apparatus Required: 1) OP-AMP - μA74l 2) Resistors l0KΩ, 3.3KΩ 3) Power supply l2V DC voltage – 2 no. 4) Sinusoidal signal generator(VAC) 12V, 1kHz. CIRCUIT DIAGRAM: VAC= 12Vpeak 1kHz R1=10kΩ R2=3.3kΩ VR=1.5V CRO Vi +12v 2 7 6 µA 741 3 4 -12v Vo
  • 11. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 11 WAVEFOREMS: CALCULATIONS: For the above circuit: UTP = 2 1 2 R R R Vsat   + 2 1 1 R R R VR  = K K K V 3 . 3 10 3 . 3 * 12  + K K K V 3 . 3 10 10 * 5 . 1  UTP = 4.32v LTP = 2 1 2 R R R Vsat   + 2 1 1 R R R VR  = K K K V 3 . 3 10 3 . 3 * 12   + K K K V 3 . 3 10 10 * 5 . 1  LTP = -1.62v Vin +6v UTP t LTP -6v +Vsat Vout -Vsat t
  • 12. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 12 Procedure: 1. Follow the simulation steps given in Expt No 6 2. Use the available cursor on the simulated window to measure the UTP and LTP values and compare with the theoretical values. Result: Theoretical UTP : ___________ Theoretical LTP : ___________ Practical UTP : _____________ Practical LTP : ____________
  • 13. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 13 Experiment No.4 WEIN BRIDGE OSCILLATOR Aim: To simulate Wein Bridge Ocsillator circuit and verify the frequency generated. Theory: The Wien bridge oscillator is developed by Maxwien in the year 1981. The Wien bridge oscillator is based on the bridge circuit it consists of four resistors and two capacitors and it is used for the measurement of impedance.The feedback circuit is used by the Wien bridge oscillator and the circuit consists of a series RC circuit which is connected to the parallel RC circuit. The Wien bridge oscillator is also called as a Wheatstone bridge circuit. Components and Equipments required: 1) Op-Amp – μA741 2) Resistors - 1k,1k,10k,20k 3) Capacitor – 0.1uf(2 no.) 5) Power supply (±12V) DC voltage CIRCUIT DIAGRAM: CALCULATION: Frequency of Oscillation fo = C R * * * 2 1  = 1.59 K Hz Where R=1K, C=0.1uf 0 0 U1 uA741 3 2 7 4 6 1 5 + - V+ V- OUT OS1 OS2 R1 1k R2 1k R3 20k R4 10k C1 0.1uf C2 0.1uf V1 12V V2 12V
  • 14. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 14 WAVEFORM: Procedure: 1. Follow the simulation steps given in Expt No 6 2. Use the available cursor on the simulated window to note down the frequency of oscillation. Results: Observations/ Quantity Time Period(T) Voltage(V) Theoretical: Practical:
  • 15. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 15 Experiment No. 5 POWER SUPPLY Aim: To determine the working of a power supply and observe the waveforms. Theory: Regulated power supply is necessary in some electronic circuits especially in Amplifier circuits. Poorly regulated power may cause buzzing and unwanted noise in RF and amplifier circuits.Rectifier is an electronic circuit consisting of diodes which carries out the rectification process. Rectification is the process of converting an alternating voltage or current into corresponding direct (DC) quantity. The input to a rectifier is AC whereas its output is unidirectional pulsating DC.Although a half wave rectifier could technically be used, its power losses are significant compared to a full wave rectifier. As such, a full wave rectifier or a bridge rectifier is used to rectify both the half cycles of the ac supply (full wave rectification). The rectified voltage from the rectifier is a pulsating DC voltage having very high ripple content. But this is not we want, we want a pure ripple free DC waveform. Hence a filter is used. Different types of filters are used such as capacitor filter, LC filter, Choke input filter, π type filter. The figure shows a capacitor filter connected along the output of the rectifier and the resultant output waveform.The output voltage or current will change or fluctuate when there is a change in the input from ac mains or due to change in load current at the output of the regulated power supply or due to other factors like temperature changes. This problem can be eliminated by using a regulator. A regulator will maintain the output constant even when changes at the input or any other changes occur. Transistor series regulator, Fixed and variable IC regulators or a zener diode operated in the zener region can be used depending on their applications. IC’s like 78XX and 79XX (such as the IC 7805) are used to obtained fixed values of voltages at the output. Components and Equipment’s required: 1) Diodes-DIN4007( 1 Nos) 2) Resistor 0.5K,10k 3) Capacitor 470uf 4) Sinusoidal signal generator(Vsin) 12V(PP), 1 kHz 5) LM 7805 IC Circuit diagram: 0 V1 DC = 0 VOFF = 0 VAMPL = 12 FREQ = 1k AC = 12 D1 D1N4007 R1 0.5k C1 470uf U1 LM7805C 1 2 3 IN OUT GND R2 10k
  • 16. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 16 Waveform: Procedure: 1. Use the available cursor on the simulated window to observe different waveform at various output points. Results:
  • 17. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 17 Experiment No. 6 RC COUPLED AMPLIFIER Aim:To build and simulate CE amplifier (RC coupled amplifier) for itsfrequency response and measure the bandwidth. Theory: RC Coupled Amplifier is an audio frequency amplifier. It is an amplifier that couples input signal to the output by coupling capacitors and collector resistance. The amplifier is biased using voltage divider bias which provides highest stability. The 3db point helps on determining the Bandwidth of the amplifier. The Amplifier has a bypass capacitor which avoids negative feedback and thus increases the amplifier gain. Components and Equipment’s required: 1) Transistor (BJT) – Q2N2222 2) Resistors – 82K, 18K, 4.7K, 1K and 1000K 3) Capacitors – 0.1uf (2 each), 10uf(2 each), 47uf 4) Sinusoidal signal generator(VAC) 20mV(PP), 1 kHz 5) Power supply 10V (VDC) CIRCUIT DIAGRAM: VAC= 20mv(pp) , 1KHz CRO 82K 4.7K 10uf 10uf Q2N2222 10V 1000K 18K 1K 47uf
  • 18. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 18 FREQUENCY RESPONSE: Procedure: 1. Create the schematic shown above using the following steps.  Double click on “capture CIS” icon on the desktop  Click on file – New – Project to create a new project  Name the project (Preferably same name as of the circuit)  Create the schematic on the schematic window by selecting the parts from the library and inter connecting them using wires.  The parts will have default values and are to be changed to the required design values  Place voltage markers on the input and output ends of the circuit 2. Apply parameters for simulation in the new simulation profile window and click on Run 3. Use the available cursor on the simulated window to note down the bandwidth Results: The response of the RC coupled amplifier is simulated and the Bandwidth is _________ Hz Vo In max Vo volts max Vo/ √2 0 fL fHFreq BW = fH - fL
  • 19. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 19 Experiment No 7. HALF/FULL ADDER AND HALF/FULL SUBTRACTORS Aim:Realization of Half/Full adder and Half/Full Subtractors using logic gates. Components/Apparatus required: 1) AND, OR, NOT, EX-OR gates -02 Nos. each 2) Digital trainer kit. 3) Patch chords. 1) Half adder Circuit diagram: Truth Table 2) Full adder Circuitdiagram: Truth Table INPUT A INPUT B OUTPUT Sum OUTPUT Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 INPUT A INPUT B INPUT CIN OUTPUT S OUTPUT COUT 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
  • 20. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 20 3) Half Subtractor Circuit diagram: Truth Table 4)FullSubtractor Circuit diagram: Truth Table Procedure: 1) Make connections as shown in the circuit diagram. 2) Connect input to +5v for logic 1 and to ground for logic 0 3) Verify the truth table. INPUT X INPUT Y OUTPUT D OUTPUT B 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 INPUT X INPUT Y INPUT Z OUTPUT D OUTPUT B 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1
  • 21. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 21 Experiment No. 8 VHDL CODE TO REALIZE FULL ADDER AND FULL SUBTRACTORS Aim: Design and develop VHDL code to realize Full adder and Full Subtractors. Steps in Using the Xilinx software for writing VHDL Code: 1. Double click on “Xilinx ISE 9.1i” icon on the desktop. 2. Click on File- New project. 3. Give a name (preferably same name as the experiment name) and click on next. 4. In the new project wizard select Family as “Automotive Spartan3” and simulator “ISE simulator (VHDL/Verilog)” and prefer language“VHDL”. Click on next. 5. Click on “New source” and next. 6. Enter the same file name as given in step 3 and select “VHDL module” click on next. 7. Enter the port name, direction and bus information given in the VHDLprogram under Entity. Click on next. 8. After ensuring the port definition clicks on finish if not go back to re-enter the values for step 7 and then click on next. 9. Click on finish to enter the editor window and enter the VHDL code. 10. Save the file and check for syntax (by expanding codes “synthesize-XST”) 11. Double click on “Create new source” and enter the file name. Select“Test Bench Waveform” and click on next - next – finish. 12. Select single clock/ combinational under “clock information” and clickon finish. 13. Select the inputs as high and low by clicking the mouse on the required inputs and save. 14. Select “Behavioral simulation” under sources and select “.tbw file” 15. Click on process and expand “Xlinx ISE simulator” and double click on simulate behavioral module to observe the output waveforms. 16. Use cursor to verify truth table / result Note: The above steps have to be used for all VHDL simulations. 1) VHDL code for Full adder: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityfull_adder is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end full_adder; architecture behavioural of full_adder is
  • 22. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 22 begin sum<= a xor b xor c; carry<=((a xor b )and c) or (a and b) ; end behavioural; Output waveform: 2)VHDL code for Full Subtractor: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full_subtractor is port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; difference : out STD_LOGIC; borrow : out STD_LOGIC); end full_subtractor; architecture behavioural of full_subtractor is begin difference <= a xor b xor c; borrow <= ((not a) and b) or ((not(a xor b)) and c); end behavioural; Output Waveform:
  • 23. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 23 OBSERVATIONS 1.) What are the errors encountered in conducting the experiment/compilation? 2.) Measures taken to fix the problem (circuit debug/logical errors)? 3.) Results ASSIGNMENT 1.) Realize the full adder using 3:8 decoder and verify the behavior. VIVA QUESTIONS 1.) The full adder realized in this experiment is a.) 4-bit adder b) 2-bit adder c) 3-bit adder d) 1-bit adder 2.) Draw the block diagram for 3-bit parallel adder. 3.) Write the 2’s compliment of the following numbers a.) 00001111 b.) 01011010 c.) 10111110 4.) Subtract 64 from 89 using 2’s compliment addition.
  • 24. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 24 Experiment No. 9 8:1 MULTIPLEXER Aim: Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the simplified logic expression using 8:1 multiplexer IC Components/Apparatus required: 1) Multiplexer IC74151. 2) Digital IC Trainer Kit. 3) Patch Chords. TRUTH TABLE: IMPLEMENTATION TABLE: A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 D = 0 Y = 0 Y = 1 Y = 0 Y = 1 Y = 1 Y = 1 Y = 1 Y = 1 D = 1 Y = 1 Y = 1 Y = 0 Y = 0 Y = 1 Y = 0 Y = 1 Y = 0 Mux I/P I0 = D I1 = 1 I2 = 0 I3 = D I4 = 1 I5 = D I6 = 1 I7 = D A B C D Y 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0
  • 25. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 25 CIRCUIT DIAGRAM: PROCEDURE: 1. Convert any given Boolean Expression into Σm( ) notation. 2. Write the Implementation table for the given expression. 3. Find the inputs to be applied to the inputs of the Multiplexer. 4. Make connections as per the implementation table. 5. Apply the inputs using Switches on the Trainer kit and verify the output LEDs on the Trainer kit. 6. Verify the truth table 0 74LS04 1 2 74HC151 7 16 4 3 2 1 15 14 13 12 11 10 9 6 5 E VCC I0 I1 I2 I3 I4 I5 I6 I7 S0 S1 S2 Z Z Y +5V D GND 8 C B A I C 7 4 1 5 1
  • 26. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 26 Experiment No.10 VHDL CODE FOR AN 8:1 MULTIPLEXER Aim: Design and develop the VHDL code for an 8:1 multiplexer. Simulate and verify it’s working. VHDL code for 8:1 MUX library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux8to1 is Port ( sel : in STD_LOGIC_vector(2 downto 0); din : in STD_LOGIC_vector(7 downto 0); dout : out STD_LOGIC); end mux8to1; architecture Behavioral of mux8to1 is begin process(sel,din(7), din(6), din(5), din(4), din(3), din(2), din(1), din(0)) begin casesel is when "000"=>dout<=din(7); when "001"=>dout<= din(6); when "010"=>dout<= din(5); when "011"=>dout<= din(4); when "100"=>dout<= din(3); when "101"=>dout<= din(2); when "110"=>dout<= din(1); when "111"=>dout<= din(0); when others=>null; end case; end process; end Behavioral;
  • 27. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 27 Output waveform: OBSERVATIONS 1.) What are the errors encountered in conducting the experiment/compilation? 2.) Measures taken to fix the problem(circuit debug/logical errors) 3.) Results ASSIGNMENT 1.) Realize the Boolean Expression Y= πM(1,2,3,6,8,9,10,12,13,14) using 8:1 Multiplexer IC VIVA QUESTIONS 1.) Draw the block diagram of a 4:1 multiplexer and a 2:1 multiplexer. 2.) Realize a 8:1 multiplexer using two 4:1 multiplexer and a 2:1 multiplexer. 3.) A circuit with many inputs and only one output is called a ___________________ 4.) Write a VHDL code for 4:1 multiplexer.
  • 28. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 28 Experiment No.11 RING COUNTER Aim: Design and implement a ring counter using 4-bit shift register and demonstrate its working. Components/Apparatus required: 1) Shift Register IC 7495 2) Digital IC Trainer Kit 3) Patch Chords CIRCUIT DIAGRAM: Procedure: Q0 Vcc Q3 Q2 Q1 Clk1 Clk2 14 13 12 11 10 9 8 I C 7 4 9 5 1 2 3 4 5 6 7 Ds D3 D2 D1 D0 M Gnd
  • 29. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 29 Experiment No.12 VHDL code for switched tail counter Aim: Design and develop the Verilog / VHDL code for switched tail counter. VHDL code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityjohnson is Port ( clk : in STD_LOGIC; q :inout STD_LOGIC_VECTOR (3 to 0) :="0000"); endjohnson; architecture Behavioral of johnson is begin process(clk) begin if(clk'event and clk='0') then q(3)<= not(q(0)); fori in 3downto 1 loop q(i-1)<= q(i); end loop; end if; end process; end Behavioral; WAVEFORM: Clk q3 q2 q1 q0
  • 30. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 30 Procedure: Follow the steps given for simulation of experiment 1b. OBSERVATIONS 1.) What are the errors encountered in conducting the experiment/compilation? 2.) Measures taken to fix the problem (circuit debug/logical errors) 3.) Results ASSIGNMENTS 1.) Modify the above ring counter circuit to Johnson counter. 2.) Modify the above VHDL code for a ring counter. VIVA QUESTIONS 1.) List the difference between ring counter and Johnson counter. 2.) List the different type of shift register. 3.) Draw the circuit of a 3-bit ring counter using JK-flip flop.
  • 31. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 31 IC Pin Configuration Sheet: e IC 7400 2 I/P NAND GATE IC 7402 2 I/P NOR GATE IC 7404 NOT GATE IC 7408 2 I/P AND GATE IC 7410 3 I/P NAND GATE IC 7432 2 I/P OR GATE
  • 32. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 32 IC 7410 3 I/P NAND GATE IC 74138 Decoder IC 7411 3 I/P AND GATE IC 7486 2 I/P EXOR GATE IC 7476 JK FLIP FLOP IC 7420 4 I/P NAND GATE IC 7427 3 I/P NOR GATE
  • 33. Analog and Digital Electronics Lab REVA University School of Computing and Information Technology Page 33 Components names of Analog Circuits Sl.No Component Name Library Part Code 1 Resistor Analog R 2 Capacitor Analog C 3 Sine wave Source Vsin 4 DC supply Source Vdc 5 Opamp Opamp uA741 6 Diode Diode D1N4007 7 Transistor Bipolar Q2N2222 8 Voltage Regulator Opamp LM7805C 9 Ground GND(0/Source) IC 74151 8:1 Mux IC uA741 OPAMP IC 555 Timer