Analysis and Impacts of Negative Bias Temperature Instability

2012 IEEE Students’ Conference on Electrical, Electronics and Computer Science

Analysis and Impacts of Negative Bias Temperature
Instability (NBTI)
Rajeev Kumar Mishra1, Amritanshu Pandey2, Sarfraz Alam3
Department of Electronics
Institute of Technology, Banaras Hindu University
Varanasi, India
1
rajeev.mishra.ece10@itbhu.ac.in, 2amritanshup@gmail.com, 3sarfraz.alam.ece10@itbhu.ac.in

Abstract— As the Integrated Circuits (IC) density keeps on oxide by the interface states creation and hole trapping in the
increasing with the scaling of CMOS devices in each successive vicinity of the interface. An interface trap is created when a
technology generation, reliability concerns mainly Negative Bias negative voltage is applied to the gate of a PMOS device for a
Temperature Instability (NBTI) becomes a major challenge. prolonged time. An interface trap is located near the Si-oxide
NBTI degrades the performance of a PMOS transistor under a
boundary where holes (positive charge) can get stuck, and
negative gate stress. The after effects of NBTI include: (a)
threshold voltage increase of PMOS transistor, (b) drain current hence, they shift the threshold voltage. NBTI is a result of
degradation, and (c) speed degradation. Elevated temperature continuous trap generation in Si-SiO2 interface of PMOS
and the negative gate stress play an important role in transistors. In bulk MOSFET structure, undesirable Si
degradation of Gate Oxide which further degrades the above said dangling bonds exist due to structural mismatch at the Si-SiO2
parameters. Before any circuit design Stress Analysis becomes interface. These dangling bonds act as charged interfacial
important for any device in order to get the complete traps. Charge can flow between the semiconductor and the
performance of the circuit. Negative bias temperature instability interface states. The net charge in these interface states is a
(NBTI) has become the dominant reliability concern for function of the position of the fermi level in the bandgap.
nanoscale PMOS transistors. In this paper basically we have
Hydrogen passivation is applied to the Si surface after the
analysed the effect of temperature variations on NBTI for a
buffer. oxidation process to transform dangling Si atoms to Si-H
bonds. However, with time, these Si-H bonds can easily break
Keywords- NBTI, Reliability, Threshold Voltage, Temperature, during operation (i.e., negative bias for PMOS). The broken
AC DC Stress, EZwave. bond acts as interfacial traps and increases the threshold
voltage (VT) of the device, thus affecting the performance of
I. INTRODUCTION the IC. NBTI impact gets even worse in scaled technology due
NBTI occurs under negative gate voltage (e.g., V gs= -VDD) to the higher operation temperature and the usage of ultra thin
and is measured as an increase in the magnitude of threshold oxide (i.e., higher oxide field).
voltage. It mostly affects the PMOS transistor [1] and The following conditions holds good for the NBTI effect
degrades the device drive current, circuit speed, noise margin, (1) PMOS needs to be inverted i.e. Formation of channel but
and other factors. As the gate oxide gets thinner than 4nm, the doesn’t need any current flow.
threshold voltage change caused by NBTI for the PMOS (2) Needs negative electric field across oxide layer (Enhanced
transistor has become the dominant factor to limit the life at relatively high negative gate voltage Vgs).
time, which is much shorter than that defined by hot-carrier (3) High temperature.
induced degradation (HCI) of the NMOS transistor.
Furthermore, different from HCI that occurs only during There are two components of NBTI based on the pre existing
dynamic switching, NBTI is caused during static stress on the interface traps and the creation of the new interface states.
oxide even without current flow. NBTI degradation in They are classified as Permanent (Non-Recoverable) and
MOSFETs is explained by the reaction-diffusion model temporary (Recoverable). Permanent NBTI is due to the new
mentioned in next section. interface traps generation i.e. the electric field is able to break
Si-H bonds located at the silicon-oxide interface. Temporary
A gradual shift of threshold voltage (VT) over time is NBTI is due to some pre-existing traps present in the gate
commonly observed in p type metal-oxide-semiconductor oxide. The pre existing traps get filled with the holes coming
field-effect transistors (p-MOSFET or PMOS). This shift is from the channel of PMOS. This is called temporary because
mainly caused by: (1) voltage stress on the gate oxide (2) the traps can be emptied when the stress voltage is removed.
temperature, (3) the duty cycle of the stressing voltage (static Even after the removal of the stress the final increase in
stress as compared to dynamic stress). This effect has become threshold voltage is mainly due to the permanent NBTI and
more severe as: Transistor dimensions have shrunk, the partly due to temporary NBTI as shown in the fig. 1 as Stress
electric field applied to the gate oxide has increased and the phase and Recovery phase.
operating voltage has become lower. NBTI degrades the gate

978-1-4673-1515-9/12/$31.00 ©2012 IEEE

degradation of the PMOS devices in terms of different sub-
processes involving the bond breaking process and generation
of interface traps.
According to the RD model, NBTI degradation originates
from Silicon Hydrogen bonds (Si-H) breaking at Silicon-
Silicon dioxide (Si-SiO2) interface during negative stress
(Vgs=-VDD), as shown in Figure 2. The broken Silicon bonds
(Si-), dangling silicon act as interface traps that are
responsible for higher VT and lower drain current.
Interface traps Nit generation is due to the dissociation of Si-H
Figure 1: Temporary & Permanent phase of NBTI bonds at the Si/SiO2 interface and subsequent movement of
released hydrogen species away from the interface (diffusion),
which leaves behind Si- dangling bonds (interface traps)
II. PARAMETER DEPENDANCIES .Inversion layer holes tunnel into the oxide and interact with
Si-H bonds. The holes get captured and take away one
As discussed above the main parameter which is affected by electron from the Si-H bonds and make them weak. The
the NBTI is Threshold Voltage (VT). NBTI raises threshold weakened Si-H bonds then get broken by thermal excitation or
voltage above the initial value and hence subsequently otherwise. The released hydrogen species either diffuse away
degrades the other parameters like drain current, from the Si/SiO2 interface and leaves behind Si- (Nit
transconductance etc which depend on threshold voltage. The generation), or reacts back with Si- and form Si-H (Nit
relationship between threshold voltage and interface trapped passivation). It is worth noting that the magnitude of N it is
charges is given by equal to the number of released H atoms at any given instant
VT VFB 2) F QB / Cox of time. The time evolution of Nit generation is modeled by the
Where following equations.
Si H o Si x H
IF kT / q ln N D / ni , QB 4qK S 0 I F N D
1/ 2
Si H H o Si x H2
QF Qit (I S )
VFB I MS
COX COX
Where QF is the fixed charge density, Qit is interface trap
density COX is the gate oxide capacitance and ΦMS is the work
function between metal and semiconductor. The MOS drain
current ID (sat) and transconductance gm is related with
threshold voltage as,
ID W P C V VT 2
2 L eff OX G
gm W P C V VT .
2 L eff OX G
Thus we see that the Threshold voltage VT of a MOS is
dependent on QF and Qit. As the threshold voltage is increased
Figure 2: Representation of RD model [3]
due to the NBTI (due to increase in interface traps) the drain
current ID and transconductance gm also degrades. The H atoms released from Si-H bond breaking contribute to
A shift in the threshold voltage (VT) ΔVth of the PMOS three sub-processes including: (a) diffusion towards the gate,
transistor is proportional to the interface trap generation due to (b) combination with other H atoms to produce H2, or (c)
NBTI, which can be expressed as [2], recovery of the broken bonds. Similarly, H2 participate in the
qN it t diffusion towards poly gate or dissociation to produce H
'Vth 1 m
COX atoms.
The R-D model takes the accumulation of hydrogen in the
Where m represents equivalent VT shifts due to mobility
gate oxide as well as the loss of hydrogen into the poly into
degradation (or model parameter), q is the electronic charge,
account in order to predict the long-time degradation. As the
and Nit (t) is the interface trap generation, which is the most
hydrogen molecules diffuses into the ploy from the SiO2, the
important factor in evaluating performance degradation due to
probability of recovery (Si passivation) becomes very less so
NBTI.
there is an increase in the interface trap generation and this is a
III. MECHANISM OF NBTI temperature dominant process. As the temperature is increased
the chances of diffusion of hydrogen molecules into the poly
Mechanism involved in Negative Bias Temperature
increases and hence decreases the probability of recovery
Instability is better understood by the Reaction Diffusion
during the recovery phase.
model (RD model) [3], which explains the physics behind the

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Figure 4: Pulse showing stress and relaxation phase of a PMOS

But the degradation rate is different (smaller) from “DC”
stress conditions when the device is permanently stressed.
This has often led to the conclusion that AC stress was less
problematic than DC stress. The degradation rate under AC
stress conditions actually depends on the duty cycle of the
applied stress signal [5][7].
Figure 3: Fig showing RD model (a) Hole tunneling, capture and
dissociation of Si-H bonds and subsequent diffusion of hydrogen
away from the Si/SiO2 interface(b) Faster hydrogen diffusion after H
front reaches the SiO2/poly interface, triggering faster interface-trap
buildup [4]
The NBTI is mostly observed in the PMOS[1] devices only
and appears to be negligible in NMOS because of the fact that
interface traps can induce positive as well as negative charge
at the interface. Interface traps readily exchange charge, either
electrons or holes, with the substrate and they introduce either
positive or negative net charge at interface, which depends on
gate bias: the net charge in interface traps is negative in n-
channel devices (NMOS), which are normally biased with
positive gate voltage, but is positive in p-channel devices
(PMOS) as they require negative gate bias to be turned on. On
the other hand, charge found trapped in the centers in the Figure 5: NBTI Degradation under DC and AC stress with different
oxide is generally positive in both n- and p-channel MOS duty cycles [6]
transistors and cannot be quickly removed by altering the gate
bias polarity. So the net effect i.e. interface charge and oxide
charge is positive charge in case of PMOS and almost IV. SIMULATION RESULTS AND DISCUSSION
negligible for NMOS.
There can be two types of NBTI stress, it can be DC or AC ELDO is a circuit simulator developed by Mentor Graphics,
stress. Once NBTI stress is removed from the device, a which delivers all the capability and accuracy of the SPICE
fraction of Interface traps Nit can self-anneal, resulting in Vth level simulation for complex analog circuits and SoC designs.
degradation being partially recovered. This recovery NBTI reliability simulation in Eldo is based on a model, which
mechanism can be observed when a device is subject to a models the difference between the fresh and aged devices by
strain of stressing pulses. These conditions are called “AC” calculating the NBTI stress which is dependent on the applied
stress. Within the context of reliability, AC stress actually gate stress and the temperature. The following results are of a
designates a large-signal pulse-like stress signal. During the buffer circuit (for 45nm design), which has been simulated in
first phase of the clock cycle, Vth increases due to the stress the tool ELDO. The buffer is designed in a way such that two
applied, and then it decreases again in the second half of the inverters are connected back to back and thus uses two PMOS
cycle when the stress is removed as shown in the figure 4 (XIP1.M1 and XIP2.M1) and two NMOS. The below results
below. As shown in the figure, a CMOS inverter is drawn and are shown in the waveform viewer EZWave, used to view the
when the Vg i.e. input gate voltage is zero (i.e. Vgs= -VDD), the output waveforms of ELDO file. Firstly a buffer circuit is
PMOS will be in the Stress phase and when V g is VDD (i.e. described by a .cir file in the ELDO using the slow model of
Vgs= 0) then PMOS will be in relaxation phase as shown. 45nm technology. Then simulation is carried out with this .cir
During Stress phase the effect of NBTI comes into picture. file. During simulation, first stress file is generated in which
stress for each device is calculated as per the ELDO’s UDRM

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model and aged simulation uses this stress file to find the
degradation.

Figure 8:Input and Output of a buffer when temperature is 125'C

As can be seen from the results that when the temperature is
increased from 27’C to 125’C the output is degraded much
more (checked at the same time at t=14.504ns). For T=27’C
V(OUT)_1 is 1.17359V and V(OUT)_2 is 1.11157, similarly
for T=125’C V(OUT)_1 is 1.07925V and V(OUT)_2 is
0.94825V.
Figure 6: Buffer output showing input, output, stress and threshold
voltage V. CONCLUSION
The values shown are for the input pulse whose magnitude is Based on the simulation results with an industrial 45nm
2V, rise time and fall time is 5nsec, pulse width is 30nsec and technology, it is observed that the degradation of threshold
period is 60nsec. The transient analysis is done for 500ns in voltage due to NBTI can be as high as 9% for a stress period
ELDO and the whole simulation is run for the period of 2years of two years. As far as temperature variation is concerned, at
(i.e output is checked after 2 years). The V(OUT)_1 value in room temperature the degradation of output is about 5% which
yellow color is fresh output and V(OUT)_2 with blue color is is increased to about 11% at a temperature of 125’C.So Lower
output after 2 years. At a particular time stamp of 16.19718ns temperature is also desirable for robust nanoscale design. The
the values are (shown in the rectangular boxes): transistor reliability will be a severe problem in future
technology nodes which makes the device life time shorter
Type of V(OUT) VTH(XIP1.M1) VTH(XIP2.M than predicted.
Simulation in V in V 1) in V
VI. REFERENCES
Fresh 1.73105 -0.514075 -0.528809 [1] http://www.iue.tuwien.ac.at/phd/entner/node27.html Physical
Mechanism of NBTI”. Institute for Microelectronics, Wien Austria.
After 2 yrs 1.67543 -0.561106 -0.577066
[2] Kunhyuk Kang, Muhammad Ashraful Alam, and Kaushik Roy,
Apart from these values the instantaneous stress is also plotted “Characterization of NBTI induced Temporal Performance Degradation
in Nano-Scale SRAM array using IDDQ”. Purdue University, West
for the two PMOS’s as shown in the Fig 6. We can see the Lafayette, Indiana, USA
degradation in the output after 2 yrs due to stress in the PMOS [3] R. Wittmann, H. Puchner, L. Hinh, “Impact of NBTI-Driven Parameter
devices. Degradation on Lifetime of a 90nm p-MOSFET”, Institute for
Microelectronics TU Wien.
The following result shows the buffer output at temperature
[4] S Mahapatra, P.Bharath Kumar, Student Member, IEEE,and
27’C M.A.Alam, “Investigation and Modeling of Interface and Bulk Trap
Generation During Negative Bias Temperature Instability of p-
MOSFETs”, IEEE Transactions on electron devices, Vol. 51, No. 9,
September 2004
[5] Wenping Wang, Vijay Reddy, Anand T. Krishnan, Rakesh Vattikonda,
Srikanth Krishnan, and Yu Cao, “An Integrated Modeling Paradigm of
Circuit Reliability for 65nm CMOS Technology,” IEEE 2007 Custom
Integrated Circuits Conference (CICC).
[6] Renju Raju, Thomas “Reliability Implications of Bias-Temperature
Instability in Digital ICs”. Technical University Munich.
[7] Cyril Desclèves, Mark Hagan, Mark Hagan “Joint Design–Reliability
Flows and Advanced Models Address IC-Reliability Issues”.
[8] http://www.iue.tuwien.ac.at/phd/wittmann/node10.html “NBTI
Reliability Analysis”.
[9] Seyab, Said Hamdioui (Delft University of Technology) “Temperature
Impact on NBTI Modeling in the Framework of Technology Scaling”.
Figure 7: Input and Output of a buffer when temperature is 27'C
[10] Chittoor Parthasarathy (ST), Philippe Raynaud (Mentor Graphics)
When the temperature is increased to 125 ‘C the output is, “Reliability simulation in CMOS design using Eldo”.

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Analysis and Impacts of Negative Bias Temperature Instability

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