![Consumption decreased in March, whereas revenues
increased, causing growing IC inventory level
3mma IC revenue, inventory and inventory days
35 3mma IC inventory value (left) Current 3mma inventory value 120
3mma IC revenues (left) at around $27 B
3mma IC revenues/3mma IC inventories [B$]
3mma IC consumption: revenues ± inventory value change (left)
30 3mma Inventory days (right) 100
25
IC inventory days
80
20
60
15
40
10
20
5
0 -
Jan-01
Jul-01
Jan-02
Jul-02
Jan-03
Jul-03
Jan-04
Jul-04
Jan-05
Jul-05
Jan-06
Jul-06
Jan-07
Jul-07
Jan-08
Jul-08
Jan-09
Jul-09
Jan-10
Jul-10
Jan-11
Source: VLSI Research, WSTS, ASML
Last data point: March 2011
/ Slide 13](https://image.slidesharecdn.com/asml2011052520110525dbconferencesingapore-13070038456088-phpapp02-110602033844-phpapp02/85/Public-Presentation-ASML-DB-Conference-Singapore-13-320.jpg)
![DRAM
Further recovery of contract prices leads tier 2/3 manufacturers at low
5x nm (closer) to profitability
<Customer litho system utilizations high>
MAIN DRAM SPOT & CONTRACT PRICES (01/2008 - 2011YTD)
3 1Gb DDR2 800 MHz SPOT PRICE
1Gb DDR2 800 MHz CONTRACT PRICE
2.8 1Gb DDR3 1333 MHz SPOT PRICE About 40%
1Gb DDR3 1333 MHz CONTRACT PRICE cash profit on
2.6 2Gb DDR3 1333MHz SPOT PRICE 2Gb DDR3 ICs,
2Gb DDR3 1333MHz CONTRACT PRICE
if manufactured
2.4 at 4x nm and
sold at current
2.2 contract prices
Chip ASP [$US]
2
Estimated DRAM cash costs in
1.8 Q1/11 (avg. production node in nm)
1.6 (4x H), 2 Gb
1.4 (6x), 1Gb
1.2
(5x H), 1 Gb
1
(5x L), 1 Gb
0.8
0.6 Current DDR3 1 Gb
Poor 5x nm
contract ASP at 0.98 $
yields do
0.4 increase
Apr-08
Aug-08
Apr-09
Aug-09
Apr-10
Aug-10
Apr-11
May-08
Nov-08
May-09
Nov-09
May-10
Nov-10
May-11
Dec-08
Dec-09
Dec-10
Jan-08
Feb-08
Jun-08
Jul-08
Sep-08
Oct-08
Jan-09
Feb-09
Jun-09
Jul-09
Sep-09
Oct-09
Jan-10
Feb-10
Jun-10
Jul-10
Sep-10
Oct-10
Jan-11
Feb-11
Mar-08
Mar-09
Mar-10
Mar-11
avg. costs
Source: DRAMeXchange (5/5/2011), ASML MCC
/ Slide 14](https://image.slidesharecdn.com/asml2011052520110525dbconferencesingapore-13070038456088-phpapp02-110602033844-phpapp02/85/Public-Presentation-ASML-DB-Conference-Singapore-14-320.jpg)
![NAND
SLC spot prices slide after change in product mix in March, overall chip prices remain
quite stable at healthy levels <Customer litho tool utilization remain high>
MAIN NAND SPOT & CONTRACT PRICES (01/2008 - 2011YTD)
20 16Gb NAND SLC SPOT PRICE
19 16Gb NAND SLC CONTRACT PRICE
18 32Gb NAND MLC SPOT PRICE
32Gb NAND MLC CONTRACT PRICE
17 64Gb NAND TLC SPOT PRICE
16 64Gb NAND TLC CONTRACT PRICE
15
14
Chip ASP [$US]
13
12
11 300 mm costs for mature
10 2x nm 64 Gb MLC NAND
9 between 5.5 and 6,5 USD
8
7
6
300 mm cash-costs for 3x
5 nm 32 Gb 2 b/c MLC NAND
4 between 3,2 and 4,0 USD
3 300 mm cash-costs
2 for 3x nm 32 Gb 3 b/c
MLC NAND between
1
2,6 and 3,2 USD
0
Apr-08
Aug-08
Apr-09
Aug-09
Apr-10
Aug-10
Apr-11
May-08
Nov-08
May-09
Nov-09
May-10
Nov-10
May-11
Jan-08
Feb-08
Jun-08
Jul-08
Sep-08
Oct-08
Dec-08
Jan-09
Feb-09
Jun-09
Jul-09
Sep-09
Oct-09
Dec-09
Jan-10
Feb-10
Jun-10
Jul-10
Sep-10
Oct-10
Dec-10
Jan-11
Feb-11
Mar-08
Mar-09
Mar-10
Mar-11
Source: DRAMeXchange (5/5/2011), ASML MCC
/ Slide 15](https://image.slidesharecdn.com/asml2011052520110525dbconferencesingapore-13070038456088-phpapp02-110602033844-phpapp02/85/Public-Presentation-ASML-DB-Conference-Singapore-15-320.jpg)
![Why EUV? EUV supports IC & Lithography roadmap
towards <10nm
200
Resolution (half pitch) "Shrink" [nm]
KrF
100
80
ArFi ArF
AT:1200
60
XT:1400
50
XT:1700i
40 XT:1900i
NXT:1950i
DPT
30
EUV-ADT LOGIC
DPT
20 NXE:3100
NXE:3300 DRAM
EUV
NXE:3350
QPT
10 DPT NAND
8
02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19
Notes: Year of production start Source: Customers, ASML
1. R&D solution required 1.5~ 2 yrs ahead of Production
2. EUV resolution requires 7nm diffusion length resist
3. DPT = Double Patterning
4. QPT = Double Double Patterning
/ Slide 18](https://image.slidesharecdn.com/asml2011052520110525dbconferencesingapore-13070038456088-phpapp02-110602033844-phpapp02/85/Public-Presentation-ASML-DB-Conference-Singapore-18-320.jpg)
![EUV lowers overall costs for customer, while increasing
litho costs
Costs per layer:
Metrology
Strip/Clean
Spacer etch ArFi Spacer imaging:
BARC/ACL/SiON etch
Overall patterning costs (including litho, etching, etc.):
Patterning steps per device layer
Metrology •
Strip/Clean
Trim Etch
70.82 €/wafer
Metrology
ArFi Develop
• Litho costs (2xArFi exposures per layer): 23.36 €/wafer
Expose
ArFi Resist
• Ratio litho costs/overall patterning costs: 33%
ArFi BARC
Metrology
Strip/Clean
Template removal
EUV imaging :
Oxide Etch Back
Metrology
Overall patterning costs: 46.44 €/wafer
Spacer
Metrology
• Litho costs (1x EUV exposure per layer): 31.74 €/wafer
Strip/Clean
BARC/ACL/SiON etch
• Ratio litho costs/overall patterning costs: 68%
Defect
Metrology Metrology
ArFi Develop
Expose
Strip/Clean
ACL Etch Reduced cost/complexity drives
ArFi Resist Metrology
ArFi BARC
SiON/SiC
EUV Develop
Expose
EUV adoption and secures it’s
ACL
Cap layer
EUV Resist
EUV BARC role in lithography for the next
ACL ACL
Spacer Li decade
€ 70.82 * € 46.44 *
Cost per layer [Euro/Wafer]
/ Slide 25
* Source: ASML Strategic Marketing; Cost of Technology
model incl. Capex & Opex – NAND Example](https://image.slidesharecdn.com/asml2011052520110525dbconferencesingapore-13070038456088-phpapp02-110602033844-phpapp02/85/Public-Presentation-ASML-DB-Conference-Singapore-25-320.jpg)
Public Presentation, ASML DB Conference Singapore
- 1. Deutsche Bank Access Asia Conference Singapore Craig DeYoung – Vice President Investor Relations May 25, 2011 / Slide 1
- 2. Safe Harbor "Safe Harbor" Statement under the US Private Securities Litigation Reform Act of 1995: the matters discussed in this document may include forward-looking statements, including statements made about our outlook, realization of backlog, IC unit demand, financial results, average selling price, gross margin and expenses, dividend policy and intention to repurchase shares. These forward looking statements are subject to risks and uncertainties including, but not limited to: economic conditions, product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors (the principal product of our customer base), including the impact of general economic conditions on consumer confidence and demand for our customers’ products, competitive products and pricing, the impact of manufacturing efficiencies and capacity constraints, the pace of new product development and customer acceptance of new products, our ability to enforce patents and protect intellectual property rights, the risk of intellectual property litigation, availability of raw materials and critical manufacturing equipment, trade environment, changes in exchange rates available cash, distributable reserves for dividend payments and share repurchases, uncertainty surrounding the impact of the earthquake and tsunami in Japan and its potential effect on our customers and suppliers and other risks indicated in the risk factors included in ASML’s Annual Report on Form 20-F and other filings with the US Securities and Exchange Commission. / Slide 2
- 3. ASML’s strategy “ To be a technology leader in lithographic systems and software for semiconductor manufacturing, thus enabling our customers to increase the functionality of microchips while reducing the cost and power consumption per function on a chip / Slide 3
- 4. ASML: the number 2 semiconductor equipment supplier in the world in 2010 ASML Headquarters in Veldhoven, the Netherlands / Slide 4
- 5. Agenda Business Overview Market ASML EUV update Outlook and summary / Slide 5
- 7. Total net sales M€ 6,000 5,000 4,508 3,768 4,000 3,582 1,521 Q4 Net sales 955 2,954 1,053 Q3 3,000 494 Q2 934 1,176 2,000 958 697 1,596 Q1 930 844 581 1,069 1,000 942 555 1,452 949 919 742 629 277 0 183 2006 2007 2008 2009 2010 2011 Numbers have been rounded for readers’ convenience. / Slide 7
- 8. Q1 results - highlights Net sales of € 1,452 million, 63 systems shipped valued at € 1,284 million, service and field option sales at € 168 million Gross margin of 44.7% Operating margin of 31.0% Net system bookings of 40 systems, € 845 million Backlog at € 3,330 million, 134 systems with ASP of € 28.4 million for new tools, includes 60 immersion tools Generated € 1,1 billon cash from operations / Slide 8
- 9. Key financial trends 2010 – 2011 Consolidated statements of operations M€ Q1 10 Q2 10 Q3 10 Q4 10 Q1 11 Net Sales 742 1,069 1,176 1,521 1,452 Gross profit 298 459 513 685 649 Gross margin % 40.3% 43.0% 43.6% 45.0% 44.7% R&D costs 120 125 137 141 145 SG&A costs 41 42 48 50 54 Income from operations 137 292 328 494 450 Operating income % 18.5% 27.4% 27.9% 32.4% 31.0% Net income 107 239 269 407 395 Net income as a % of net sales 14.5% 22.4% 22.8% 26.7% 27.2% Units sold 34 43 51 69 63 ASP new systems 25.8 25.6 24.1 22.4 22.5 Net bookings value 1,165 1,342 1,391 2,315 845 Numbers have been rounded for readers’ convenience. / Slide 9
- 10. Backlog in value per March 27, 2011 Total value M€ 3,330 New Used Total systems systems systems Technology Units 115 19 134 Value M€ 3,262 68 3,330 ASP M€ 28.4 3.6 24.9 KrF 19% I-Line 2% ArF ArF dry 5% End-use immersion 74% Region (ship to location) Japan 8% Foundry USA IDM 18% Singapore 13% 22% 17% Taiwan 17% Europe 10% NAND DRAM Korea 34% 27% 25% China 9% Numbers have been rounded for readers’ convenience. / Slide 10
- 12. Business environment Semiconductor manufacturers have shown caution in assessing economic impact of Japanese earthquake on their supply chain and end-product markets Although direct impact to the electronics industry world- wide seems limited, it has caused some of our customers to review their existing equipment delivery and order plans Resulting adjustments are only affecting potential litho system demand above what is currently the analyst’s consensus We continue to expect a total revenue level for 2011 clearly above € 5 billion / Slide 12
- 13. Consumption decreased in March, whereas revenues increased, causing growing IC inventory level 3mma IC revenue, inventory and inventory days 35 3mma IC inventory value (left) Current 3mma inventory value 120 3mma IC revenues (left) at around $27 B 3mma IC revenues/3mma IC inventories [B$] 3mma IC consumption: revenues ± inventory value change (left) 30 3mma Inventory days (right) 100 25 IC inventory days 80 20 60 15 40 10 20 5 0 - Jan-01 Jul-01 Jan-02 Jul-02 Jan-03 Jul-03 Jan-04 Jul-04 Jan-05 Jul-05 Jan-06 Jul-06 Jan-07 Jul-07 Jan-08 Jul-08 Jan-09 Jul-09 Jan-10 Jul-10 Jan-11 Source: VLSI Research, WSTS, ASML Last data point: March 2011 / Slide 13
- 14. DRAM Further recovery of contract prices leads tier 2/3 manufacturers at low 5x nm (closer) to profitability <Customer litho system utilizations high> MAIN DRAM SPOT & CONTRACT PRICES (01/2008 - 2011YTD) 3 1Gb DDR2 800 MHz SPOT PRICE 1Gb DDR2 800 MHz CONTRACT PRICE 2.8 1Gb DDR3 1333 MHz SPOT PRICE About 40% 1Gb DDR3 1333 MHz CONTRACT PRICE cash profit on 2.6 2Gb DDR3 1333MHz SPOT PRICE 2Gb DDR3 ICs, 2Gb DDR3 1333MHz CONTRACT PRICE if manufactured 2.4 at 4x nm and sold at current 2.2 contract prices Chip ASP [$US] 2 Estimated DRAM cash costs in 1.8 Q1/11 (avg. production node in nm) 1.6 (4x H), 2 Gb 1.4 (6x), 1Gb 1.2 (5x H), 1 Gb 1 (5x L), 1 Gb 0.8 0.6 Current DDR3 1 Gb Poor 5x nm contract ASP at 0.98 $ yields do 0.4 increase Apr-08 Aug-08 Apr-09 Aug-09 Apr-10 Aug-10 Apr-11 May-08 Nov-08 May-09 Nov-09 May-10 Nov-10 May-11 Dec-08 Dec-09 Dec-10 Jan-08 Feb-08 Jun-08 Jul-08 Sep-08 Oct-08 Jan-09 Feb-09 Jun-09 Jul-09 Sep-09 Oct-09 Jan-10 Feb-10 Jun-10 Jul-10 Sep-10 Oct-10 Jan-11 Feb-11 Mar-08 Mar-09 Mar-10 Mar-11 avg. costs Source: DRAMeXchange (5/5/2011), ASML MCC / Slide 14
- 15. NAND SLC spot prices slide after change in product mix in March, overall chip prices remain quite stable at healthy levels <Customer litho tool utilization remain high> MAIN NAND SPOT & CONTRACT PRICES (01/2008 - 2011YTD) 20 16Gb NAND SLC SPOT PRICE 19 16Gb NAND SLC CONTRACT PRICE 18 32Gb NAND MLC SPOT PRICE 32Gb NAND MLC CONTRACT PRICE 17 64Gb NAND TLC SPOT PRICE 16 64Gb NAND TLC CONTRACT PRICE 15 14 Chip ASP [$US] 13 12 11 300 mm costs for mature 10 2x nm 64 Gb MLC NAND 9 between 5.5 and 6,5 USD 8 7 6 300 mm cash-costs for 3x 5 nm 32 Gb 2 b/c MLC NAND 4 between 3,2 and 4,0 USD 3 300 mm cash-costs 2 for 3x nm 32 Gb 3 b/c MLC NAND between 1 2,6 and 3,2 USD 0 Apr-08 Aug-08 Apr-09 Aug-09 Apr-10 Aug-10 Apr-11 May-08 Nov-08 May-09 Nov-09 May-10 Nov-10 May-11 Jan-08 Feb-08 Jun-08 Jul-08 Sep-08 Oct-08 Dec-08 Jan-09 Feb-09 Jun-09 Jul-09 Sep-09 Oct-09 Dec-09 Jan-10 Feb-10 Jun-10 Jul-10 Sep-10 Oct-10 Dec-10 Jan-11 Feb-11 Mar-08 Mar-09 Mar-10 Mar-11 Source: DRAMeXchange (5/5/2011), ASML MCC / Slide 15
- 16. ASML EUV update / Slide 16
- 17. Technology - EUV NXE:3100 second generation EUV Three NXE:3100 shipped to date, 3 more to go Progress ongoing to reach target throughput by year end Customer process development started Infrastructure development transitioning to optimization phase (masks, resist, metrology, etc) Revenue recognition expected in 2012 NXE:3300 third generation EUV Commitments received for 10 NXE:3300 production systems, deliveries to start H2 2012 / Slide 17
- 18. Why EUV? EUV supports IC & Lithography roadmap towards <10nm 200 Resolution (half pitch) "Shrink" [nm] KrF 100 80 ArFi ArF AT:1200 60 XT:1400 50 XT:1700i 40 XT:1900i NXT:1950i DPT 30 EUV-ADT LOGIC DPT 20 NXE:3100 NXE:3300 DRAM EUV NXE:3350 QPT 10 DPT NAND 8 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 Notes: Year of production start Source: Customers, ASML 1. R&D solution required 1.5~ 2 yrs ahead of Production 2. EUV resolution requires 7nm diffusion length resist 3. DPT = Double Patterning 4. QPT = Double Double Patterning / Slide 18
- 19. Consumers are the winners Shrink drives manufacturing cost down 10000 $2,305 for 1Gigabyte (GB) 1000 100 $/GByte 10 1 $0.17 for 1 GB 0 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 Note: data iSupply, March 2009. High quality Flash / Slide 19
- 20. Shrink drives device complexity which drives litho opportunity due to a growing number of critical litho layers Average Logic + DSP + MCU immersion layers Average MPU immersion layers 18 18 16 16 14 14 12 12 10 10 8 8 d A l y . a p e s r s i o r n e p E I m x u 6 6 4 4 2 2 0 0 2008 2009 2010 2011 2012 2008 2009 2010 2011 2012 Node 9x,6x 9x, 6x 6x ,4x 6x, 4x 4x, 3x Node 6x, 4x 6x, 4x 4x, 3x 3x, 2x 2x, 1x Source: ASML Marketing (03/11), 300mm wafers only / Slide 20
- 21. Increasing immersion layers per node, per year with shrink in memory too Average DRAM immersion layers Average NAND immersion layers 10 10 8 8 6 6 4 4 2 2 0 0 2008 2009 2010 2011 2012 2008 2009 2010 2011 2012 Node 8x, 6x 6x, 5x 5x, 4x 4x, 3x 3x, 2x Node 5x, 4x 4x, 3x 4x, 3x 3x, 2x 2x, 1x Source: ASML Marketing (03/11), 300mm wafers only / Slide 21
- 22. Typical Patterning Schemes for Critical Layers 2011 Strip & Clean 2013 Hard Mask Etch Defect Inspect Metrology Develop Expose Litho Patterning Process Steps Resist Organic BARC Inorganic BARC Cap Layer Hard Mask Logic NAND DRAM Logic NAND DRAM 32nm 2x nm 3x nm 22nm 1x nm 2xnm ArFi Spacer DPT Spacer DPT Litho DPT 2x Spacer Spacer DPT EUV DPT = Double Patterning / Slide 22 Source: ASML Strategic Marketing
- 23. Cost Impact of Double Patterning 3.0 Relative Patterning Cost 2.5 Reticle Strip/Clean 2.0 Etch Metrology 1.5 CVD 1.0 Litho chemicals Track 0.5 Litho - Logic NAND DRAM Logic NAND DRAM ALL 32nm 2x nm 3x nm 22nm 1x nm 2xnm - ArFi 1D 1D 2x Litho- Double 2D EUV Spacer Spacer Etch Spacer Spacer Source: ASML Strategic Marketing / Slide 23
- 24. Cycle Time Impact of Double Patterning 3.5 3.0 Relative Cycle Time 2.5 Strip/Clean 2.0 Etch Metrology 1.5 CVD 1.0 Litho 0.5 - Logic NAND DRAM Logic NAND DRAM ALL 32nm 2x nm 3x nm 22nm 1x nm 2xnm - ArFi 1D 1D 2x Litho- Double 2D EUV Spacer Spacer Etch Spacer Spacer Source: ASML Strategic Marketing / Slide 24
- 25. EUV lowers overall costs for customer, while increasing litho costs Costs per layer: Metrology Strip/Clean Spacer etch ArFi Spacer imaging: BARC/ACL/SiON etch Overall patterning costs (including litho, etching, etc.): Patterning steps per device layer Metrology • Strip/Clean Trim Etch 70.82 €/wafer Metrology ArFi Develop • Litho costs (2xArFi exposures per layer): 23.36 €/wafer Expose ArFi Resist • Ratio litho costs/overall patterning costs: 33% ArFi BARC Metrology Strip/Clean Template removal EUV imaging : Oxide Etch Back Metrology Overall patterning costs: 46.44 €/wafer Spacer Metrology • Litho costs (1x EUV exposure per layer): 31.74 €/wafer Strip/Clean BARC/ACL/SiON etch • Ratio litho costs/overall patterning costs: 68% Defect Metrology Metrology ArFi Develop Expose Strip/Clean ACL Etch Reduced cost/complexity drives ArFi Resist Metrology ArFi BARC SiON/SiC EUV Develop Expose EUV adoption and secures it’s ACL Cap layer EUV Resist EUV BARC role in lithography for the next ACL ACL Spacer Li decade € 70.82 * € 46.44 * Cost per layer [Euro/Wafer] / Slide 25 * Source: ASML Strategic Marketing; Cost of Technology model incl. Capex & Opex – NAND Example
- 26. ASML’s Unique Holistic Litho Optimisation & Control of future low k1, DP and EUV litho processes ••Optimize scanner Optimize scanner Source-Mask Optimization Tachyon SMO Pre-reticle illumination conditions illumination conditions ••Enlarge process window for Enlarge process window for robust yield robust yield Optical Proximity Correction Tachyon OPC+ ••Verify mask for release to Verify mask for release to manufacturing. manufacturing. Litho Manufacturability Check Tachyon LMC Expand Increase Process window Process control •• Optimize and match Optimize and match Tachyon Pattern Application-Specific Scanner Tuning Production scanners or litho cells for scanners or litho cells for Application-Specific Scanner Tuning Matcher Full Chip specific patterns or reticle specific patterns or reticle •• Monitor and control litho- Monitor and control litho- LithoCell Monitoring & Control BaselinerTM cell performance and LithoCell Monitoring & Control cell performance and process over time process over time YieldStarTM T200 Integrated Metrology Process Feedback Integrated Metrology Process Feedback + FeedBack Control / Slide 26
- 27. ASML Scanner Optimisation & Control enabled through Wafer Metrology & Computational Litho Programmable Programmable Wavefront pupil and polarization Stages Illuminator Lens Sensors ators ipe scanner actu rec Computational CD and Overlay Wafer Lithography improvements Metrology ion Optimization Setup and rat and Tuning Control of lib ca for CD CD and Overlay / Slide 27
- 28. Section Summary Low k1 Double Patterning Lithography enables extension of immersion Lithography bridging the gap until single patterning EUV is available However, Double Patterning presents significant Cost, Process Control, and Cycle Time manufacturing challenges Advanced Optical Metrology enables improved Scanner control and utilisation whilst integrated solutions enable improved Overlay & CD Uniformity through feedback loops & increased correction capability / Slide 28
- 29. Outlook and summary / Slide 29
- 30. Q2 2011 outlook Order intake between € 900 million – €1 billion Net sales around € 1.5 billion Gross margin about 45% R&D at € 150 million SG&A at € 55 million ASML expects 2011 total revenue clearly above € 5 billion / Slide 30
- 31. Cash return € 2.7B cash & cash equivalents at end Q1 2011 € 1 B / 24 month share buy back program in progress 21% of program executed until wk 19 7 million shares repurchased at an average price of € 29.66 Weekly updates available on ASML’s website Dividend for 2010 of € 0.40 per ordinary share (approx. € 175 million) vs. € 0.20 per share in 2009 Share buy back (cumulative) € 250 Millions € 200 € 150 € 100 € 50 €0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Week / Slide 31
- 32. / Slide 32