BCSE205L_Module 4 Computer Architecture Org.pptx

Module 4
Memory SystemOrganization and
Architecture

Topics to be covered
• Memory systems hierarchy: Characteristics,
Byte Storage methods, Conceptual view of
memory cell - Design of scalable memory using
RAM’s- ROM’s chips - Construction of larger size
memories - Memory Interleaving - Memory
interface address map- Cache memory:
principles, Cache memory management
techniques, Types of caches, caches misses,
Mean memory access time evaluation of cache

Introduction
• Programs and the data that processor operate are
held in the main memory of the computer during
execution, and the data with high storage
requirement is stored in the secondary memories.

Characteristics Of Memory Systems
• The key characteristics of memory systems are:
• Location: The computer memory is placed in three different
locations, CPU, Internal and External
• Capacity: It is expressed using two terms: Word size and number
of words.
• Unit of Transfer: It is the maximum number of bits that can be
read or written into the memory at a time
• Access Method: Sequential access and Random access
• Performance: Of the memory system is determined using three
parameters, Access time, Memory cycle time and Transfer rate.
• Physical Type: Two most common physical types used today are
semiconductor memory and magnetic surface memory.
• Physical characteristics: Volatile/Nonvolatile and Erasable/
Nonerasable

Memory Hierarchy / Multilevel Memory

Memory Hierarchy / Multilevel Memory
• Memory unit is essential component of digital
computer since it is needed for storing programs
and data.
• Memory unit that communicates directly with CPU
is called Main memory.
• Devices that provide backup storage is called
auxiliary memory.
• Only programs and data currently needed by
processor reside in the main memory.
• All other information is stored in auxiliary memory
and transferred to main memory when needed.
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BCSE205L_Module 4 Computer Architecture Org.pptx

Main Memory
• It is the memory used to store programs and data
during the computer operation.
• The principal technology is based on
semiconductor integrated circuits.
• It consists of RAM and ROM chips.
• RAM chips are available in two form static and
dynamic.

Main Memory
• ROM is uses random access method.
• It is used for storing programs that are permanent
and the tables of constants that do not change.
• ROM store program called bootstrap loader whose
function is to start the computer software when
the power is turned on.
• When the power is turned on, the hardware of the
computer sets the program counter to the first
address of the bootstrap loader

Cache Memory
• A special very high-speed memory.
• Used to speed up and synchronizing with high-speed CPU.
• Costlier than main memory or disk memory but economical
than CPU registers.
• Extremely fast memory type that acts as a buffer between
RAM and the CPU. It holds frequently requested data and
instructions so that they are immediately available to the CPU
when needed.
• Used to reduce the average time to access data from the Main
memory.
• Smaller and faster memory which stores copies of the data
from frequently used main memory locations.
• Various different independent caches in a CPU, which store
instructions and data.

Terminology
• Locality: memory references to cluster
• Temporal locality: tendency of the time intervals
between references to a given address to be small
• Spatial locality: tendency of the distances between
consecutive memory references to be small
• Memory hierarchy : characteristic of computer
design in which a series of storage technologies are
used such that the access time is faster as the
memory is closer to the processor and the capacity is
larger as the memory is further from the processor

Terminology
• Cache: memory closest to the processor in a
memory hierarchy
• Caching: any storage management technique
exploiting locality
• Upper/lower level: memory closer/further from
the processor
• Block: unit of memory transfer between two
levels in a memory hierarchy. Also called a cache
line

Cache Performance
• Cache hit: If the processor finds that the memory
location
• Cache miss: If the processor does not find the
memory location
• The performance of cache memory is frequently
measured in terms of a quantity called Hit ratio.
Hit ratio = hit / (hit + miss)= Number of hits/total accesses
• Miss penalty : time to move a block from a lower level in
the hierarchy and satisfy the processor’s request

Cache Access Time
Effective access time is a standard effective
average.
effective-access-time = hit-rate * cache-access-time + miss-rate * lower-level-access-time
Miss penalty is defined as the difference between
lower level access time and cache access time.

Lower-Level Traffic
Lower-level-traffic = miss-rate * requested traffic

Cache Memory (Levels of memory)

Cache Memory (Levels of memory)
• Level 1 or Register : Data is stored and accepted that are
immediately stored in CPU. Most commonly used
registers are accumulator, Program counter, address
register etc.
• Level 2 or Cache memory: Fastest memory which has
faster access time where data is temporarily stored.
• Level 3 or Main Memory: Memory on which computer
works currently. It is small in size and once power is off
data no longer stays in this memory.
• Level 4 or Secondary Memory: External memory which is
not as fast as main memory but data stays permanently in
this memory.

Cache mapping
• Usually, the cache memory can store a
reasonable number of blocks at any given
time, but this number is small compared to
the total number of blocks in the main
memory.
• The correspondence between the main
memory blocks and those in the cache is
specified by a mapping function.

Cache Replacement
• When the cache is full and a memory word
(instruction or data) that is not in the cache is
referenced, the cache control hardware must
decide which block should be removed to
create space for the new block that contains
the referenced word.
• The collection of rules for making this decision
constitutes the cache’s replacement algorithm

Cache Mapping
• Following are cache memory mapping techniques
– Direct mapping,
– Associative mapping,
– Set-Associative mapping

Cache Mapping: Direct mapping
• Maps each block of main memory into only one
possible cache line.

Direct Mapping
Consider a cache consisting of 128
blocks of 16 words each, for a total of
2048 (2K) words, and
assume that the main memory is
addressable by a 16-bit address. The
main memory has
64K words, which we will view as 4K
blocks of 16 words each. For simplicity,
we have
assumed that consecutive addresses
refer to consecutive words.
j modulo 128 of the cache
Each cache block is mapped to
32 blocks of main memory
(4096/128)

Direct Mapping
• main memory blocks 0, 128, 256, . . . is loaded into the cache, it is stored in
cache block 0. Blocks 1, 129, 257, . . . are stored in cache block 1, and so on.
• The low-order 4 bits select one of 16 words in a block.
• When a new block enters the cache, the 7-bit cache block field determines
the cache position in which this block must be stored.
• The high-order 5 bits of the memory address of the block are stored in 5 tag
bits associated with its location in the cache.
• The tag bits identify which of the 32 main memory blocks mapped into this
cache position is currently resident in the cache.
• As execution proceeds, the 7-bit cache block field of each address generated
by the processor points to a particular block location in the cache.
• The high-order 5 bits of the address are compared with the tag bits
associated with that cache location.

Direct-Mapped cache
• A particular block of main memory can be mapped
to one particular cache line only.
• Block ‘j’ of main memory will map to line number (j
mod number of cache lines) of the cache.
• There is no need of any replacement algorithm.

Problems
Consider a 64KB direct-mapped cache with a line length of 32
bytes.
a. Determine the number of bits in the address that refer to
the byte within a cache line.
b. Determine the number of bits in the address required to
select the cache line.
Solution-
a. For the given cache, the number of bits in the address to
determine the byte within the line=n = 25
= 5 bits
b. There are 64K/32= 2048 lines in the given cache. The number
of bits required to select the required line 2 11
= 11 bits

Problems
A digital computer has a memory unit of 64K x 16 and a cache memory of
1K words. The cache uses direct mapping with a block size of four words.
– How many bits are there in the tag, block and word fields of the
address format?
– How many blocks can the cache accommodate?
Solution-
• 64 K × 16: 16 bit address; 16-bit data. = 16 bit address
• Number of Cache Blocks = Cache Size / Block Size
• = 1024words / 4 words = 28
= 256 blocks
16 BITS
TAG
(6)
BLOCK /LINE
(8)
BLOCK OFFSET
(2)

Consider a direct mapped cache of size 16 KB with block
size 256 bytes. The size of main memory is 128 KB. Find the
number of bits in tag and Tag directory size.
• Solution:
Given:-
– Cache memory size = 16 KB
– Block size = Frame size = Line size = 256 bytes
– Main memory size = 128 KB
• Consider that the memory is byte addressable
• Number of Bits in Physical Address-
• Size of main memory= 128 KB = 217
bytes
• Thus, Number of bits in physical address = 17 bits

• Solution:
Number of bits in physical address = 17 bits

• Number of Bits in Block Offset-
• Block size = 256 bytes = 28
bytes
• Thus, Number of bits in block offset = 8 bits

Consider a direct mapped cache of size 16 KB with block size
256 bytes. The size of main memory is 128 KB. Find the
• Number of Bits in Line Number-
Total number of lines in cache = Cache size /Line size
• = 16 KB / 256 bytes
• = 214
bytes / 28
bytes = = 26
lines
• Thus, Number of bits in line number = 6 bits

• Number of Bits in Tag-
• = Number of bits in physical address – (Number
of bits in line number + Number of bits in block
offset)
• = 17 bits – (6 bits + 8 bits) = 17 bits – 14 bits
• = 3 bits
• Thus, Number of bits in tag = 3 bits

• Tag Directory Size
• = Number of tags x Tag size
• = Number of lines in cache x Number of bits in tag
• = 26
x 3 bits
• = 192 bits
• = 24 bytes
• Thus, size of tag directory = 24 bytes

Problem-02: Consider a direct mapped cache of size 512 KB
with block size 1 KB. There are 7 bits in the tag. Find Size of
main memory, Tag directory size
• Solution
• Given:
• Cache memory size = 512 KB
• Block size = Frame size = Line size = 1 KB
• Number of bits in tag = 7 bits
• Consider that the memory is byte addressable.

Problem-02: Consider a direct mapped cache of size 512 KB
with block size 1 KB. There are 7 bits in the tag. Find Size of
main memory, Tag directory size
• Number of Bits in Block Offset-
• Block size = 1 KB = 210
bytes
Number of Bits in Line Number
• Cache size / Line size = 512 KB / 1 KB = 29
lines
• Number of bits in line number = 9 bits

Number of bits in physical address
= Number of bits in tag + Number of bits in line number + Number of
bits in block offset
• = 7 bits + 9 bits + 10 bits = 26 bits
Number of bits in physical address = 26 bits
Size of Main Memory-
• Number of bits in physical address = 26 bits
• Thus, Size of main memory = 226
bytes = 64 MB
• Tag Directory Size-
• Tag directory size = Number of tags x Tag size
= Number of lines in cache x Number of bits in tag = = 29
x 7 bits
• = 3584 bits = 448 bytes

3. Consider a direct mapped cache with block size 4 KB. The size of
main memory is 16 GB and there are 10 bits in the tag. Find the Size
of cache memory and Tag directory size.
• Size of main memory = 16 GB
Number of Bits in Physical Address ?
Number of Bits in Block Offset ?
Number of Bits in Line Number ?
Number of Lines in Cache ?
Size of Cache Memory?
Tag Directory Size?

3. Consider a direct mapped cache with block size 4 KB. The size of
main memory is 16 GB and there are 10 bits in the tag. Find the Size
of cache memory and Tag directory size.
• Size of main memory = 16 GB
Number of Bits in Physical Address ? – 34 bits
Number of Bits in Block Offset ? – 12 bits
Number of Bits in Line Number ? -12 bits
Number of Lines in Cache ? -4096 block
Size of Cache Memory? – 16 MB
Tag Directory Size? – 5 KB

Set Associative Mapping
• In k-way set associative mapping,
– Cache lines are grouped into sets where each set contains k number of lines.
– A particular block of main memory can map to only one particular set of the
cache.
– However, within that set, the memory block can map to any freely available
cache line.
– The set of the cache to which a particular block of the main memory can map
is given by
• Cache set number= ( Main Memory Block Address ) Modulo (Number of sets in
Cache)

• A particular block of main memory can be mapped to
one particular cache set only.
• Block ‘j’ of main memory will map to set number (j
mod number of sets in cache) of the cache.
• A replacement algorithm is needed if the cache is full.

2 way set associative
Cache Memory
j mod number of sets in cache
Consider a cache consisting of 128
blocks of 16 words each, for a total of
2048 (2K) words, and
assume that the main memory is
addressable by a 16-bit address. The
main memory has
64K words, which we will view as 4K
blocks of 16 words each. For simplicity,
we have
assumed that consecutive addresses
refer to consecutive words.
memory blocks 0, 64, 128, . . . , 4032 map
into cache set 0, and they
can occupy either of the two block
positions within this set.

Consider a 2-way set associative mapped cache of size 16 KB with
block size 256 bytes. The size of main memory is 128 KB. Find
Number of bits in tag and Tag directory size
• Given: Set size = 2, Cache memory size = 16 K,
Block size = Frame size = Line size = 256 bytes,
Main memory size = 128 KB, consider that the
memory is byte addressable.
• Number of Bits in Physical Address-
bytes

Number of Bits in Block Offset-
bytes
• Number of Lines in Cache-
Total number of lines in cache = Cache size /Line size
= 16 KB / 256 bytes = 214
bytes / 28
bytes = 64 lines

• Number of Sets in Cache-
Total number of sets in cache
• = Total number of lines in cache / Set size
• = 64 / 2 = 32 sets = 25
sets
• Thus, Number of bits in set number = 5 bits

= Number of bits in physical address – (Number of
bits in set number + Number of bits in block offset)
= 17 bits – (5 bits + 8 bits) = 17 bits – 13 bits = 4 bits

= Number of tags x Tag size
• = 64 x 4 bits = 256 bits = 32 bytes

Three types of cache memory mapping

Three types of cache memory mapping
• In a fully associative cache every memory location can be
cached in any cache line. This memory type significantly
decreases amount of cache-line misses, considered as
complex type of cache memory implementation.
• In direct-mapped cache memory location maps to a
single cache line. It can be used once per address per
amount of time. Performance of this cache memory type
is lower than others.
• In N-way-set-associative cache, the most common cache
implementation, memory address can be stored in any N
lines of cache.

Fully Associative Mapping
• A block of main memory can be mapped to
any freely available cache line.
• This makes fully associative mapping more
flexible than direct mapping.
• A replacement algorithm is needed to replace
a block if the cache is full.

Associative
Mapping
A main memory block can be placed
into any cache block position

Consider a fully associative mapped cache of size 16 KB
with block size 256 bytes. The size of main memory is 128
KB. Find the number of bits in tag, Tag directory size.
• Block size = Frame size = Line size = 256 bytes
• Main memory size = 128 KB
bytes
• Number of bits in physical address = 17 bits

Number of Bits in Block Offset
bytes
• Number of bits in block offset = 8 bits
• Number of Bits in Tag

Number of Lines in Cache
• Total number of lines in cache = Cache size/Line size
• = 16 KB / 256 bytes = 214
bytes / 28
bytes = 26
lines
• Tag Directory Size = Number of tags x Tag size
• = 26
x 9 bits = 576 bits = 72 bytes
• Size of tag directory = 72 bytes

Consider a fully associative mapped cache of size 512
KB with block size 1 KB. There are 17 bits in the tag.
Find the size of main memory, Tag directory size

Consider a fully associative mapped cache of size 512
KB with block size 1 KB. There are 17 bits in the tag.
Find the size of main memory, Tag directory size
• Number of Bits in Block Offset
• Block size = 1 KB = 210
bytes

• Number of Bits in Physical Address
Number of bits in physical address = Number of bits
in tag + Number of bits in block offset
• = 17 bits + 10 bits = 27 bits
• Size of Main Memory= Number of bits in physical
address = 27 bits
• Size of main memory = 227
bytes = 128 MB

• Number of Lines in Cache-
Total number of lines in cache = Cache size / Line size
• = 512 KB / 1 KB = 512 lines = 29
lines
• = Number of tags x Tag size
• = 29
x 17 bits = 8704 bits = 1088 bytes

• Consider a 2-way set associative mapped cache of
size 16 KB with block size 256 bytes. The size of
main memory is 128 KB. Find Number of bits in tag
and Tag directory size
• Given:-
• Set size = 2
• Block size = Frame size = Line size = 256 bytes
• Main memory size = 128 KB

Number of Bits in Physical Address
bytes
• Number of Bits in Block Offset
bytes

Number of Lines in Cache-
• Total number of lines in cache = Cache size / Line size = 16
KB / 256 bytes
• = 214
bytes / 28
bytes = 64 lines
• Thus, Number of lines in cache = 64 lines
• Number of Sets in Cache-
Total number of sets in cache = Total number of lines in cache/Set size
= 64 / 2 = 32 sets = 25
sets
• Thus, Number of bits in set number = 5 bits

= Number of bits in physical address – (Number of
bits in set number + Number of bits in block offset)
= 17 bits – (5 bits + 8 bits) = 17 bits – 13 bits = 4 bits

= Number of tags x Tag size
= Number of lines in cache x Number of bits in tag
= 64 x 4 bits = 256 bits = 32 bytes

block size 1 KB. There are 7 bits in the tag. Find Size of main memory
and Tag directory size.
• Size of main memory – 8 MB
• Tag directory size – 3584 bytes

Replacement in Cache Mapping
• Direct Mapping
– In direct mapping, There is no need of any
replacement algorithm.
– This is because a main memory block can map
only to a particular line of the cache.
– Thus, the new incoming block will always replace
the existing block (if any) in that particular line.

• Fully Associative Mapping
– A replacement algorithm is required.
– Replacement algorithm suggests the block to be
replaced if all the cache lines are occupied.
– Thus, replacement algorithm like FCFS Algorithm,
LRU Algorithm etc is employed.

• Set Associative Mapping
– Set associative mapping is a combination of direct
mapping and fully associative mapping.
– It uses fully associative mapping within each set.
– Thus, set associative mapping requires a
replacement algorithm.

• Consider a direct mapped cache with 8 cache blocks (0-7). If the memory
block requests are in the order-
3, 5, 2, 8, 0, 6, 3, 9, 16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82, 17, 24
Which of the following memory blocks will be in the cache at the end of
the sequence? Also, calculate the hit ratio and miss ratio.

Consider a direct mapped cache with 8 cache blocks (0-7). If the memory
3, 5, 2, 8, 0, 6, 3, 9, 16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82, 17, 24
Which of the following memory blocks will be in the cache at the end of the
sequence? Also, calculate the hit ratio and miss ratio.
Solution
• There are 8 blocks in cache memory numbered from 0 to 7.
• In direct mapping, a particular block of main memory is mapped to a
particular line of cache memory.
• The line number is given by-
• Cache line number = Block address modulo Number of lines in cache
• For the given sequence-
– Requests for memory blocks are generated one by one.
– The line number of the block is calculated using the above relation.
– Then, the block is placed in that particular line.
– If already there exists another block in that line, then it is replaced.

Hit ratio = 3 / 20
Miss ratio = 17 / 20

Consider a fully associative cache with 8 cache blocks (0-7). The memory
4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, 8, 3, 16, 25, 7
If LRU replacement policy is used, which cache block will have memory block
7? Also, calculate the hit ratio and miss ratio.
Solution
• There are 8 blocks in cache memory numbered from 0 to 7.
• In fully associative mapping, any block of main memory can be mapped to
any line of the cache that is freely available.
• If all the cache lines are already occupied, then a block is replaced in
accordance with the replacement policy.

Line-5 contains the block-7.
Hit ratio = 5 / 17
Miss ratio = 12 / 17
Consider a fully associative cache with 8 cache blocks (0-7). The memory
4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, 8, 3, 16, 25, 7
If LRU replacement policy is used, which cache block will have memory block
7? Also, calculate the hit ratio and miss ratio.

Cache Replacement
• Consider the cache has 4 blocks. For the memory references-
5, 12, 13, 17, 4, 12, 13, 17, 2, 13, 19, 13, 43, 61, 19
What is the hit ratio for the following cache replacement algorithms-
– FIFO
– LRU
– Direct mapping
– 2-way set associative mapping using LRU
• Solution
• Using FIFO as cache replacement algorithm, hit ratio = 5/15 = 1/3.
• Using LRU as cache replacement algorithm, hit ratio = 6/15 = 2/5.
• Using direct mapping as cache replacement algorithm, hit ratio =
1/15.
• Using 2-way set associative mapping as cache replacement
algorithm, hit ratio = 5/15 = 1/3

Cache Replacement
• Consider the cache has 4 blocks. For the memory
• references-
5, 12, 13, 17, 4, 12, 13, 17, 2, 13, 19, 13, 43, 61, 19
What is the hit ratio for the following
cache replacement algorithms-
– FIFO
5 - miss
12 –miss
13-miss
17- miss
4 – miss
12 – hit
13- hit
17 – hit
2 – miss
13 – hit
19 – miss
13 – miss
43 – miss
61 – miss
19 - hit
No of Hits = 5
Hit Ratio = 5 / 15

Cache Replacement
• references-
5, 12, 13, 17, 4, 12, 13, 17, 2, 13, 19, 13, 43, 61, 19
– LRU
5 - miss
12 –miss
13-miss
17- miss
4 – miss
12 – hit
13- hit
17 – hit
2 – miss
13 – hit
19 – miss
13 – hit
43 – miss
61 – miss
19 - hit
No of Hits = 6
Hit Ratio = 6 / 15

Cache Replacement
• references-
5, 12, 13, 17, 4, 12, 13, 17, 2, 13, 19, 13, 43, 61, 19
– Direct Mapping
5 - miss
12 –miss
13-miss
17- miss
4 – miss
12 – hit
13- hit
17 – hit
2 – miss
13 – hit
19 – miss
13 – hit
43 – miss
61 – miss
19 - hit
No of Hits = 6
Hit Ratio = 6 / 15
Cache Memory
Set 0
Line 0
Line 1
Set 1
Line 2
Line 3

Cache Replacement
• references-
5, 12, 13, 17, 4, 12, 13, 17, 2, 13, 19, 13, 43, 61, 19
– Direct Mapping
5 % 4 = 1 miss
12 % 4=0 miss
13% 4=1 miss
17% 4=1 miss
4 % 4=0 miss
12% 4 =0 miss
13% 4=1 miss
17% 4 =1 miss
2 % 4=2 miss
13 % 4=1 miss
19% 4=3 miss
13 % 4=1 hit
43 % 4=3 miss
61% 4=1 miss
19 % 4=3 miss
Cache memory Block =Block j of MM % Number of Cache Blocks
No of Hits = 1
Hit Ratio = 1 / 15

Cache Replacement
• references-
5, 12, 13, 17, 4, 12, 13, 17, 2, 13, 19, 13, 43, 61, 19
– 2-way set associative mapping using LRU
5 % 2 = 1 miss
12 % 2=0 miss
13% 2=1 miss
17% 2=1 miss
4 % 2=0 miss
12% 2 =0 hit
13% 2=1 hit
17% 2 =1 hit
2 % 2=0 miss
13 % 2=1 hit
19% 2=1 miss
13 % 2=1 hit
43 % 2=1 miss
61% 2=1 miss
19 % 2=1 miss
Cache memory Block =Block j of MM % Number of Sets
No of Hits = 5
Hit Ratio = 5 / 15

BCSE205L_Module 4 Computer Architecture Org.pptx

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