bec306c Computer Architecture and Organization

Computer
Organization and
Architecture
MODULE 1 - PART 2
SUBJECT CODE: 18EC35
SAVITA M
ASSISTANT PROFESSOR
DEPT. OF ECE
JIT

Machine Instructions and Programs
Numbers and It’s Representation
•Computers are built using logic circuits that operate on information represented
by two valued electrical signals i.e 0 & 1.
•The amount of information represented by such signals is called as bit (binary
digit).
•In computer system, we represent numbers as string of bits called binary
numbers.
•Consider an n-bit vector
B=bn−1
...b1
b0
where bi
=0 or 1 for 0≤i ≤n−1. This vector can represent an unsigned integer value
V(B) in the range 0 to 2n −1, where
V(B) = bn−1
× 2n−1
+···+b1
×21
+b0
×20

•We need to represent both positive
and negative numbers. Three systems
are used for representing such
numbers:
• Sign-and-magnitude
• 1’s-complement
• 2’s-complement
•In all three systems, the leftmost bit is
0 for positive numbers and 1 for
negative numbers.

•In the sign-and-magnitude system, negative values are represented by changing the most
signiﬁcant bit (b3 in the above figure) from 0 to 1 in the B vector of the corresponding positive
value.
•For example, +5 is represented by 0101, and−5 is represented by 1101.
•In 1’s – complement representation, negative values are obtained by complementing each bit
of the corresponding positive number.
•Thus, the representation for −3 is obtained by complementing each bit in the vector 0011 to
yield 1100.
•For n-bit numbers, this operation is equivalent to subtracting the number from 2n
−1.
•In the case of the 4-bit numbers, we subtract from 24
−1=15, or 1111 in binary.
•Finally, in the 2’s-complement system, forming the 2’s-complement of an n-bit number is
done by subtracting the number from 2n
.
•Hence, the 2’s-complement of a number is obtained by adding 1 to the 1’s-complement of
that number.

Addition of Positive Numbers
Figure: Addition of 1-bit numbers

Addition and Subtraction of Signed Numbers
•Let us apply the mod 16 addition technique to the
example of adding +7 (0111) to −3 (1101).
•To add these numbers, locate 0111 on the circle in
Figure b.
•Then move 1101 (13) steps in the clockwise
direction to arrive at 0100, which yields the correct
answer of +4.

•The rules governing addition and subtraction of n-bit signed numbers using the
2’scomplement representation system may be stated as follows:
1. To add two numbers, add their n-bit representations, ignoring the carry-out bit from the
most signiﬁcant bit (MSB) position. The sum will be the algebraically correct value in
2’s-complement representation if the actual result is in the range −2n−1
through +2n−1
−1.
2. To subtract two numbers X and Y, that is, to perform X −Y, form the 2’s-complement of Y,
then add it to X using the add rule. Again, the result will be the algebraically correct value
in 2’s-complement representation if the actual result is in the range −2n−1
through +2n−1
−1.

•In all of these 4-bit examples, the answers
fall within the representable range of −8
through +7. When answers do not fall
within the representable range, we say that
arithmetic overﬂow has occurred.
•The four addition operations (a) through (d)
in Figure above follow the rule 1, and the
six subtraction operations (e) through (j)
follow the rule 2.
•The subtraction operation requires forming
the 2’s-complement of the subtrahend (the
bottom value).

Sign Extension
•We often need to represent a value given in a certain number of bits by using a larger number
of bits. For a positive number, this is achieved by adding 0s to the left.
•For a negative number in 2’s-complement representation, the leftmost bit, which indicates the
sign of the number, is a 1.
•A longer number with the same value is obtained by replicating the sign bit to the left as many
times as needed.
•In summary, to represent a signed number in 2’s-complement form using a larger number of
bits, repeat the sign bit as many times as needed to the left. This operation is called sign
extension.

•It might seem that the 1’s-complement representation would be just as good as the
2’s-complement system.
•However, although complementation is easy, the result obtained after an addition
operation is not always correct.
•The carry-out, cn
, cannot be ignored. If cn
=0, the result obtained is correct. If cn
=1, then
a 1 must be added to the result to make it correct.
•The need for this correction operation means that addition and subtraction cannot be
implemented as conveniently in the 1’s-complement system as in the 2’s-complement
system.

Overflow in Integer Arithmetic
•When adding unsigned numbers, a carry-out of 1 from the most significant bit position
indicates that an overflow has occurred. However, this is not always true when adding signed
numbers.
•For example, using 2’s-complement representations for 4-bit signed numbers, if we add +7
and +4, the sum vector is 1011, which is the representation for −5, an incorrect result.
•In this case, the carry-out bit from the MSB position is 0.
•If we add −4 and −6, we get 0110=+6, also an incorrect result. In this case, the carry-out bit is
1.
•Overflow may occur only if both summands have the same sign. The addition of numbers with
different signs cannot cause overflow because the result is always within the representable
range.
•A way to detect overflow when adding two numbers in 2’s-complement representation is to
examine the signs of the two summands and the sign of the result. When both summands
have the same sign, an overflow has occurred when the sign of the sum is not the same as the
signs of the summands.

Memory Locations and Addresses
Figure: Memory Words
Modern computers have word
lengths that typically range
from 16 to 64 bits.

Figure: Examples of encoded information in a 32-bit word

•Accessing the memory to store or retrieve a single item of information, either a word or
a byte, requires distinct names or addresses for each location.
•It is customary to use numbers from 0 to 2k
−1, for some suitable value of k, as the
addresses of successive locations in the memory. Thus, the memory can have up to 2k
addressable locations. The 2k
addresses constitute the address space of the computer.
•For example, a 24-bit address generates an address space of 224
(16,777,216) locations.
This number is usually written as 16M (16 mega), where 1M is the number 220
(1,048,576). A 32-bit address creates an address space of 232
or 4G (4giga) locations,
where 1G is 230
.
Byte Addressability
•There are three basic information quantities: bit, byte, and word. A byte is always 8 bits,
but the word length typically ranges from 16 to 64 bits.
•Byte locations have addresses 0,1,2,....Thus, if the word length of the machine is 32 bits,
successive words are located at addresses 0,4,8,...,with each word consisting of four
bytes.

Big-Endian and Little-Endian Assignments
Figure: Byte and word addressing

Word Alignment
•The word locations have two types of addresses: aligned and unaligned.
•We say that the word locations have aligned addresses if they begin at a byte address that is
a multiple of the number of bytes in a word.
•For practical reasons associated with manipulating binary-coded addresses, the number of
bytes in a word is a power of 2.
•Hence, if the word length is 16 (2 bytes), aligned words begin at byte addresses 0, 2, 4,...,
and for a word length of 64 (23 bytes), aligned words begin at byte addresses 0, 8, 16,....
•There is no fundamental reason why words cannot begin at an arbitrary byte address.
•In that case, words are said to have unaligned addresses.

Memory Operations
•Two basic operations involving the memory are needed, namely,
1. Read (Load or Fetch) and
2. Write (or Store).
•The Load operation transfers a copy of the contents of a speciﬁc memory location to the
processor. The memory contents remain unchanged. To start a Load operation, the
processor sends the address of the desired location to the memory and requests that its
contents be read. The memory reads the data stored at that address and sends them to
the processor.
•The Store operation transfers an item of information from the processor to a speciﬁc
memory location, overwriting the former contents of that location. To initiate a Store
operation, the processor sends the address of the desired location to the memory,
together with the data to be written into that location. The memory then uses the address
and data to perform the write.

Instructions and Instruction Sequencing
A computer must have instructions capable of performing four types of operations:
• Data transfers between the memory and the processor registers
• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers
Register Transfer Notation
•We need to describe the transfer of information from one location in a computer to
another.
•Possible locations that may be involved in such transfers are memory locations, processor
registers, or registers in the I/O subsystem.
•Most of the time, we identify such locations symbolically with convenient names.
•For example, names that represent the addresses of memory locations may be LOC,
PLACE,A, orVAR2.

•Pre-deﬁned names for the processor registers maybe R0 or R5.
•Registers in the I/O subsystem maybe identiﬁed by names such as DATAIN or OUTSTATUS.
•To describe the transfer of information, the contents of any location are denoted by
placing square brackets around its name. Thus, the expression
R2←[LOC]
means that the contents of memory location LOC are transferred into processor register
R2.
•As another example, consider the operation that adds the contents of registers R2 and R3,
and places their sum into register R4. This action is indicated as
R4←[R2]+[R3]
•This type of notation is known as Register Transfer Notation (RTN).
•Note that the right hand side of an RTN expression always denotes a value, and the
left-hand side is the name of a location where the value is to be placed, overwriting the
old contents of that location.

Assembly-Language Notation
•We need another type of notation to represent machine instructions and programs.
•For this, we use assembly language. For example, a generic instruction that causes the
transfer described above, from memory location LOC to processor register R1, is speciﬁed
by the statement
Move LOC, R1
•The contents of LOC are unchanged by the execution of this instruction, but the old
contents of register R1 are overwritten.
•The second example of adding two numbers contained in processor registers R2 and R3
and placing their sum in R4 can be speciﬁed by the assembly-language statement
Add R2, R3, R4

Basic Instruction Types:
Operations using Memory Locations
•The fundamental capability in any computer is addition operation i.e C = A+B as given in
HLL.
•When the compiler compiles this statement, three variables A, B & C are assigned to
distinct locations in the memory.
•The above operation can be represented in RTN as C←[A]+[B]
Three Address Instruction
•The general format for any operation in general is
Operation source1,source2,destination
•For Example, Add A,B,C
A,B = source operands, C = destination operand

Two Address Instruction
•The general format for any operation in general is
Operation source , destination
•For example, Add A,B
Move B,C
where Add performs the operation B←[A]+[B] and Move copies the contents of
B to C.
•The above example replaces the contents of B. In order to avoid this we can use
Move B,C
Add A,C
•Here the contents of B are moved or copied to C.
•Then the contents of C are added with A and the sum is stored in C, leaving the
contents of B unchanged.

One Address Instruction
•One more alternative is to use a machine instruction that specify only one
memory operand.
•When a second operand is needed, as in case of Add instruction it is understood
implicitly to be in unique location.
•A processor register usually called accumulator maybe used for this purpose.
•Thus, the one address instruction is can be written as Add A
•Add the contents of memory location A to the contents of accumulator register
and place the sum back into the accumulator.
•For example, the operation C←[A]+[B] can be written using one address
instruction as
Load A
Add B
Store C

Operations using General Purpose Registers
•Most modern computers have number of general-purpose processor registers,
typically 8 to 32.
•Access to the data in these registers is much faster than to the data stored in
memory locations because the registers are inside the processor.
•In modern processors, the computations can be performed directly on data held
in the processor registers such as
Add Ri
, Rj
and Add Ri
, Rj
, Rk
where Rj
in the first instruction and Rk
in the second instruction respectively are
destination registers.

•To transfer data between different locations,
Move source,destination
is used which places a copy of contents of source into destination.
•The operation C = A+B task can be performed by the instruction sequence
Move A,Ri
Move B,Rj
Add Ri
,Rj
Move Rj
,C
•In processors where one operand may be in the memory but the other must be in
a register, an instruction sequence for the required task would be
Move A,Ri
Add B,Ri
Move Ri
,C

Speed of task:
•The speed with which a given task is carried out depends on
a) the time it takes to transfer instructions from memory into the processor and
b) time taken to access the operands referenced by these instructions.
•Transfers that involve memory are much slower than transfers within the
processor (registers).

Instruction Execution and Straight-Line Sequencing
Figure: A program for C←[A]+[B].

•We assume that the word length is 32 bits and the memory is byte-addressable.
•The three instructions of the program are in successive word locations, starting at
location i.
•Since each instruction is 4 bytes long, the second and third instructions are at addresses
i+4 and i+8.
Program Execution:
•The processor contains a register called the program counter (PC), which holds the
address of the next instruction to be executed.
•To begin executing a program, the address of its ﬁrst instruction (i in our example) must
be placed into the PC.
•Then, the processor control circuits use the information in the PC to fetch and execute
instructions, one at a time, in the order of increasing addresses. This is called straight-line
sequencing.
•During the execution of each instruction, the PC is incremented by 4 to point to the next
instruction.

•Thus, after the Move instruction at location i + 8 is executed, the PC contains the value i + 12, which is
the address of the first instruction of the next program segment.
•Executing a given instruction is a two-phase procedure: Instruction fetch and instruction execute.
•In the first phase, called instruction fetch, the instruction is fetched from the memory location whose
address is in the PC. This instruction is placed in the instruction register (IR) in the processor.
•At the start of the second phase, called instruction execute, the instruction in IR is examined to
determine which operation is to be performed. The specified operation is then performed by the
processor.
•This involves a small number of steps such as fetching operands from the memory or from processor
registers, performing an arithmetic or logic operation, and storing the result in the destination
location.
•At some point during this two-phase procedure, the contents of the PC are advanced to point to the
next instruction.
•When the execute phase of an instruction is completed, the PC contains the address of the next
instruction, and a new instruction fetch phase can begin.

Branching
Figure: A program
for adding n
numbers.

•Consider the task of adding a list of n numbers. The program outlined in the above Figure is a
generalization of the program in shown in previous figure.
•The addresses of the memory locations containing the n numbers are symbolically given as
NUM1, NUM2,...,NUMn, and a separate Add instruction is used to add each number to contents
of register R0.
•After all the numbers have been added, the result is placed in memory location SUM.
•Instead of using along list of Add instructions, as in the above Figure, it possible to place a single
Add instruction in program loop.
•The loop is a straight line sequence of instructions executed as many times as needed.
•It starts at location LOOP and ends at the instruction Branch>0.
•During each pass through this loop, the address of the next list entry is determined, and that
entry is fetched and added to R0.
•In order to create and control a program loop, assume that the number of entries in the list, n, is
stored in memory location N, as shown.

•Register R1 is used as a counter to determine the number of times the loop is executed.
•Hence, the contents of location N are loaded into register R1 at the beginning of the program.
•Then, within the body of the loop, the instruction
•Decrement R1 reduces the contents of R1 by 1 each time through the loop.
•Execution of the loop is repeated as long as the contents of R1 are greater than zero.
Branch Instructions:
•This type of instruction loads a new address into the program counter.
•As a result, the processor fetches and executes the instruction at this new address, called the
branch target, instead of the instruction at the location that follows the branch instruction in
sequential address order.
•A conditional branch instruction causes a branch only if a specified condition is satisfied. If
the condition is not satisfied, the PC is incremented in the normal way, and the next
instruction in sequential address order is fetched and executed.

Figure: Using a loop to
add n numbers.

•In the program in the above Figure, the instruction
Branch>0 LOOP
is a conditional branch instruction that causes a branch to location LOOP if the
result of immediately preceding instruction, which is the decremented value in
the register R1 is greater than zero.
•This means that the loop is repeated as long as there are entries in the list that
are yet to be added to R0.
•At the end of the nth pass through the loop, the Decrement instruction produces
a value of zero in R1, and, hence, branching does not occur.
•Instead, the Move instruction is fetched and executed. It moves the ﬁnal result
from R0 into memory location SUM.

Conditional Codes
•Condition code flags are used to record the required information in individual bits
in case of various operations used in conditional branch instructions.
•These flags are grouped together in a special processor register called condition
code register or status register.
•Individual condition code flags are set to 1 or clear to 0 depending on the outcome
of the operation performed.

bec306c Computer Architecture and Organization

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