Building a DRAM flip flop using capacitive storing element
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The document discusses various attempts at developing memory elements, highlighting the time constants associated with different designs. It specifically mentions the creation of a D latch and a negative edge-triggered D flip-flop, addressing issues related to undefined states. Overall, it outlines the evolution of these memory components and their increasing complexity.
Building a DRAM flip flop using capacitive storing element
- 2. What we know until know R S Qn+1 0 0 Qn 0 1 1 1 0 0 1 1 X Simplest Memory Element
- 3. Crown Jewel
- 4. First Attempt Time Constant = 1ms
- 5. Second Attempt - Buffer Time Constant = 2ms
- 6. Third Attempt – Buffer + Refresh Trickle Switch Trickle Switch
- 9. Undefined States at 0,0 0 0 1 1 1 0 0 0
- 10. Negative Edge Triggered D Flip-Flop