SlideShare a Scribd company logo

CASFPGA1.ppt

Download as PPT, PDF
A
AswiniSamantray2

This document provides a summary of an introduction to field programmable gate arrays (FPGAs) lecture. It begins with a brief history of digital design and programmable logic, including how FPGAs evolved from programmable logic arrays and complex programmable logic devices. It then covers basics of digital design principles like synchronous design and combinational vs sequential logic. The document outlines and describes the basic FPGA architecture including logic blocks, routing resources, and examples from Xilinx Virtex II Pro family. It concludes with an overview of the traditional HDL design flow process from behavioral simulation to synthesis, implementation, and downloading the design.

Engineering
1 of 29
Download to read offline
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Introduction to Field Programmable Gate Arrays Lecture 1/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May – 9 June 2007 Javier Serrano, CERN AB-CO-HT
Outline Historical introduction. Basics of digital design. FPGA structure. Traditional (HDL) design flow. Demo.
Outline Historical introduction. Basics of digital design. FPGA structure. Traditional (HDL) design flow. Demo.
Historical Introduction  In the beginning, digital design was done with the ’74 series of chips.  Some people would design their own chips based on Gate Arrays, which were nothing else than an array of NAND gates:
Historical Introduction  The first programmable chips were PLAs (Programmable Logic Arrays): two level structures of AND and OR gates with user programmable connections.  Programmable Array Logic devices were an improvement in structure and cost over PLAs. Today such devices are generically called Programmable Logic Devices (PLDs).
Historical introduction  A complex PLD (CPLD) is nothing else than a collection of multiple PLDs and an interconnection structure.  Compared to a CPLD, a Field Programmable Gate Array (FPGA) contains a much larger number of smaller individual blocks + large interconnection structure that dominates the entire chip.
Outline Historical introduction. Basics of digital design. FPGA structure. Traditional (HDL) design flow. Demo.
Basics of digital design  Unless you really know what you are doing, stick to synchronous design: sandwiching bunches of combinational logic in between flip flops.  Combinational logic: state of outputs depend on current state of inputs alone (forgetting about propagation delays for the time being). E.g. AND, OR, mux, decoder, adder...  D-type Flip flops propagate D to Q upon a rising edge in the clk input.  Synchronous design simplifies design analysis, which is good given today’s logic densities.
Don’t do this! Toggle flip-flops get triggered by glitches produced by different path lengths of counter bits.
Basics of (synchronous) Digital Design dataSelectC dataAC[31:0] dataBC[31:0] dataSelectCD1 dataACd1[31:0] DataOut_3[31:0] 0 1 DataOut[31:0] sum_1[31:0] + sum[31:0] DataOut[31:0] [31:0] DataInB[31:0] [31:0] DataInA[31:0] [31:0] DataSelect Clk Q[0] D[0] [31:0] Q[31:0] [31:0] D[31:0] [31:0] Q[31:0] [31:0] D[31:0] Q[0] D[0] [31:0] Q[31:0] [31:0] D[31:0] [31:0] [31:0] [31:0] [31:0] Q[31:0] [31:0] D[31:0] [31:0] [31:0] [31:0] [31:0] Q[31:0] [31:0] D[31:0] High clock rate: 144.9 MHz on a Xilinx Spartan IIE. Higher clock rate: 151.5 MHz on the same chip. dataSelectC dataAC[31:0] dataBC[31:0] sum[31:0] + DataOut_3[31:0] 0 1 DataOut[31:0] DataOut[31:0] [31:0] DataInB[31:0] [31:0] DataInA[31:0] [31:0] DataSelect Clk Q[0] D[0] [31:0] Q[31:0] [31:0] D[31:0] [31:0] Q[31:0] [31:0] D[31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] Q[31:0] [31:0] D[31:0] 6.90 ns 6.60 ns Illustrating the latency/throughput tradeoff
Outline Historical introduction. Basics of digital design. FPGA structure. Traditional (HDL) design flow. Demo.
Basic FPGA architecture
The logic block: a summary view Example: using a LUT as a full adder.
A practical example: Xilinx Virtex II Pro family (used in the lab) Overview Configurable Logic Block (CLB) Embedded PowerPC Digitally Controlled Impedance (DCI)
A practical example: Xilinx Virtex II Pro family Slice Detail of half-slice
A practical example: Xilinx Virtex II Pro family Routing resources
FPGA state of the art  In addition to logic gates and routing, in a modern FPGA you can find:  Embedded processors (soft or hard).  Multi-Gb/s transceivers with equalization and hard IP for serial standards as PCI Express and Gbit Ethernet.  Lots of embedded MAC units, with enough bits to implement single precision floating point arithmetic efficiently.  Lots of dual-port RAM.  Sophisticated clock management through DLLs and PLLs.  System monitoring infrastructure including ADCs.  On-substrate decoupling capacitors to ease PCB design.  Digitally Controlled Impedance to eliminate on-board termination resistors.
Embedded processors
Why use embedded processors? Customization: take only the peripherals you need and replicate them as many times as needed. Create your own custom peripherals. Strike optimum balance in system partitioning.
Serial signaling  Avoids clock/data skew by using embedded clock.  Reduces EMI and power consumption.  Simplifies PCB routing.
Clock management
Outline Historical introduction. Basics of digital design. FPGA structure. Traditional (HDL) design flow. Demo.
Traditional design flow 1/3 HDL Synthesis Implementation Download HDL Implement your design using VHDL or Verilog Functional Simulation Timing Simulation In-Circuit Verification Behavioral Simulation
Traditional design flow 2/3 Behavioral Simulation HDL Synthesis Implementation Download HDL Synthesize the design to create an FPGA netlist Functional Simulation Timing Simulation In-Circuit Verification
Traditional design flow 3/3 Behavioral Simulation HDL Synthesis Implementation Download HDL Translate, place and route, and generate a bitstream to download in the FPGA Functional Simulation Timing Simulation In-Circuit Verification
VHDL 101 Both VHDL code segments produce exactly the same hardware.
VHDL 101: hierarchy
Outline Historical introduction. Basics of digital design. FPGA structure. Traditional (HDL) design flow. Demo.
Demo Now, let’s see how you go from design idea to hardware, using the traditional flow. Many thanks to Jeff Weintraub (Xilinx University Program), Bob Stewart (University of Strathclyde) and Silica for some of the slides.

More Related Content

PPT
Short.course.introduction.to.vhdl for beginners
Ravi Sony
 
PPTX
SoC FPGA Technology
Siraj Muhammad
 
PPTX
UNIT 5 FPGA DESIGN r16.pptx UNIT 5 FPGA DESIGN r16.pptx
Eswar610868
 
DOCX
Fpg as 11 body
Rameez Raja
 
PDF
8d545d46b1785a31eaab12d116e10ba41d996928Lecture%202%20and%203%20pdf (1).pdf
yatinsingh34
 
PPTX
Using FPGA in Embedded Devices
GlobalLogic Ukraine
 
DOCX
Fpga lecture
Zhwan Rashid
 
PPT
ASIC VS FPGA.ppt
gopakumar885691
 
Short.course.introduction.to.vhdl for beginners
Ravi Sony
 
SoC FPGA Technology
Siraj Muhammad
 
UNIT 5 FPGA DESIGN r16.pptx UNIT 5 FPGA DESIGN r16.pptx
Eswar610868
 
Fpg as 11 body
Rameez Raja
 
8d545d46b1785a31eaab12d116e10ba41d996928Lecture%202%20and%203%20pdf (1).pdf
yatinsingh34
 
Using FPGA in Embedded Devices
GlobalLogic Ukraine
 
Fpga lecture
Zhwan Rashid
 
ASIC VS FPGA.ppt
gopakumar885691
 

Similar to CASFPGA1.ppt (20)

PPT
Fpga &;cpld(by alok singh)
Alok Singh
 
PPTX
Introduction to EDA Tools
venkatasuman1983
 
PDF
1. FPGA architectures.pdf
TesfuFiseha1
 
PPTX
Lecture 16 RC Architecture Types & FPGA Interns Lecturer.pptx
wafawafa52
 
PDF
J044084349
IJERA Editor
 
PPTX
Seminar on field programmable gate array
Saransh Choudhary
 
PDF
Fpga & VHDL
Francesco De Canio
 
PPT
Short.course.introduction.to.vhdl
Ravi Sony
 
PPTX
Fpga architectures and applications
Sudhanshu Janwadkar
 
PDF
FPGA Architecture and application
ADARSHJKALATHIL
 
PDF
Project report of 2016 Trainee_final
Akash Chowdhury
 
PPTX
Lecture Slide (1).pptx
BilalMumtaz9
 
PDF
Basic Design Flow for Field Programmable Gate Arrays
Usha Mehta
 
PDF
digitaldesign-s20-lecture3b-fpga-afterlecture.pdf
Duy-Hieu Bui
 
PDF
Summer training vhdl
Arshit Rai
 
PPTX
Summer training vhdl
Arshit Rai
 
PPTX
Introduction to CPLD: Field Programmable Gate Array
ENAULHAQSHAIK
 
PPTX
Design options for digital systems
dennis gookyi
 
PDF
FPGA Based VLSI Design
Debargha Chakraborty
 
PPTX
module nenddhd dhdbdh dehrbdbddnd d 1.pptx
kashinathvpillai51
 
Fpga &;cpld(by alok singh)
Alok Singh
 
Introduction to EDA Tools
venkatasuman1983
 
1. FPGA architectures.pdf
TesfuFiseha1
 
Lecture 16 RC Architecture Types & FPGA Interns Lecturer.pptx
wafawafa52
 
J044084349
IJERA Editor
 
Seminar on field programmable gate array
Saransh Choudhary
 
Fpga & VHDL
Francesco De Canio
 
Short.course.introduction.to.vhdl
Ravi Sony
 
Fpga architectures and applications
Sudhanshu Janwadkar
 
FPGA Architecture and application
ADARSHJKALATHIL
 
Project report of 2016 Trainee_final
Akash Chowdhury
 
Lecture Slide (1).pptx
BilalMumtaz9
 
Basic Design Flow for Field Programmable Gate Arrays
Usha Mehta
 
digitaldesign-s20-lecture3b-fpga-afterlecture.pdf
Duy-Hieu Bui
 
Summer training vhdl
Arshit Rai
 
Summer training vhdl
Arshit Rai
 
Introduction to CPLD: Field Programmable Gate Array
ENAULHAQSHAIK
 
Design options for digital systems
dennis gookyi
 
FPGA Based VLSI Design
Debargha Chakraborty
 
module nenddhd dhdbdh dehrbdbddnd d 1.pptx
kashinathvpillai51
 
Ad

Recently uploaded (20)

PPTX
Lecture Notes Electrical Wiring System Components
eedgecbhojpur
 
PDF
Operating System & Kernel Study Guide-1 - converted.pdf
mranoninvisib16
 
PPTX
OOP with Java - Java Introduction (Basics)
Rashmi T V
 
PPTX
Internet of Things (IOT) - A guide to understanding
Davies Chacko
 
PDF
BMEC211 - INTRODUCTION TO MECHATRONICS-1.pdf
ryankakungu
 
PPTX
Recipes for Real Time Voice AI WebRTC, SLMs and Open Source Software.pptx
Alberto González Trastoy
 
PPTX
CH1 Production IntroductoryConcepts.pptx
RacemMellouli1
 
DOCX
573137875-Attendance-Management-System-original
AYUSHMANAV
 
PDF
Well-logging-methods_new................
ZafriFarid
 
PPTX
Geodesy 1.pptx...............................................
abhi1361yadav
 
PPTX
bas. eng. economics group 4 presentation 1.pptx
kiribakimoses1993
 
PPT
Project quality management in manufacturing
BarMusaTetik
 
PDF
Mitigating Risks through Effective Management for Enhancing Organizational Pe...
IJAEMSJORNAL
 
PDF
July 2025 - Top 10 Read Articles in International Journal of Software Enginee...
sebastianku31
 
DOCX
ASol_English-Language-Literature-Set-1-27-02-2023-converted.docx
AYUSHMANAV
 
PPTX
KTU 2019 -S7-MCN 401 MODULE 2-VINAY.pptx
VinayB68
 
PPTX
CYBER-CRIMES AND SECURITY A guide to understanding
Davies Chacko
 
PPTX
IOT PPTs Week 10 Lecture Material.pptx of NPTEL Smart Cities contd
ssusera400e8
 
PPTX
Infosys Presentation by1.Riyan Bagwan 2.Samadhan Naiknavare 3.Gaurav Shinde 4...
bapushinde7218
 
PPTX
Construction Project Organization Group 2.pptx
vj5agdales
 
Lecture Notes Electrical Wiring System Components
eedgecbhojpur
 
Operating System & Kernel Study Guide-1 - converted.pdf
mranoninvisib16
 
OOP with Java - Java Introduction (Basics)
Rashmi T V
 
Internet of Things (IOT) - A guide to understanding
Davies Chacko
 
BMEC211 - INTRODUCTION TO MECHATRONICS-1.pdf
ryankakungu
 
Recipes for Real Time Voice AI WebRTC, SLMs and Open Source Software.pptx
Alberto González Trastoy
 
CH1 Production IntroductoryConcepts.pptx
RacemMellouli1
 
573137875-Attendance-Management-System-original
AYUSHMANAV
 
Well-logging-methods_new................
ZafriFarid
 
Geodesy 1.pptx...............................................
abhi1361yadav
 
bas. eng. economics group 4 presentation 1.pptx
kiribakimoses1993
 
Project quality management in manufacturing
BarMusaTetik
 
Mitigating Risks through Effective Management for Enhancing Organizational Pe...
IJAEMSJORNAL
 
July 2025 - Top 10 Read Articles in International Journal of Software Enginee...
sebastianku31
 
ASol_English-Language-Literature-Set-1-27-02-2023-converted.docx
AYUSHMANAV
 
KTU 2019 -S7-MCN 401 MODULE 2-VINAY.pptx
VinayB68
 
CYBER-CRIMES AND SECURITY A guide to understanding
Davies Chacko
 
IOT PPTs Week 10 Lecture Material.pptx of NPTEL Smart Cities contd
ssusera400e8
 
Infosys Presentation by1.Riyan Bagwan 2.Samadhan Naiknavare 3.Gaurav Shinde 4...
bapushinde7218
 
Construction Project Organization Group 2.pptx
vj5agdales
 
Ad

CASFPGA1.ppt

  • 1. Introduction to Field Programmable Gate Arrays Lecture 1/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May – 9 June 2007 Javier Serrano, CERN AB-CO-HT
  • 2. Outline Historical introduction. Basics of digital design. FPGA structure. Traditional (HDL) design flow. Demo.
  • 3. Outline Historical introduction. Basics of digital design. FPGA structure. Traditional (HDL) design flow. Demo.
  • 4. Historical Introduction  In the beginning, digital design was done with the ’74 series of chips.  Some people would design their own chips based on Gate Arrays, which were nothing else than an array of NAND gates:
  • 5. Historical Introduction  The first programmable chips were PLAs (Programmable Logic Arrays): two level structures of AND and OR gates with user programmable connections.  Programmable Array Logic devices were an improvement in structure and cost over PLAs. Today such devices are generically called Programmable Logic Devices (PLDs).
  • 6. Historical introduction  A complex PLD (CPLD) is nothing else than a collection of multiple PLDs and an interconnection structure.  Compared to a CPLD, a Field Programmable Gate Array (FPGA) contains a much larger number of smaller individual blocks + large interconnection structure that dominates the entire chip.
  • 7. Outline Historical introduction. Basics of digital design. FPGA structure. Traditional (HDL) design flow. Demo.
  • 8. Basics of digital design  Unless you really know what you are doing, stick to synchronous design: sandwiching bunches of combinational logic in between flip flops.  Combinational logic: state of outputs depend on current state of inputs alone (forgetting about propagation delays for the time being). E.g. AND, OR, mux, decoder, adder...  D-type Flip flops propagate D to Q upon a rising edge in the clk input.  Synchronous design simplifies design analysis, which is good given today’s logic densities.
  • 9. Don’t do this! Toggle flip-flops get triggered by glitches produced by different path lengths of counter bits.
  • 10. Basics of (synchronous) Digital Design dataSelectC dataAC[31:0] dataBC[31:0] dataSelectCD1 dataACd1[31:0] DataOut_3[31:0] 0 1 DataOut[31:0] sum_1[31:0] + sum[31:0] DataOut[31:0] [31:0] DataInB[31:0] [31:0] DataInA[31:0] [31:0] DataSelect Clk Q[0] D[0] [31:0] Q[31:0] [31:0] D[31:0] [31:0] Q[31:0] [31:0] D[31:0] Q[0] D[0] [31:0] Q[31:0] [31:0] D[31:0] [31:0] [31:0] [31:0] [31:0] Q[31:0] [31:0] D[31:0] [31:0] [31:0] [31:0] [31:0] Q[31:0] [31:0] D[31:0] High clock rate: 144.9 MHz on a Xilinx Spartan IIE. Higher clock rate: 151.5 MHz on the same chip. dataSelectC dataAC[31:0] dataBC[31:0] sum[31:0] + DataOut_3[31:0] 0 1 DataOut[31:0] DataOut[31:0] [31:0] DataInB[31:0] [31:0] DataInA[31:0] [31:0] DataSelect Clk Q[0] D[0] [31:0] Q[31:0] [31:0] D[31:0] [31:0] Q[31:0] [31:0] D[31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] Q[31:0] [31:0] D[31:0] 6.90 ns 6.60 ns Illustrating the latency/throughput tradeoff
  • 11. Outline Historical introduction. Basics of digital design. FPGA structure. Traditional (HDL) design flow. Demo.
  • 13. The logic block: a summary view Example: using a LUT as a full adder.
  • 14. A practical example: Xilinx Virtex II Pro family (used in the lab) Overview Configurable Logic Block (CLB) Embedded PowerPC Digitally Controlled Impedance (DCI)
  • 15. A practical example: Xilinx Virtex II Pro family Slice Detail of half-slice
  • 16. A practical example: Xilinx Virtex II Pro family Routing resources
  • 17. FPGA state of the art  In addition to logic gates and routing, in a modern FPGA you can find:  Embedded processors (soft or hard).  Multi-Gb/s transceivers with equalization and hard IP for serial standards as PCI Express and Gbit Ethernet.  Lots of embedded MAC units, with enough bits to implement single precision floating point arithmetic efficiently.  Lots of dual-port RAM.  Sophisticated clock management through DLLs and PLLs.  System monitoring infrastructure including ADCs.  On-substrate decoupling capacitors to ease PCB design.  Digitally Controlled Impedance to eliminate on-board termination resistors.
  • 19. Why use embedded processors? Customization: take only the peripherals you need and replicate them as many times as needed. Create your own custom peripherals. Strike optimum balance in system partitioning.
  • 20. Serial signaling  Avoids clock/data skew by using embedded clock.  Reduces EMI and power consumption.  Simplifies PCB routing.
  • 22. Outline Historical introduction. Basics of digital design. FPGA structure. Traditional (HDL) design flow. Demo.
  • 23. Traditional design flow 1/3 HDL Synthesis Implementation Download HDL Implement your design using VHDL or Verilog Functional Simulation Timing Simulation In-Circuit Verification Behavioral Simulation
  • 24. Traditional design flow 2/3 Behavioral Simulation HDL Synthesis Implementation Download HDL Synthesize the design to create an FPGA netlist Functional Simulation Timing Simulation In-Circuit Verification
  • 25. Traditional design flow 3/3 Behavioral Simulation HDL Synthesis Implementation Download HDL Translate, place and route, and generate a bitstream to download in the FPGA Functional Simulation Timing Simulation In-Circuit Verification
  • 26. VHDL 101 Both VHDL code segments produce exactly the same hardware.
  • 28. Outline Historical introduction. Basics of digital design. FPGA structure. Traditional (HDL) design flow. Demo.
  • 29. Demo Now, let’s see how you go from design idea to hardware, using the traditional flow. Many thanks to Jeff Weintraub (Xilinx University Program), Bob Stewart (University of Strathclyde) and Silica for some of the slides.