ch16_1 Memory System Design .pdf

Memory System Design
Chapter 16
S. Dandamudi

2003
To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.
 S. Dandamudi Chapter 16: Page 2
Outline
• Introduction
• A simple memory block
∗ Memory design with D flip
flops
∗ Problems with the design
• Techniques to connect to a
bus
∗ Using multiplexers
∗ Using open collector
outputs
∗ Using tri-state buffers
• Building a memory block
• Building larger memories
• Mapping memory
∗ Full mapping
∗ Partial mapping
• Alignment of data
• Interleaved memories
∗ Synchronized access
organization
∗ Independent access
organization
∗ Number of banks

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Introduction
• To store a single bit, we can use
∗ Flip flops or latches
• Larger memories can be built by
∗ Using a 2D array of these 1-bit devices
» “Horizontal” expansion to increase word size
» “Vertical” expansion to increase number of words
• Dynamic RAMs use a tiny capacitor to store a bit
• Design concepts are mostly independent of the
actual technique used to store a bit of data

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Memory Design with D Flip Flops
• An example
∗ 4X3 memory design
∗ Uses 12 D flip flops in a 2D array
∗ Uses a 2-to-4 decoder to select a row (i.e. a word)
∗ Multiplexers are used to gate the appropriate output
∗ A single WRITE (WR) is used to serve as a write and
read signal
– zero is used to indicate write operation
– one is used for read operation
∗ Two address lines are needed to select one of four
words of 3 bits each

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Memory Design with D Flip Flops (cont’d)

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Memory Design with D Flip Flops (cont’d)
• Problems with the design
∗ Requires separate data in
and out lines
» Cannot use the
bidirectional data bus
∗ Cannot use this design as a
building block to design
larger memories
» To do this, we need a chip
select input
• We need techniques to
connect multiple devices
to a bus

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Techniques to Connect to a Bus
• Three techniques
∗ Use multiplexers
» Example
– We used multiplexers in the last memory design
» We cannot use MUXs to support bidirectional buses
∗ Use open collector outputs
» Special devices that facilitate connection of several outputs
together
∗ Use tri-state buffers
» Most commonly used devices

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Techniques to Connect to a Bus (cont’d)
Open collector technique

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Open collector register chip

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Tri-State Buffers

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Two example tri-state buffer chips

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8-bit tri-state register

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Building a Memory Block
A 4 X 3 memory design
using D flip-flops

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Building a Memory Block (cont’d)
Block diagram representation of a 4x3 memory

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Building Larger Memories
2 X 16 memory module using 74373 chips

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Designing Larger Memories
• Issues involved
∗ Selection of a memory chip
» Example: To design a 64M X 32 memory, we could use
– Eight 64M X 4 in 1 X 8 array (i.e., single row)
– Eight 32M X 8 in 2 X 4 array
– Eight 16M X 16 in 4 X 2 array
• Designing M X N memory with D X W chips
∗ Number of chips = M.N/D.W
∗ Number of rows = M/D
∗ Number of columns = N/W

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Designing Larger Memories (cont’d)
64M X 32
memory using
16M X 16 chips

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Designing Larger Memories (cont’d)
• Design is simplified by partitioning the address
lines (M X N memory with D X W memory chips)
∗ Z bits are not connected (Z = log2(N/8))
∗ Y bits are connected to all chips (Y = log2D)
∗ X remaining bits are used to map the memory block
» Used to generate chip selects

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Memory Mapping
Full mapping

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Memory Mapping (cont’d)
Partial mapping

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Alignment of Data

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Alignment of Data (cont’d)
• Alignment
∗ 2-byte data: Even address
» Rightmost address bit should be zero
∗ 4-byte data: Address that is multiple of 4
» Rightmost 2 bits should be zero
∗ 8-byte data: Address that is multiple of 8
» Rightmost 3 bits should be zero
∗ Soft alignment
» Can handle aligned as well as unaligned data
∗ Hard alignment
» Handles only aligned data (enforces alignment)

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Interleaved Memory
• In our memory designs
∗ Block of contiguous memory addresses is mapped to a module
» One advantage
– Incremental expansion
» Disadvantage
– Successive accesses take more time
4Not possible to hide memory latency
• Interleaved memories
∗ Improve access performance
» Allow overlapped memory access
» Use multiple banks and access all banks simultaneously
– Addresses are spread over banks
4Not mapped to a single memory module

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Interleaved Memory (cont’d)
• The n-bit address is divided into two r and m bits:
n = r + m
• Normal memory
∗ Higher order r bits identify a module
∗ Lower order m bits identify a location in the module
» Called high-order interleaving
• Interleaved memory
∗ Lower order r bits identify a module
∗ Higher order m bits identify a location in the module
» Called low-order interleaving
∗ Memory modules are referred to as memory banks

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• Two possible implementations
∗ Synchronized access organization
» Upper m bits are presented to all banks simultaneously
» Data are latched into output registers (MDR)
» During the data transfer, next m bits are presented to initiate
the next cycle
∗ Independent access organization
» Synchronized design does not efficiently support access to
non-sequential access patterns
» Allows pipelined access even for arbitrary addresses
» Each memory bank has a memory address register (MAR)
– No need for MDR

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Synchronized access organization

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Interleaved
memory allows
pipelined access
to memory

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Independent access organization

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• Number of banks
∗ M = memory access time in cycles
∗ To provide one word per cycle
» Number of banks ≥ M
• Drawbacks of interleaved memory
∗ Involves complex design
» Example: Need MDR or MAR
∗ Reduced fault-tolerance
» One bank failure leads to failure of the whole memory
∗ Cannot be expanded incrementally
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ch16_1 Memory System Design .pdf

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