Chapter 6

Er. Nawaraj Bhandari
Topic 6
Computer Arithmetic
Computer
Architecture

Arithmetic & Logic Unit
 Does the calculations
 Everything else in the computer is there to service this unit
 Handles integers
 May handle floating point (real) numbers
 May be separate Floating-point unit (maths co-processor)
 May be on chip separate FPU (486DX +)

Arithmetic & Logic Unit
 Operands for arithmetic and logic operations are presented to the ALU
in registers, and the results of an operation are stored in registers.
 These registers are temporary storage locations within the processor
that are connected by signal paths to the ALU
 The ALU may also set flags as the result of an operation. For example,
an overflow flag is set to 1 if the result of a computation exceeds the
length of the register into which it is to be stored
 The flag values are also stored in registers within the processor. The
processor provides signals that control the operation of the ALU and
the movement of the data into and out of the ALU.

Integer Representation
 Only have 0 & 1 to represent everything
 Positive numbers stored in binary
 e.g. 41=00101001
 No minus sign
 No period
 Sign-Magnitude
 Two’s compliment

Sign-Magnitude
 Left most bit is sign bit
 0 means positive
 1 means negative
 +18 = 00010010
 -18 = 10010010
 Problems
 Need to consider both sign and magnitude in arithmetic
 Two representations of zero (+0 and -0)
+ 010 = 00000000
- 010 = 10000000 (sign magnitude)

Two’s Compliment
 Like sign magnitude, twos complement representation uses the most
significant bit as a sign bit, making it easy to test whether an integer is
positive or negative.
 It differs from the use of the sign-magnitude representation in the way
that the other bits are interpreted

Two’s Compliment
 +3 = 00000011
 +2 = 00000010
 +1 = 00000001
 +0 = 00000000
 -1 = 11111111
 -2 = 11111110
 -3 = 11111101

Benefits
 One representation of zero
 Arithmetic works easily
 Negating is fairly easy
 3 = 00000011
 Boolean complement gives 11111100
 Add 1 to LSB 11111101

Negation Special Case 1
 0 = 00000000
 Bitwise not 11111111
 Add 1 to LSB +1
 Result 1 00000000
 Overflow is ignored, so:
 - 0 = 0 

Negation Special Case 2
 -128 = 10000000
 bitwise not 01111111
 Add 1 to LSB +1
 Result 10000000
 So:
 -(-128) = -128 X
 Monitor MSB (sign bit)
 It should change during negation

Addition and Subtraction
 Normal binary addition
 Monitor sign bit for overflow
 Take twos compliment of substahend and add to minuend
 i.e. a - b = a + (-b)
 So we only need addition and complement circuits

Hardware for Addition and Subtraction

Floating Point
 +/- .significand x 2exponent
 Misnomer
 Point is actually fixed between sign bit and body of
mantissa
 Exponent indicates place value (point position)
Signbit
Biased
Exponent
Significand or Mantissa

Signs for Floating Point
 Mantissa is stored in 2s compliment
 Exponent is in excess or biased notation
 e.g. Excess (bias) 128 means
 8 bit exponent field
 Pure value range 0-255
 Subtract 128 to get correct value
 Range -128 to +127

Normalization
 FP numbers are usually normalized
 i.e. exponent is adjusted so that leading bit (MSB) of mantissa is 1
 Since it is always 1 there is no need to store it
 (c.f. Scientific notation where numbers are normalized to give a single
digit before the decimal point
 e.g. 3.123 x 103)

FP Ranges
 For a 32 bit number
 8 bit exponent
 +/- 2256  1.5 x 1077
 Accuracy
 The effect of changing lsb of mantissa
 23 bit mantissa 2-23  1.2 x 10-7
 About 6 decimal places

Density of Floating Point Numbers

IEEE 754
 Standard for floating point storage
 32 and 64 bit standards
 8 and 11 bit exponent respectively
 Extended formats (both mantissa and exponent) for intermediate
results

FP Arithmetic +/-
 Check for zeros
 Align significands (adjusting exponents)
 Add or subtract significands
 Normalize result

FP Arithmetic x/
 Check for zero
 Add/subtract exponents
 Multiply/divide significands (watch sign)
 Normalize
 Round
 All intermediate results should be in double length storage

Required Reading
 Stallings Chapter 9
 IEEE 754 on IEEE Web site

Chapter 6

More Related Content

What's hot (20)

Similar to Chapter 6 (20)

More from Er. Nawaraj Bhandari (20)

Recently uploaded (20)

Chapter 6