Chitra_BE_ECE_2015_74AGG
- 1. Chaitra N. Email Id: chaitranaganur@gmail.com Mobile: 91-9620356255 CAREER OBJECTIVE To become a responsible engineer and participate in the development of technology with challenging assignments thereby improving my existing skills and acquiring new skills and to associate with a company, that is technology driven and where my talent and contributions are valued and encouraged. SKILL SET Tools : Basic Knowledge on Keil, cadence virtuoso Operating Systems : Basic Knowledge on RTOS, Windows XP and Windows 7. Programming Skills : Basic Knowledge on C, C++, Verilog Assembly Languages : Basic Knowledge on Microprocessors 8086 and Microcontroller 8051 Others : Basic Knowledge on DSP, Embedded Systems, VLSI ACADEMIC QUALIFICATION 2015 B.E in Electronics & Communication from HIT, Nidasoshi. (74) 2011 Pre-University from G.H College, Haveri. (74.16) 2009 SSLC from HSH School, Haveri. (79.52) TECHNICAL ACTIVITIES Participated in Paper Presentation praxis2k14 National Level Tech Fest held at K.L.E college of Engineering & Technology, Chikkodi. Participated in Paper presentation National level Technical Competition HIT QUEST-2014 held at HIT, Nidasoshi CERTIFICATION Completed following Software Testing courses in Q-Spider Banglore: Automation testing - Black box and White box testing Manual Testing Mobile Testing Selenium Testing using Java Scripting Currently doing JAVA course in Q-Spider Banglore center. ACADEMIC PROJECT DETAILS Project Title : Implementation of 16-point 4-parallel radix-2^2 FFT architecture using Verilog Tool : cadence virtuoso Programming: Verilog Project Brief:
- 2. This proposed work presents the 16-point 4-parallel radix-2^2 feed forward FFT architecture. In the 16-point radix-2^2 DIF FFT we use 16 paths for sending 16 samples, so it needs more number of multipliers and adders. To overcome from this problem we proposed to work on 4-parallel radix-2^2 feed forward architectures. In this proposed work the 16 samples are sending in 4-parallel paths, hence reducing number of multipliers and adders for calculation. The tool used for the proposed work is cadence virtuoso, and the programming language used to write code for proposed work is Verilog. The proposed designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed 4-parallel radix-2^2 feed forward architecture for the computation of the 16-point DIF FFT require few hardware resources than parallel feedback ones, when several samples in parallel must be processed. PERSONAL DETAILS Name : Chaitra N Nationality : Indian Gender : Female Date of Birth : 13th Sept 1993 Languages known : English, Hindi, Kannada Marital Status : Single (Chaitra N)