Clamping circuits|Dept of ECE| ANITS
- 1. ANIL NEERUKONDA INSTITUTE OF TECHNOLOGY & SCIENCES(A) Department of Electronics and Communication Engineering ECE 216 Electronic circuits and Analysis-I ➢Academic year : 2020-21 ➢Class & Section : 2/4 ECE-C ➢Name of the Faculty : Mr.D.Anil Prasad ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 2. ANIL NEERUKONDA INSTITUTE OF TECHNOLOGY & SCIENCES(A) Department of Electronics and Communication Engineering Non Linear Wave shaping circuits Clamping circuits ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 3. Clamping circuits • The circuit which is used to add DC level as per requirement in the output of the AC signal. • The clamper circuit is also called as DC restorer or DC inserter ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 4. Clamping circuits Types of Clamping circuits: 1. Positive clamper 2. Negative clamper ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 5. -Vm Positive Clamper circuit Positive clamper t0 Vm V0 t0 Vm 2 Vm Vi V0=Vi +Vm ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 6. Negative Clamper circuit Negative clamper t0 Vm -Vm V0 t0 Vm 2 Vm Vi V0=Vi -Vm -Vm -2 Vm ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 7. Analysis of Positive clamper circuit using ideal diode model ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 8. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL VC=0 - + - V0Vi VC(0 -)=0=VC(0+) Capacitor is initially uncharged + - Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 9. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL VC=0 - + - V0Vi 0<t<T/4 VC(0 -)=0=VC(0+) Capacitor is initially uncharged ANIL PRASAD DADI/DEPT OF ECE/ANITS Diode is reverse biased
- 10. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL C - + - V0Vi 𝑉𝑐 𝑇 4 − = 𝑉𝑐 𝑇 4 + =0V τ=RthC=RLC RLC>>T, Time period of input signal ANIL PRASAD DADI/DEPT OF ECE/ANITS 0<t<T/4
- 11. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 0<t<T/4 RL VC=0 - + - V0Vi V0=Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 12. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/4<t<T/2 RL VC=0 - + - V0Vi + - Vi 𝑉𝑐 𝑇 4 − = 𝑉𝑐 𝑇 4 + =0V ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 13. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL VC=0 - + - V0Vi T/4<t<T/2 Diode is reverse biased ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 14. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL C - + - V0Vi 𝑉𝑐 𝑇 2 − = 𝑉𝑐 𝑇 2 + =0V τ=RthC=RLC RLC>>T, Time period of input signal ANIL PRASAD DADI/DEPT OF ECE/ANITS T/4<t<T/2
- 15. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/4<t<T/2 RL VC=0 - + - V0Vi V0=Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 16. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/2<t<3T/4 RL VC=0 - + - V0Vi + - Vi 𝑉𝑐 𝑇 2 − = 𝑉𝑐 𝑇 2 + =0V ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 17. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/2<t<3T/4 RL - + - V0Vi i VC +- τ=RthC=0 VC= -Vi 𝑉𝑐 3𝑇 4 − = 𝑉𝑐 3𝑇 4 + =+Vm ANIL PRASAD DADI/DEPT OF ECE/ANITS Diode is forward biased
- 18. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/2<t<3T/4 RL - + - V0Vi i VC +- V0=0 ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 19. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 3T/4<t<T RL - + - V0Vi VC +- 𝑉𝑐 3𝑇 4 − = 𝑉𝑐 3𝑇 4 + =+Vm V0=VD=VC+Vi VD =Vm+Vi + - VD ANIL PRASAD DADI/DEPT OF ECE/ANITS Let Vm=10V 10-9.9 10-9.8 ….
- 20. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi tT 3𝑇 4 3T/4<t<T RL - + - V0Vi Vm +- Diode is reverse biased V0=Vm+Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS 2Vm 𝑇 4 𝑇 2 T τ=RthC=RLC RLC>>T, Time period of input signal
- 21. Problem #1(Assume ideal diode) ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 22. Analysis of Negative clamper circuit using ideal diode model ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 23. Vi RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 0<t<T/4 VC(0 -)=0=VC(0+) Capacitor is initially uncharged + RL VC=0 - + - Vi + - ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 24. RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 0<t<T/4 VC(0 -)=0=VC(0+) Capacitor is initially uncharged + RL - + - Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Diode is forward biased -VC+ i
- 25. - RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 0<t<T/4 + RL VC - + - Vi i + τ=RthC=0 𝑉𝑐 𝑇 4 − = 𝑉𝑐 𝑇 4 + =+Vm VC= Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 26. - RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 0<t<T/4 + RL VC - + - Vi i +V0=0 ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 27. VD - RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/4<t<T/2 + RL VC - + - Vi +𝑉𝑐 𝑇 4 − = 𝑉𝑐 𝑇 4 + =+Vm VD= -VC+Vi + - V0 Let Vm=10V ANIL PRASAD DADI/DEPT OF ECE/ANITS -10+9.9 -10+9.8 …. VD= -Vm+Vi
- 28. - RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 T/4<t<T/2 + RL Vm - + - Vi + V0 V0= Vi - Vm ANIL PRASAD DADI/DEPT OF ECE/ANITS Diode is reverse biased 𝑇 4 τ=RthC=RLC RLC>>T, Time period of input signal
- 29. Problem #1(Assume ideal diode) ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 30. Analysis of Positive clamper circuit using diode equivalent resistance model ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 31. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL VC=0 - + - V0Vi VC(0 -)=0=VC(0+) Capacitor is initially uncharged + - Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 32. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL VC=0 - + - V0Vi 0<t<T/4 ANIL PRASAD DADI/DEPT OF ECE/ANITS Rr Diode is in Reverse bias
- 33. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL - + - V0Vi 0<t<T/4 ANIL PRASAD DADI/DEPT OF ECE/ANITS Rr 𝑉𝑐 𝑇 4 − = 𝑉𝑐 𝑇 4 + =0V τ=RthC=(Rr||RL)C RLC>>T, Time period of input signal τ=RLC
- 34. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 0<t<T/4 RL - + - V0Vi V0=Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Rr
- 35. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/4<t<T/2 RL - + - V0Vi + - Vi 𝑉𝑐 𝑇 4 − = 𝑉𝑐 𝑇 4 + =0V ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 36. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL - + - V0Vi T/4<t<T/2 ANIL PRASAD DADI/DEPT OF ECE/ANITS Rr Diode is in Reverse bias
- 37. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL - + - V0Vi T/4<t<T/2 ANIL PRASAD DADI/DEPT OF ECE/ANITS Rr 𝑉𝑐 𝑇 2 − = 𝑉𝑐 𝑇 2 + =0V RLC>>T, Time period of input signal τ=RthC=(Rr||RL)C τ=RLC
- 38. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/4<t<T/2 RL - + - V0Vi V0=Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Rr
- 39. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/2<t<3T/4 RL VC=0 - + - V0Vi + - Vi 𝑉𝑐 𝑇 2 − = 𝑉𝑐 𝑇 2 + =0V ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 40. Rf + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/2<t<3T/4 RL - + - V0Vi i VC +- ANIL PRASAD DADI/DEPT OF ECE/ANITS Diode is forward biased
- 41. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/2<t<3T/4 RL - + - V0Vi i VC +- VC= -Vi 𝑉𝑐 3𝑇 4 − = 𝑉𝑐 3𝑇 4 + =+Vm ANIL PRASAD DADI/DEPT OF ECE/ANITS Rf RfC<<T, Time period of input signal τ=RthC=(Rf||RL)C=RfC
- 42. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/2<t<3T/4 RL - + - V0Vi i VC +- V0 ≈ 0 ANIL PRASAD DADI/DEPT OF ECE/ANITS Rf
- 43. + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 3T/4<t<T RL - + - V0Vi VC +- 𝑉𝑐 3𝑇 4 − = 𝑉𝑐 3𝑇 4 + =+Vm V0=VD=VC+Vi VD =Vm+Vi + - VD ANIL PRASAD DADI/DEPT OF ECE/ANITS Let Vm=10V 10-9.9 10-9.8 ….
- 44. + RL C Positive Clamper circuit + - + - V0Vi 3T/4<t<T RL - + - V0Vi Vm +- Diode is reverse biased V0=Vm+Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Rr Vi(t) tT 3𝑇 4 2Vm 𝑇 4 𝑇 2 T RLC>>T, Time period of input signal τ=RthC=(Rr||RL)C τ=RLC
- 45. Analysis of Negative clamper circuit using diode equivalent resistance model ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 46. Vi RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 VC(0 -)=0=VC(0+) Capacitor is initially uncharged + RL VC=0 - + - Vi + - ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 47. RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 0<t<T/4 VC(0 -)=0=VC(0+) Capacitor is initially uncharged + RL - + - Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS RfDiode is forward biased
- 48. - RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 0<t<T/4 + RL VC - + - Vi i + 𝑉𝑐 𝑇 4 − = 𝑉𝑐 𝑇 4 + =+VmVC= Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Rf τ=RthC=(Rf||RL)C=RfC RfC<<T, Time period of input signal
- 49. - RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 0<t<T/4 + RL VC - + - Vi i +V0 ≈ 0 ANIL PRASAD DADI/DEPT OF ECE/ANITS Rf
- 50. VD - RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/4<t<T/2 + RL VC - + - Vi +𝑉𝑐 𝑇 4 − = 𝑉𝑐 𝑇 4 + =+Vm VD= -VC+Vi + - V0 ANIL PRASAD DADI/DEPT OF ECE/ANITS Let Vm=10V -10+9.9 -10+9.8 …. VD= -Vm+Vi
- 51. - RL C Negative Clamper circuit + - + - V0Vi T/4<t<T/2 + RL Vm - + - Vi + V0 V0= Vi - Vm ANIL PRASAD DADI/DEPT OF ECE/ANITS Rr Diode is reversed biased Vi(t) t𝑇 2 T𝑇 4 𝑇 4 3𝑇 4 -2Vm RLC>>T, Time period of input signal τ=RthC=(Rr||RL)C τ=RLC
- 52. Analysis of Positive clamper circuit using Constant voltage drop model ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 53. - + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL VC=0 - + - V0Vi VC(0 -)=0=VC(0+) Capacitor is initially uncharged + Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Vγ
- 54. - + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 0<t<T/4 RL VC=0 - + - V0Vi VC(0 -)=0=VC(0+) Capacitor is initially uncharged + Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS VγDiode is reverse biased
- 55. - + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL VC=0 - + - V0Vi + Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Vγ 𝑉𝑐 𝑇 4 − = 𝑉𝑐 𝑇 4 + =0V τ=RthC=RLC RLC>>T, Time period of input signal 0<t<T/4
- 56. - + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL VC=0 - + - V0Vi + Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Vγ 0<t<T/4 V0=Vi
- 57. - + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/4<t<T/2 RL VC=0 - + - V0Vi 𝑉𝑐 𝑇 4 − = 𝑉𝑐 𝑇 4 + =0V ANIL PRASAD DADI/DEPT OF ECE/ANITS Vγ + Vi
- 58. - + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/4<t<T/2 RL VC=0 - + - V0Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Vγ + Vi Diode is reverse biased
- 59. - + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/4<t<T/2 RL VC=0 - + - V0Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Vγ + Vi 𝑉𝑐 𝑇 2 − = 𝑉𝑐 𝑇 2 + =0V τ=RthC=RLC RLC>>T, Time period of input signal
- 60. - + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/4<t<T/2 RL VC=0 - + - V0Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Vγ + Vi V0=Vi
- 61. - + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL VC=0 - + - V0Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Vγ + Vi T/2<t<3T/4 𝑉𝑐 𝑇 2 − = 𝑉𝑐 𝑇 2 + =0V
- 62. - + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL VC - + - V0Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Vγ + Vi T/2<t<3T/4 τ=RthC=0 VC +Vi +Vγ=0 𝑉𝑐 3𝑇 4 − = 𝑉𝑐 3𝑇 4 + = Vm -Vγ - i Diode is in forward bias for Vi>- Vγ VC =-(Vi +Vγ)
- 63. - + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 RL VC - + - V0Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS Vγ + Vi T/2<t<3T/4 - i V0= -Vγ
- 64. Vγ + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 3T/4<t<T RL - + - V0Vi VC +- 𝑉𝑐 3𝑇 4 − = 𝑉𝑐 3𝑇 4 + = Vm -Vγ VC+Vi+Vγ-VD=0 VD=VC+ Vγ +Vi Let Vm=10V + - VD ANIL PRASAD DADI/DEPT OF ECE/ANITS 10-9.9 10-9.8 …. VD= Vm -Vγ + Vγ +Vi VD= Vm +Vi
- 65. Vγ + RL C Positive Clamper circuit + - + - Vi(t) 0 V0Vi t 𝑇 2 T𝑇 4 3𝑇 4 3T/4<t<T RL - + - V0Vi Vm -Vγ +- ANIL PRASAD DADI/DEPT OF ECE/ANITS Diode is reverse biased V0=VC+Vi V0= Vm -Vγ +Vi 2Vm- Vγ τ=RthC=RLC RLC>>T, Time period of input signal
- 66. Analysis of Negative clamper circuit using Constant voltage drop model ANIL PRASAD DADI/DEPT OF ECE/ANITS
- 67. - Vi RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 VC(0 -)=0=VC(0+) Capacitor is initially uncharged + RL VC=0 - + - Vi + ANIL PRASAD DADI/DEPT OF ECE/ANITS Vγ
- 68. Vγ - RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 0<t<T/4 VC(0 -)=0=VC(0+) Capacitor is initially uncharged + RL VC=0 - + - Vi + ANIL PRASAD DADI/DEPT OF ECE/ANITS Diode is forward biased for Vi> Vγ
- 69. VC Vγ - RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 + RL - + - Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS 0<t<T/4 τ=RthC=0 𝑉𝑐 𝑇 4 − = 𝑉𝑐 𝑇 4 + =Vm –Vγ VC-Vi +Vγ=0 VC=Vi –Vγ
- 70. VC Vγ - RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 + RL - + - Vi ANIL PRASAD DADI/DEPT OF ECE/ANITS 0<t<T/4 V0=Vγ
- 71. - VD - RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t𝑇 2 T𝑇 4 3𝑇 4 T/4<t<T/2 + RL VC - + - Vi +𝑉𝑐 𝑇 4 − = 𝑉𝑐 𝑇 4 + = Vm –Vγ -VC+Vi –Vγ-VD=0 + V0 Let Vm=10V ANIL PRASAD DADI/DEPT OF ECE/ANITS VγVD =-VC –Vγ +Vi -10+9.9 -10+9.8 ….VD =-Vm +Vγ–Vγ +Vi VD =-Vm +Vi
- 72. - RL C Negative Clamper circuit + - + - Vi(t) 0 V0Vi t 𝑇 2 T 3𝑇 4 T/4<t<T/2 + RL VC - + - Vi + V0 ANIL PRASAD DADI/DEPT OF ECE/ANITS Vγ V0= Vi - VC Diode is reverse biased V0= Vi - Vm +Vγ 𝑇 4 -2Vm+Vγ τ=RthC=RLC RLC>>T, Time period of input signal
- 73. Thank you For Watching ANIL PRASAD DADI/DEPT OF ECE/ANITS ANIL NEERUKONDA INSTITUTE OF TECHNOLOGY & SCIENCES(A) Department of Electronics and Communication Engineering