computer organization and Architecture Introduction

Computer Organization
Computer Organization

3 Fundamental Components
3 Fundamental Components
of Computer
of Computer
 The CPU (ALU, Control Unit, Registers)
The CPU (ALU, Control Unit, Registers)
 The Memory Subsystem (Stored Data)
The Memory Subsystem (Stored Data)
 The I/O subsystem
The I/O subsystem (I/O devices)
(I/O devices)
I/O Device
Subsystem
Address Bus
Data Bus
Control Bus
CPU Memory
Subsystem
2

Each of these Components
Each of these Components
are connected through
are connected through
Buses.
Buses.
 BUS - Physically a set of wires. The
BUS - Physically a set of wires. The
components of the Computer are
components of the Computer are
connected to these buses.
connected to these buses.
 Address Bus
Address Bus
 Data Bus
Data Bus
 Control Bus
Control Bus
3

Address Bus
Address Bus
 Used to specify the address of the memory
Used to specify the address of the memory
location to access.
location to access.
 Each I/O devices has a unique address.
Each I/O devices has a unique address.
(monitor, mouse, cd-rom)
(monitor, mouse, cd-rom)
 CPU reads data or instructions from other
CPU reads data or instructions from other
locations by specifying the address of its
locations by specifying the address of its
location.
location.
 CPU always outputs to the address bus and
CPU always outputs to the address bus and
never reads from it.
never reads from it.
4

Data Bus
Data Bus
 Actual data is transferred via the data
Actual data is transferred via the data
bus.
bus.
 When the cpu sends an address to
When the cpu sends an address to
memory, the memory will send data
memory, the memory will send data
via the data bus in return to the cpu.
via the data bus in return to the cpu.
5

Control Bus
Control Bus
 Collection of individual control signals.
Collection of individual control signals.
 Whether the cpu will read or write data.
Whether the cpu will read or write data.
 CPU is accessing memory or an I/O
CPU is accessing memory or an I/O
device
device
 Memory or I/O is ready to transfer data
Memory or I/O is ready to transfer data
6

I/O Bus or Local Bus
I/O Bus or Local Bus
 In today’s computers the the I/O
In today’s computers the the I/O
controller will have an extra bus
controller will have an extra bus
called the I/O bus.
called the I/O bus.
 The I/O bus will be used to access all
The I/O bus will be used to access all
other I/O devices connected to the
other I/O devices connected to the
system.
system.
 Example: PCI bus
Example: PCI bus
7

Instruction Cycles
Instruction Cycles
 Procedure the CPU goes through to
Procedure the CPU goes through to
process an instruction.
process an instruction.
 1. Fetch - get instruction
1. Fetch - get instruction
 2. Decode - interperate the
2. Decode - interperate the
instruction
instruction
 3. Execute - run the instruction.
3. Execute - run the instruction.
8

CPU organization
CPU organization
 CPU controls the Computer
CPU controls the Computer
 The CPU will fetch, decode and
The CPU will fetch, decode and
execute instructions.
execute instructions.
 The CPU has three internal sections:
The CPU has three internal sections:
register section, ALU and Control Unit
register section, ALU and Control Unit
9

Register Section
Register Section
 Includes collection of registers and a
Includes collection of registers and a
bus.
bus.
 Processor’s instruction set architecture
Processor’s instruction set architecture
are found in this section.
are found in this section.
 Non accessible registers by the
Non accessible registers by the
programmer. These are to be used for
programmer. These are to be used for
registers to latch the address being
registers to latch the address being
accessed and a temp storage register.
accessed and a temp storage register.
10

Arithmetic/Logic Unit (ALU)
Arithmetic/Logic Unit (ALU)
 Performs most Arithmetic and logical
Performs most Arithmetic and logical
operations.
operations.
 Retrieves and stores its information
Retrieves and stores its information
with the register section of the CPU.
with the register section of the CPU.
11

MEMORY ORGANIZATION
MEMORY ORGANIZATION
• Memory Hierarchy
Memory Hierarchy
• Main Memory
Main Memory
• Auxiliary Memory
Auxiliary Memory
• Associative Memory
Associative Memory
• Cache Memory
Cache Memory
• Virtual Memory
Virtual Memory
• Memory Management Hardware`
Memory Management Hardware`
12

Memory
Main memory consists of a number of
storage locations, each of which is
identified by a unique address
The ability of the CPU to identify each
location is known as its addressability
Each location stores a word i.e. the
number of bits that can be processed by
the CPU in a single operation. Word
length may be typically 16, 24, 32 or as
many as 64 bits.
A large word length improves system
performance, though may be less efficient on
occasions when the full word length is not
used
13

MEMORY HIERARCHY
MEMORY HIERARCHY
Magnetic
tapes
Magnetic
disks
I/O
processor
CPU
Main
memory
Cache
memory
Auxiliary memory
Register
Cache
Main Memory
Magnetic Disk
Magnetic Tape
Memory Hierarchy is to obtain the highest possible
access speed while minimizing the total cost of the memory system
Memory Hierarchy
14

Memory Subsystem
Memory Subsystem
 2 Types of Memory:
2 Types of Memory:
– ROM : Read Only Memory
ROM : Read Only Memory

Program that is loaded into memory and
Program that is loaded into memory and
cannot be changed also retains its data even
cannot be changed also retains its data even
without power.
without power.
– RAM : Random Access Memory
RAM : Random Access Memory

Also called read/write memory. This type of
Also called read/write memory. This type of
memory can have a program loaded and then
memory can have a program loaded and then
reloaded. It also loses its data with no power.
reloaded. It also loses its data with no power.
15

Different ROM Chips
Different ROM Chips
 Masked ROM :
Masked ROM :

ROM that is programmed with data when
ROM that is programmed with data when
fabricated. Data will not change once installed.
fabricated. Data will not change once installed.
Hardwired.
Hardwired.
 Programmable ROM (PROM) :
Programmable ROM (PROM) :

Capable of being programmed by the user with a
Capable of being programmed by the user with a
ROM programmer. Not hardwired.
ROM programmer. Not hardwired.
 Erasable PROM (EPROM) :
Erasable PROM (EPROM) :

Much like the PROM this EPROM can be
Much like the PROM this EPROM can be
programmed and then erased by light.
programmed and then erased by light.
 EEPROM :
EEPROM :

Another form of EPROM but is reprogammable
Another form of EPROM but is reprogammable
electrically.
electrically. 16

Different RAM Chips
Different RAM Chips
 Dynamic RAM (DRAM) :
Dynamic RAM (DRAM) :

Leaky capacitors. Caps are charged and slowly
Leaky capacitors. Caps are charged and slowly
leak until they are refreshed to there original
leak until they are refreshed to there original
data locations. Ex. Computer RAM
data locations. Ex. Computer RAM
 Static RAM (SRAM) :
Static RAM (SRAM) :

Much like a register. The contents stay valid and
Much like a register. The contents stay valid and
does not have to be refreshed. SRAM is faster
does not have to be refreshed. SRAM is faster
than DRAM but cost more Ex. Cache
than DRAM but cost more Ex. Cache
– Each RAM chip has 2^n * m. n address
Each RAM chip has 2^n * m. n address
inputs and m bidirectional data pins
inputs and m bidirectional data pins
17

The operation of cache memory
1. Cache fetches data from
next to current addresses in
main memory
2. CPU checks to see
whether the next instruction
it requires is in cache
3. If it is, then the
instruction is fetched from
the cache – a very fast
position
4. If not, the CPU has to
fetch next instruction from
main memory - a much
slower process
Main
Memory
(DRAM)
CPU
Cache
Memory
(SRAM)
= Bus connections 18

Addressing Modes
Addressing Modes
 Immediate
Immediate
 Direct
Direct
 Indirect
Indirect
 Register
Register
 Register Indirect
Register Indirect
 Displacement (Indexed)
Displacement (Indexed)
 Stack
Stack
19

Immediate Addressing
 Operand is part of instruction
Operand is part of instruction
 Operand = address field
Operand = address field
 e.g. ADD 5
e.g. ADD 5
– Add 5 to contents of accumulator
Add 5 to contents of accumulator
– 5 is operand
5 is operand
 No memory reference to fetch data
No memory reference to fetch data
 Fast
Fast
 Limited range
Limited range
20

Diagram
Diagram
Operand
Opcode
Instruction
21

Direct Addressing
Direct Addressing
 Address field contains address of
Address field contains address of
operand
operand
 Effective address (EA) = address field (A)
Effective address (EA) = address field (A)
 e.g. ADD A
e.g. ADD A
– Add contents of cell A to accumulator
Add contents of cell A to accumulator
– Look in memory at address A for operand
Look in memory at address A for operand
 Single memory reference to access data
Single memory reference to access data
 No additional calculations to work out
No additional calculations to work out
effective address
effective address
 Limited address space
Limited address space
22

Direct Addressing Diagram
Address A
Opcode
Instruction
Memory
Operand
23

Address A
Opcode
Instruction
Memory
Operand
24

Indirect Addressing (1)
 Memory cell pointed to by address field
Memory cell pointed to by address field
contains the address of (pointer to) the
contains the address of (pointer to) the
operand
operand
 EA = (A)
EA = (A)
– Look in A, find address (A) and look there for
Look in A, find address (A) and look there for
operand
operand
 e.g. ADD (A)
e.g. ADD (A)
– Add contents of cell pointed to by contents
Add contents of cell pointed to by contents
of A to accumulator
of A to accumulator
25

 Large address space
Large address space
 2
2n
n
where n = word length
where n = word length
 May be nested, multilevel, cascaded
May be nested, multilevel, cascaded
– e.g. EA = (((A)))
e.g. EA = (((A)))

Draw the diagram yourself
Draw the diagram yourself
 Multiple memory accesses to find
Multiple memory accesses to find
operand
operand
 Hence slower
Hence slower
26

Indirect Addressing Diagram
Indirect Addressing Diagram
Address A
Opcode
Instruction
Memory
Operand
Pointer to operand
27

Register Addressing (1)
 Operand is held in register named in
Operand is held in register named in
address filed
address filed
 EA = R
EA = R
 Limited number of registers
Limited number of registers
 Very small address field needed
Very small address field needed
– Shorter instructions
Shorter instructions
– Faster instruction fetch
Faster instruction fetch
28

 No memory access
No memory access
 Very fast execution
Very fast execution
 Very limited address space
Very limited address space
 Multiple registers helps performance
Multiple registers helps performance
– Requires good assembly programming or
Requires good assembly programming or
compiler writing
compiler writing
– N.B. C programming
N.B. C programming

register int a;
register int a;
 c.f. Direct addressing
c.f. Direct addressing
29

Register Addressing
Register Addressing
Diagram
Diagram
Register Address R
Opcode
Instruction
Registers
Operand
30

Register Indirect Addressing
Register Indirect Addressing
 C.f. indirect addressing
C.f. indirect addressing
 EA = (R)
EA = (R)
 Operand is in memory cell pointed to
Operand is in memory cell pointed to
by contents of register R
by contents of register R
 Large address space (2
Large address space (2n
n
)
)
 One fewer memory access than
One fewer memory access than
indirect addressing
indirect addressing
31

Register Indirect Addressing Diagram
Register Indirect Addressing Diagram
Register Address R
Opcode
Instruction
Memory
Operand
Pointer to Operand
Registers
32

Displacement Addressing
Displacement Addressing
 EA = A + (R)
EA = A + (R)
 Address field hold two values
Address field hold two values
– A = base value
A = base value
– R = register that holds displacement
R = register that holds displacement
– or vice versa
or vice versa
33

Displacement Addressing Diagram
Displacement Addressing Diagram
Register R
Opcode
Instruction
Memory
Operand
Pointer to Operand
Registers
Address A
+
34

Relative Addressing
Relative Addressing
 A version of displacement addressing
A version of displacement addressing
 R = Program counter, PC
R = Program counter, PC
 EA = A + (PC)
EA = A + (PC)
 i.e. get operand from A cells from
i.e. get operand from A cells from
current location pointed to by PC
current location pointed to by PC
 c.f locality of reference & cache usage
c.f locality of reference & cache usage
35

Base-Register Addressing
Base-Register Addressing
 A holds displacement
A holds displacement
 R holds pointer to base address
R holds pointer to base address
 R may be explicit or implicit
R may be explicit or implicit
 e.g. segment registers in 80x86
e.g. segment registers in 80x86
36

Indexed Addressing
Indexed Addressing
 A = base
A = base
 R = displacement
R = displacement
 EA = A +
EA = A + (
(R
R)
)
 Good for accessing arrays
Good for accessing arrays
– EA = A +
EA = A + (
(R
R)
)
– R++
R++
37

Stack Addressing
Stack Addressing
 Operand is (implicitly) on top of stack
Operand is (implicitly) on top of stack
 e.g.
e.g.
– ADD
ADD Pop top two items from stack
Pop top two items from stack
and add
and add
38

Input-Output Organization
Input-Output Organization
 11-1
11-1 Peripheral Devices
Peripheral Devices
– I/O Subsystem
I/O Subsystem

Provides an efficient mode of
Provides an efficient mode of
communication between the central system
communication between the central system
and the outside environment
and the outside environment
– Peripheral (
Peripheral (or
or I/O Device
I/O Device)
)

Input or Output devices attached to the
Input or Output devices attached to the
computer
computer
 11-2
11-2 Input-Output Interface
Input-Output Interface

1)
1) A conversion of signal values may be
A conversion of signal values may be
required
required
39


2)
2) A synchronization mechanism may be needed
A synchronization mechanism may be needed
– The data transfer rate of peripherals is usually slower than the
The data transfer rate of peripherals is usually slower than the
transfer rate of the CPU
transfer rate of the CPU

3) Data codes and formats in peripherals differ from the
3) Data codes and formats in peripherals differ from the
word format in the CPU and Memory
word format in the CPU and Memory

4) The operating modes of peripherals are different from
4) The operating modes of peripherals are different from
each other
each other
– Each peripherals must be controlled so as not to disturb the
Each peripherals must be controlled so as not to disturb the
operation of other peripherals connected to the CPU
operation of other peripherals connected to the CPU
– Interface
Interface

Special hardware components between the CPU and
Special hardware components between the CPU and
peripherals
peripherals

Supervise and Synchronize all input and output transfers
Supervise and Synchronize all input and output transfers
Interface
Keyboard
and
display
terminal
Interfac e
Magnetic
tape
Interfac e
Magnetic
disk
Interfac e
Printer
Processor
Data
C ontrol
Address
I/O bus
40

– Transfer
Transfer
– Synchronous Data Transfer
Synchronous Data Transfer

All data transfers occur
All data transfers occur
simultaneously during the
simultaneously during the
occurrence of a clock pulse
occurrence of a clock pulse

Registers in the
Registers in the interface
interface
share a common clock with
share a common clock with
CPU
CPU registers
registers
– Asynchronous Data Transfer
Asynchronous Data Transfer

Internal timing in each unit
Internal timing in each unit
(
(CPU and Interface
CPU and Interface) is
) is
independent
independent

Each unit uses its own private
Each unit uses its own private
clock for internal registers
clock for internal registers
41

Source
unit
Destination
unit
(a) Block diagram
Valid data
Data
Strobe
(b) Timing diagram
Data bus
Strobe
Source
unit
Destination
unit
(a) Block diagram
Valid data
Data
Strobe
(b) Timing diagram
Data bus
Strobe
Fig. 11-3 Source-
initiated strobe
Fig. 11-4 Destination-
initiated strobe

 

42

– Handshake :
Handshake : Agreement betwee
Agreement betwee
S ource
unit
Destination
unit
(a) Block diagram
Valid data
Data
(b) Timing diagram
Data bus
Data valid
Data accepted
Data valid
Data acc epted
Place data on bus
E nable data valid.
Disable data valid
Invalidate data on bus
Accept data from bus
E nable data accepted
Disable data accepted
Ready to acc ept data
(initial state)
(c) S equenc e of events
S ource unit Destination unit
Fig. 11-5 Source-initiated handshake
S ource
unit
Destination
unit
(a) Block diagram
Valid data
(b) Timing diagram
Data bus
Data valid
Ready for data
Data valid
Data bus
Place data on bus
Enable data valid.
Disable data valid
Invalidate data on bus
(initial state)
Accept data from bus
Disable reday for data
Ready to ac cept
data.
Enable ready for data
(c) S equence of events
Ready for data
S ource unit Destination unit
Fig. 11-6 Destination-initiated handshak






43

 11-4
11-4 Modes of Transfer
Modes of Transfer
– Data transfer to and from peripherals
Data transfer to and from peripherals

1) Programmed I/O
1) Programmed I/O

2) Interrupt-initiated I/O
2) Interrupt-initiated I/O

3) Direct Memory Access
3) Direct Memory Access
(
(DMA
DMA)
)

4) I/O Processor (
4) I/O Processor (IOP
IOP)
)
Interrupt-initiated I/O
Interrupt-initiated I/O

1) Non-vectored : fixed branch
1) Non-vectored : fixed branch
address
address

2) Vectored : interrupt source
2) Vectored : interrupt source
supplies the branch address
supplies the branch address
(
(interrupt vector
interrupt vector)
)
Read status register
C heck flag bit
Read data register
Transfer data to memory
C ontinue
with
program
Flag
Operation
com plete ?
= 0
= 1
yes
no
44

– Polling
Polling

Identify the highest-priority source by software means
Identify the highest-priority source by software means
– One common branch address is used for all interrupts
One common branch address is used for all interrupts
– Program polls the interrupt sources in sequence
Program polls the interrupt sources in sequence
– The highest-priority source is tested first
The highest-priority source is tested first

Polling priority interrupt
Polling priority interrupt
– If there are many interrupt sources, the time required to poll
If there are many interrupt sources, the time required to poll
them can exceed the time available to service the I/O device
them can exceed the time available to service the I/O device
– 따라서
따라서 Hardware priority interrupt
Hardware priority interrupt
– Daisy-Chaining :
Daisy-Chaining :
Devic e 1
PI PO
Devic e 3
PI PO
Devic e 2
PI PO
To next
Devic e
C PU
INT
INTAC K
Interrupt request
Interrupt ac knowledge
Proc essor data bus
VAD 1 VAD 3
VAD 2
“1
”
“1
”
“0
”
45


One stage of the daisy-chain priority
One stage of the daisy-chain priority
arrangement :
arrangement : Fig. 11-13
Fig. 11-13

 No interrupt request
No interrupt request

 Invalid : interrupt request, but no
Invalid : interrupt request, but no
acknowledge
acknowledge

 No interrupt request : Pass to other device
No interrupt request : Pass to other device
(
(other device requested interrupt
other device requested interrupt )
)

 Interrupt request
Interrupt request
S Q
R
Vec tor address
Delay
E nable
RF
PI
Priority in
Interrupt
request
from devic e
Open- c ollector
inverter Interrupt request to C PU
Priority out
PO
VAD
RF
PI PO Enable
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1




INTACK
INT
46

 Direct Memory Access (
Direct Memory Access (DMA
DMA)
)
– DMA
DMA
 DMA controller takes over the buses to
DMA controller takes over the buses to
manage the transfer
manage the transfer directly
directly between the
between the
I/O device
I/O device and
and memory
memory
C PU
BR
BG
DBUS
WR
ABUS
RD
Bus request
Bus grant
Address bus
Write
Read
Data bus
High- impedance
(disable)
when BG is
enabled
DMA
C ontroller
BR
BG
47

– Transfer Modes
Transfer Modes

1) Burst transfer :
1) Burst transfer :

2)
2) Cycle stealing transfer
Cycle stealing transfer
– DMA Controller (
DMA Controller ( Intel 8237 DMAC
Intel 8237 DMAC )
)

DMA Initialization Process
DMA Initialization Process
– 1)
1) Set Address register :
Set Address register :

memory address for read/write
memory address for read/write
– 2)
2) Set Word count register :
Set Word count register :

the number of words to transfer
the number of words to transfer
– 3)
3) Set transfer mode :
Set transfer mode :
4) DMA transfer start :
4) DMA transfer start :
– 5) EOT (End of Transfer) :
5) EOT (End of Transfer) :
Control
logic
CS
Data bus
buffers
Control register
Data bus
DMA select
I
n
t
e
r
n
a
l
b
u
s
RS
Interrupt
BG
BR
RD
WR
Registerselect
Read
Write
Bus request
Bus grant
Interrupt
Address register
Word countregister
Address bus
buffers
Address bus
DMA request
DMA Acknowledge
to I/O device
48

– DMA Transfer (
DMA Transfer (I/O to Memory
I/O to Memory)
)

1) I/O Device sends a DMA request
1) I/O Device sends a DMA request

2) DMAC activates the
2) DMAC activates the BR
BR line
line

3) CPU responds with
3) CPU responds with BG
BG line
line

4) DMAC sends a DMA acknowledge
4) DMAC sends a DMA acknowledge
to the I/O device
to the I/O device

5) I/O device puts a word in the data
5) I/O device puts a word in the data
bus (
bus (for memory write
for memory write)
)

6) DMAC write a data to the address
6) DMAC write a data to the address
specified by
specified by Address register
Address register

7) Decrement
7) Decrement Word count register
Word count register

8)
8) Word count
Word count

9
9)
) Word count register
Word count register
I/O
Peripheral
device
DMA acknowledge
Address
select
CPU
Interrupt
Address Data
BG
BR
RD WR
Random access
memory (RAM)
Address Data
RD WR
Directmemory
access (DAM)
controller
Interrupt
Address Data
RD WR
BG
RS
DS
BR
DMA request
Read control
Write control
Address bus
Data bus
49

 Input-Output Processor (
Input-Output Processor (IOP
IOP)
)
– IOP
IOP

Communicate directly with all I/O devices
Communicate directly with all I/O devices

Fetch and execute its own instruction
Fetch and execute its own instruction
– IOP instructions are specifically designed to facilitate I/O transfer
IOP instructions are specifically designed to facilitate I/O transfer
– DMAC must be set up entirely by the CPU
DMAC must be set up entirely by the CPU

Designed to handle the details of I/O processing
Designed to handle the details of I/O processing
Memory unit
Central Processing
unit (CPU)
Input- output
processor (IOP)
Memory
bus
PD PD
PD
PD
Peripheral devices
I/O bus
50

– CPU - IOP Communication
CPU - IOP Communication

Memory units acts as a message center :
Memory units acts as a message center :
– each processor leaves information for the other
each processor leaves information for the other
C PU operations IOP operations
S end instruction
to test IOP path
Transfer status word
to memory loc ation
If status OK. , send
start I/O instruction
to IOP
Access memory for
IOP program
C PU continues with
another program
C onduct I/O transfer
using DMA ; prepare
status report
I/O transfer completed
interrupt C PU
Request IOP status
Transfer status word
to memory loc ation
C hec k status word
for correct transfer
C ontinue
51

Input/output Devices
Input/output Devices
 Input/output devices are required for
Input/output devices are required for
users to communicate with the computer.
users to communicate with the computer.
 In simple terms, input devices bring
In simple terms, input devices bring
information INTO the computer and
information INTO the computer and
output devices bring information OUT of
output devices bring information OUT of
a computer system. These input/output
a computer system. These input/output
devices are also known as peripherals.
devices are also known as peripherals.
52

Input Devices are:
Input Devices are:
 Keyboard
Keyboard
 Mouse
Mouse
 Joystick
Joystick
 Scanner
Scanner
 Light Pen
Light Pen
 Touch Screen
Touch Screen
53

Output devices are:
Output devices are:
 Printers
Printers
 Plotters
Plotters
 Monitor
Monitor
 LCD
LCD
54

55
Intel 8086/8088
Intel 8086/8088
Microprocessors
Microprocessors
 Intel 8086 and 8088 Microprocessors
Intel 8086 and 8088 Microprocessors
are the basis of all IBM-PC compatible
are the basis of all IBM-PC compatible
computers
computers
(8086 introduced in 1978, first IBM-PC released in 1981)
(8086 introduced in 1978, first IBM-PC released in 1981)
 All Intel, AMD and other advanced
All Intel, AMD and other advanced
microprocessors are based on and are
microprocessors are based on and are
compatible with the original 8086/8
compatible with the original 8086/8
 At Power Up and Reset time, Pentiums,
At Power Up and Reset time, Pentiums,
Athlons etc all look like 8086 processors
Athlons etc all look like 8086 processors

56
Intel 8086/8088
Intel 8086/8088
Microprocessors
Microprocessors
 Intel 8086 is a 16b microprocessor:
Intel 8086 is a 16b microprocessor:
– 16b data registers, 16b ALU
16b data registers, 16b ALU
 Width of external data bus:
Width of external data bus:
– 8086: 16b
8086: 16b
– 8088: 8b
8088: 8b
 Width of external address bus: 16b+4b=
Width of external address bus: 16b+4b=20b
20b
 Some techniques to optimise the CPU
Some techniques to optimise the CPU
performance when it’s executing programs
performance when it’s executing programs
 Segment: Offset memory model
Segment: Offset memory model
 Little-Endian
Little-Endian Data Format
Data Format

57
8086/8088
8086/8088
 Original IBM PC used 8088 microprocessor
Original IBM PC used 8088 microprocessor
 8088 is similar to the 8086, but it has an
8088 is similar to the 8086, but it has an
external 8b data bus & only 4B-deep queue
external 8b data bus & only 4B-deep queue
– For cost reduction reasons
For cost reduction reasons
 We can consider 8086 and 8088 together
We can consider 8086 and 8088 together
 PC clones often used 8086 for better
PC clones often used 8086 for better
performance
performance
 8-bit bus reduces performance, but meant
8-bit bus reduces performance, but meant
cheaper computers
cheaper computers

58
8086/8088 Functional Units
8086/8088 Functional Units
Execution Unit
(EU)
Bus Interface
Unit(BIU)
Fetches Opcodes,
Reads Operands,
Writes Data
8086/8088 MPU

59
8086/8088
8086/8088
 8086/8088 consists of two internal units
8086/8088 consists of two internal units
– The execution unit (EU) - executes the
The execution unit (EU) - executes the
instructions
instructions
– The bus interface unit (BIU) - fetches
The bus interface unit (BIU) - fetches
instructions, reads operands and writes
instructions, reads operands and writes
results
results
 The 8086 has a 6B prefetch queue
The 8086 has a 6B prefetch queue
 The 8088 has a 4B prefetch queue
The 8088 has a 4B prefetch queue

60
Organisation
Organisation
Temporary
Registers
ALU
Flags
EU
Control
AH AL
BH BL
CH CL
DH DL
SP
BP
DI
BI
CS
DS
SS
ES
IO
Internal
Communications
Registers
SUMMATION
Address Bus 20 bits
Data Bus
Bus
Control
1 2 3 4
Instruction Queue
8088
Bus
EU BIU

BIU Elements
BIU Elements
 Instruction Queue: the next instructions or data can be
Instruction Queue: the next instructions or data can be
fetched from memory while the processor is executing
the current instruction
– The memory interface is slower than the processor execution
The memory interface is slower than the processor execution
time so this speeds up overall performance
 Segment Registers:
Segment Registers:
– CS, DS, SS and ES are 16b registers
CS, DS, SS and ES are 16b registers
– Used with the 16b Base registers to generate the 20b address
Used with the 16b Base registers to generate the 20b address
– Allow the 8086/8088 to address 1MB of memory
Allow the 8086/8088 to address 1MB of memory
– Changed under program control to point to different
Changed under program control to point to different
segments as a program executes
 Instruction Pointer (IP) contains the Offset Address of
Instruction Pointer (IP) contains the Offset Address of
the next instruction, the distance in bytes from the
address given by the current CS register
61

62
8086/8088 20-bit Addresses
8086/8088 20-bit Addresses
16-bit Segnment Base Address 0000
16-bit Offset Address
20-bit Physical Address
CS
IP

BIU Elements
BIU Elements
 Instruction Queue: the next instructions or data can be
Instruction Queue: the next instructions or data can be
– The memory interface is slower than the processor execution
The memory interface is slower than the processor execution
 Segment Registers:
Segment Registers:
– CS, DS, SS and ES are 16b registers
CS, DS, SS and ES are 16b registers
– Used with the 16b Base registers to generate the 20b address
Used with the 16b Base registers to generate the 20b address
– Allow the 8086/8088 to address 1MB of memory
Allow the 8086/8088 to address 1MB of memory
– Changed under program control to point to different
Changed under program control to point to different
 Instruction Pointer (IP) contains the Offset Address of
Instruction Pointer (IP) contains the Offset Address of
63

64
MAXIMUM
MODE
MINIMUM
MODE
1 40
20 21
8086
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
Vcc
AD15
A16,S3
A17,S4
A18,S5
A19,S6
/BHE,S7
MN,/MX
/RD
/RQ,/GT0
/LOCK
/S2
/S1
/S0
QS0
QS1
/TEST
READY
RESET
/RQ,/GT1
HOLD
/WR
IO/M
DT/R
/DEN
ALE
/INTA
HLDA

65
8086/8088 Summary
8086/8088 Summary
 First Generation (introduced June 1978)
First Generation (introduced June 1978)
 One of the first 16b processors on the
One of the first 16b processors on the
market
market
 16b internal registers
16b internal registers
 16/8b external data bus
16/8b external data bus
 20b address bus (1MB addressable)
20b address bus (1MB addressable)
 Used in 1
Used in 1st
st
generation IBM PCs (1981)
generation IBM PCs (1981)

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