Cyclone iii
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The Cyclone III FPGA family provides an unprecedented combination of low power, high functionality, and low cost. It enables designs with up to 120K logic elements, 4Mbit embedded memory, and 288 embedded multipliers. The family includes devices ranging from 5K to 120K logic elements that meet the needs of emerging high-volume applications with 50% lower power than previous families.
![PLL Dynamic Phase Adjustment
Dynamic adjustment of PLL phase setting
Increase/decrease 1 step at a time
− Step increments depend on PLL configuration
inclk0 C0
Phasecounterselect[3:0] Phasedone
Phaseupdown PLL Locked
Phasestep
© 2009 Altera Corporation— Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.](https://image.slidesharecdn.com/cycloneiii-130419024806-phpapp02/85/Cyclone-iii-35-320.jpg)
![Clock Networks & PLLs Overview
Up to 20 Global Clocks Per Device
Dual purpose as high fan out control signals
4
GCLK
PLL 3 Mux PLL 2
GCLK [14:10]
4
GCLK GCLK
4 Mux GCLK [9:5] Mux
GCLK [0:4]
GCLK [15:19]
GCLK
PLL 1 PLL 4
Mux
© 2009 Altera Corporation— Public
4
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.](https://image.slidesharecdn.com/cycloneiii-130419024806-phpapp02/85/Cyclone-iii-41-320.jpg)
![Cyclone III PLL Functions
Clock Multiplication & Division
Clock Synthesis
Phase Alignment & Phase Shift
Output
Clock C0 Pin
Switchover
Clock Inputs C0
[1..0]
N Global
PFD CP LF VCO C1
Clock
C[4..0] Network
C2
M
C3
Feedback
C4
Reconfigurable in user mode
© 2009 Altera Corporation— Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.](https://image.slidesharecdn.com/cycloneiii-130419024806-phpapp02/85/Cyclone-iii-42-320.jpg)
![PLL Dynamic Phase Adjustment
Dynamic adjustment of PLL phase setting
Increase/decrease 1 step at a time
− Step increments depend on PLL configuration
inclk0 C0
Phasecounterselect[3:0] Phasedone
Phaseupdown PLL Locked
Phasestep
Enables Auto-Calibrating PHY for External Memory
Interfaces
© 2009 Altera Corporation— Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.](https://image.slidesharecdn.com/cycloneiii-130419024806-phpapp02/85/Cyclone-iii-44-320.jpg)
Cyclone iii
- 1. Cyclone III FPGA Family Unprecedented combination of low power, high functionality, and low cost to enable your new designs © 2009 Altera Corporation— Public
- 2. Meeting the Needs of Emerging High-Volume Applications • 50% lower power vs. Cyclone® II FPGAs • 5 – 120K LEs • 4-Mbits embedded RAM • 288 18 x 18 multipliers for DSP • 5 – 70K LEs • Higher performance DDR2 support • 1.1-Mbits embedded RAM • Nios II embedded processor • 150 18 x 18 multipliers for DSP • 2 – 20K logic elements (LEs) • DDR2 support • 295-Kbits embedded RAM • Nios II embedded processor • DDR support • Nios® embedded processor 2002 2004 2007 © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 3. Cyclone III Key Architectural Features 400-Mbps 65-nm low- external power process memory interfaces Up to 4-Mbit embedded Up to 288 memory embedded multipliers Up to 535 for high- flexible user throughput I/O pins DSP Parallel and 5 – 120K LEs serial configuration Dynamically with new configurable remote update phase-locked feature loops (PLLs) © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 4. System Integration System integration eases your design constraints FIFO UART CPU − Board space requirements − Cost pressures DDR2 UART − Product obsolescence concerns DSP − Short development times Flash ASSP Cyclone III FPGAs— complete feature set for DDR2 better integration over any other low-cost FPGA Flash Do more with less! © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 5. Power-Aware Design With Quartus II Software Design Timing Entry Constraints Automatic power reduction for maximum productivity Synthesis Up to 25% Place-and-route lower PowerPlay Power Analyzer power Timing, area, power optimization Power-optimized design © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 6. Lowest-Power Low-Cost FPGAs Lower Lower static Cyclone III family power reduction technique dynamic power power Process optimization Power-aware design with Quartus II software 50+ Percent Power Reduction vs. Cyclone II FPGAs © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 7. DSP Advantages Combination of logic, memory, and multipliers allows for efficient implementation of arithmetic DSP functions − Integrate multiple DSP devices into a single Cyclone III FPGA − Process multiple signal data streams at lower cost per channel than dedicated DSP devices DSP DSP 80 70 Gigamultiplies / sec 60 50 DSP DSP 40 30 Up to 20 Multi 288 pliers 10 0 ADI TS203S TI C6455 Altera EP3C25 Altera EP3C120 @ 600 MHz @ 1 GHz @ 260 MHz @ 223 MHz © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 8. Memory Optimizations Increased memory block size − Allows for increased memory capacity Cyclone II family Higher memory-to-logic ratio − Implement packet buffers − Integrate larger data and instruction caches for embedded 36 M4K 36 processors − or 4 Kbits or Integrate larger FIFO buffers 18 18 Optimized memory-to-multiplier ratio for intensive processing applications − Video line buffers Up to Cyclone III family − Video and image processing 4 Mb on-ch its ip memo 4.5 ry 4.0 36 M9K 36 Memory (Mbits) 3.5 Cyclone II FPGAs or 9 Kbits or 3.0 Cyclone III FPGAs 2.5 18 18 2.0 1.5 1.0 0.5 0 5K 8-10K 20-26K 30-40K 50-55K 70-120K © 2009 Altera Corporation— Public LEs ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 9. Clocking Resources Clock routing resources − Up to 20 global clocks − Global clock routing can also be used for global signals Global clock networks − Powered down when not in use to save power Full-featured and robust PLLs − Up to four low-jitter (200 ps) PLLs − Five programmable outputs per PLL − Wide frequency range of 5 to 440 MHz − Dynamically change both frequency and phase − Cascadable to allow broader Up to 20 networks per device frequency generation Flexible and robust clocking resources to support higher system integration © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 10. I/O Pin Features Variety of I/O Standards LVDS − HSTL, SSTL Class I and II up to 875 Mbps − LVDS, RSDS, Mini-LVDS, PPDS Bank 3 Bank 4 − LVCMOS Bank 5 Bank 5 Bank 2 − LVTTL − LVPECL − PCI, PCI-X Bank 6 Bank 6 Bank 1 3.3-V compatible On-chip termination Bank 8 Bank 7 Adjustable slew rates Eight banks of every device in the family − Each can implement any supported I/O standard DDR2 Dedicated memory interfaces up to 400 Mbps − QDR II, DDR, and DDR2 Complete flexibility to implement a wide variety of I/O standards © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 11. Memory Interfaces That Automatically Calibrate, Track, and Adjust Intellectual property (IP) auto calibrates for process differences − For both FPGA and memory − Removes timing uncertainties External memory Monitors voltage and temperature Memory variations / PHY / controller − Adjusts resynchronization IP / IP / phase (PLL output) − Does not interrupt operation − Supports DDR, DDR2, Flexibility to use Auto-calibrating PHY QDR II memories Altera® or custom minimizes effort for memory controller reliable timing closure Increase productivity and minimize timing closure efforts © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 12. New Configuration Features • Multiboot feature allows multiple Update programming files to be loaded into the Control Logic FPGA, and protect against remote system upgrade configuration failures • Remote system update no longer requires Serial or Parallel Configuration Device external host, saves board space Application n Application 1 Factory application © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 13. A Complete Solution Embedded Intellectual soft-core processors Design Development property software kits © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 14. Nios II Embedded Processor Choose the exact set of CPUs, peripherals, and memory you need for your application − Achieve over 160 DMIPs of performance − Build custom instructions − Accelerate with hardware—C2H compiler automatically converts C subroutines into hardware for Nios II embedded processor Low cost − Integrate your peripherals and microprocessor into a Available programmable single chip logic − Support for multiple processors in a single device − Implement a processor for $0.25 of logic on a Cyclone III FPGA Industry’s leading soft-core processor © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 15. Cyclone III Family Plan M9K Total 18 X 18 Device LEs memory memory PLLs Global clocks Multipliers blocks (Mbits) EP3C5 5,136 46 0.4 23 2 10 EP3C10 10,320 46 0.4 23 2 10 EP3C16 15,408 56 0.5 56 4 20 EP3C25 24,624 66 0.6 66 4 20 EP3C40 39,600 126 1.1 126 4 20 EP3C55 55,856 260 2.3 156 4 20 EP3C80 81,264 305 2.7 244 4 20 EP3C120 119,088 432 3.9 288 4 20 Notes: 1. Selected product lines are available in commercial, industrial, extended industrial, and automotive temperature variants. 2. Selected product lines/packages offer the following speed grades: -6 (fastest), -7, and -8. © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 16. Cyclone III Package Offerings E144 M164 Q240 F256 U256 F324 F484 U484 F780 N ew Device ! 0.5 mm 0.5 mm 0.5 mm 1.0 mm 0.8 mm 1.0 mm 1.0 mm 0.8 mm 1.0 mm 22 x 22 8x8 35 x 35 17 x 17 14 x14 19 x 19 23 x 23 19 x19 29 x 29 EP3C5 94 106 182 182 EP3C10 94 106 182 182 EP3C16 84 92 160 168 168 346 346 EP3C25 82 148 156 156 215 EP3C40 128 195 331 331 535 EP3C55 327 327 377 EP3C80 295 295 429 EP3C120 283 531 Denotes vertical migration support Optimized to offer the highest logic, memory, multiplier, and I/O resources © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 17. Technical Details © 2009 Altera Corporation— Public
- 18. Cyclone II LAB Structure Cyclone II Logic Array Block (LAB) 0 1 2 3 LUT LUT LUT LUT 7 6 5 4 LUT LUT LUT LUT LAB-Wide Control Block 8 9 10 11 LUT LUT LUT LUT 15 14 13 12 LUT LUT LUT LUT © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 19. Cyclone II Logic Element LUT Carry Carry Register Chain In0 In1 Chain Local Routing In1 In2 General LUT REG In3 Routing In4 Clock General Routing Carry Carry Register Out0 Out1 Chain © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 20. Embedded Multiplier Functionality Up to 260-MHz performance Supports full-precision 18-bit or 9-bit mode − One 18-bit or two 9-bit multipliers per block Sign_X Output Registers 18 X Input Registers 36 36 18 Y Sign_Y Clock Clear © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 21. On-Chip Memory Enhancements Cyclone III Feature Cyclone II (M4K) Benefit (M9K) Block Size 4 Kbits 9 Kbits Increased Memory Performance 216 MHz 260 MHz Faster Performance Dual-Port Read During New Data Flexibility and New Data or Old Data Write Behavior (“Flow Thru”) Ease of Use Usability for High Reliability Parity Bit Yes Yes Apps Increased Flexibility Clock Enables 2 4 and Reduced Power Increased Flexibility Read and Write Enables 2 4 and Reduced Power © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 22. I/O Enhancements I/O Enhancement Benefit All Interfaces and Standards -Allows flexible I/O placement for easier PCB design reduced Supported on all Banks board area -Eliminates external resistors for LVDS, RSDS, and mini-LVDS transmission Enhanced LVDS Buffers -Increases LVDS interface performance – up to 875 Mbps (Rx) & 840 Mbps (Tx) -OCT Eliminates external resistors Selectable Series OCT with -Improves signal integrity and performance with selectable Calibration impedance matching -Calibration eliminates variations due to PVT Two Additional I/O -Increases external interface performance Element Registers -Improves Tco performance -Improves signal integrity by slowing down edge rates on non- Adjustable Slew Rates performance critical I/O pins © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 23. All I/O Standards On All Banks Bank 8 Bank 7 3.3-V LVTTL 3.0-V LVTTL / LVCMOS 2.5-V LVTTL / LVCMOS 1.8-V LVTTL / LVCMOS Bank 1 Bank 6 1.5-V LVCMOS 1.2-V LVCMOS 3.0-V PCI / PCI-X 3.0-V PCI-X SSTL-2 Class I and II SSTL-18 Class I and II HSTL-18 Class I and II HSTL-15 Class I and II HSTL-12 Class I and II* LVDS RSDS mini-LVDS PPDS Bank 2 Bank 5 LVPECL Differential SSTL-2 Differential SSTL-18 Differential HSTL-18 Differential HSTL-15 PCI Express (using external PHY ) Serial RapidIO (using external PHY ) Bank 3 Bank 4 © 2009 Altera Corporation— Public *HSTL-12 Class II is only supported on top and bottom banks ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 24. Supported I/O Standards Single-Ended I/O Standards Max Usage 2.5-V SSTL Class I and II 167 MHz DDR SDRAM 1.8-V SSTL Class I and II 200 MHz DDR/DDR2 SDRAM 1.8-V/1.5V/1.2-V HSTL I and II 167 MHz QDR II SRAM 3.3-V PCI Compatible 66 MHz Embedded 3.3-V PCI-X 1.0 Compatible 100 MHz Embedded 3.3-V LVTTL 100 MHz* System Interface 3.0-V/2.5-V/1.8-V LVTTL 167 MHz System Interface 3.0-V*/2.5-V/1.8-V/1.5-V/1.2-V LVCMOS 167 MHz System Interface Differential I/O Standards Max Comment LVDS 875 Mbps High-Speed Serial RSDS/Mini-LVDS Transmission 440 Mbps High-Speed Serial LVPECL 500 MHz High-Speed Clocks PCI Express* 2.5 Gbps Per Channel Serial RapidIO* 3.125 Gbps Per Channel *Different from BA presentation *IP cores available, requires external PHY devices © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 25. Enhanced LVDS Buffers Dedicated LVDS Output Buffers on the left and right banks − Increased performance, 840 Mbps − No external resistors required Improved LVDS Input Buffers on all banks − Increased performance, 875 Mbps LVDS Rx Dedicated LVDS Tx PLL PLL 875 Mbps LVDS Tx PLL PLL 840 Mbps 90-110 Ohm External Resistor LVDS Rx Standard LVDS 875 Mbps LVDS Tx 640 Mbps © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 26. LVDS Pairs Reference LVDS Pairs Total With Without Package Device I/O Dedicated Output Buffers Dedicated Output Buffers Total 3C10 85 5 7 12 3C16 67 3 4 7 E144 3C25 65 4 2 6 3C16 143 17 18 35 3C25 131 17 14 31 Q240 3C40 111 7 7 14 3C10 173 21 36 57 3C16 151 19 24 43 F256 3C25 139 18 24 42 3C25 198 29 42 71 F324 3C40 178 22 27 49 3C16 329 66 62 128 3C40 314 58 56 114 3C55 310 61 62 123 F484 3C80 278 53 48 101 3C40 518 110 105 215 3C55 360 68 83 151 F780 3C80 412 77 92 169 © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 27. OCT With Calibration Output buffer impedance may vary slightly due to PVT With OCT Calibration, after configuration the output buffer impedance is automatically adjusted to match two external resisters (RUP & RDN), which are either 50 Ohms or 25 Ohms OCT Without Calibration OCT With Calibration VCCIO RUP 25 or 50 Ohm 25 or 50 Ohm RDN © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 28. Two additional I/O element registers Cyclone II Cyclone III Memory Performance Performance Increase DDR2 167 MHz 200 MHz 20% Improved Memory Performance and Flexibility © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 29. Slew Rate Control Available for all single ended I/O standards, with drive strengths of 8 mA or more (except 3.3-V LVTTL) Selectable on a pin by pin basis, using the Quartus II Software assignment editor Three settings: fast, medium, slow Default is fast © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 30. Cyclone III – The Right Balance The benefits of leading edge technology − 300 mm wafers − TSMC’s 65 nm low power process With 3.3-V I/O support − 3.3-V I/O driven from 3.3-V VCCIO, or − 3.3-V I/O driven from 3.0-V VCCIO As long as a few simple guidelines are followed − See AN 447 © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 31. Cyclone III External Memory Support Memory C6 (MHz) C7 (MHz) C8 (MHz) Availability Standards Col Row Col Row Col Row Quartus II I/O I/O I/O I/O I/O I/O software version DDR1 SDRAM 167 150 150 133 133 125 6.1 DDR2 SDRAM 200 167 167 150 150 133 6.1 QDRII SRAM 167 150 150 133 133 125 Q2 ’06 All numbers are minimum frequencies achievable; maximum frequencies pending characterization © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 32. ALTMEMPHY Physical Interface Soft megafunction included with all versions of the Quartus II software Self-calibrating at startup: − FPGA and memory device process changes − System uncertainties Periodic calibration during operation − Voltage and temperature changes Push button timing closure Better performance for fast and slow speed grade devices Cyclone III FPGA PLL Memory External Memory ALTMEM- / / Controller PHY Soft IP / Soft IP / Altera or Custom Autocalibrating PHY Memory Controller Minimizes Effort for Timing Closure © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 33. Timing Margins Are Shrinking Align Clock Capture Phase Here DQS DQ (First Data Valid) DQ (Last Data Valid) Data Valid at Memory Data Valid at FPGA Board Uncertainties Setup & Hold Time Internal Skew between DQS & DQ Total Timing Margin © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 34. Additional Uncertainties Temperature and voltage changes Process variations over time Memory vendor changes Board layout changes Data Valid at FPGA Setup & Hold Time Internal Skew between DQS & DQ Total Timing Margin © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 35. PLL Dynamic Phase Adjustment Dynamic adjustment of PLL phase setting Increase/decrease 1 step at a time − Step increments depend on PLL configuration inclk0 C0 Phasecounterselect[3:0] Phasedone Phaseupdown PLL Locked Phasestep © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 36. Calibration at Startup Write Training Pattern Phase Pin Set PLL Phase 0 15 30 45 60 … … … … 315 330 345 360 dq0 dq1 dq2 Read DQ and dq3 Compare to Training dq4 dq5 Pattern dq6 (repeat for all pins) dq7 Valid data window Set Optimum Clock Phase PHY adapts to your system! © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 37. Periodic Calibration Data capture and measurement of a representative mimic path delay every 128 ms − Path delay may change due to voltage and temperature changes − Assumption: Data Valid window drift due to temperature and voltage similar to delay change of representative path Non-Intrusive dynamic phase adjustment Data Valid Window Shifts Due to Measure delay Voltage and Temp. Changes changes 0 15 30……….......330 345 360 of mimic path T=0 T=1 Re-Set Optimum T=2 Clock Phase T=500 © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 38. Signal Integrity Series On-Chip Termination − Match output driver impedance to trace impedance − Calibrated on power up for process, temperature, and voltage variations Adjustable Slew Rates − Choose slower slew rates to lower simultaneously switching output (SSO) effects IBIS models for board simulation − Pending characterization © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 39. Flexible PCB Layout Interfaces available on all sides © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 40. Clock Networks & PLLs Overview Flexible clock management resources maximize system integration capabilities − PLL features Dynamic phase adjustments enable self-calibrating external memory controllers Reconfiguration enables display applications where the input frequency is unknown Generate up to 10 internal clocks and 2 external clocks from a single clock source 5 outputs per PLL combined with new IP enables x72 DDR2 interfaces using just 1 PLL − Unused clock networks are turned off to minimize power consumption − Global clock networks double as low skew, high fanout control signals © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 41. Clock Networks & PLLs Overview Up to 20 Global Clocks Per Device Dual purpose as high fan out control signals 4 GCLK PLL 3 Mux PLL 2 GCLK [14:10] 4 GCLK GCLK 4 Mux GCLK [9:5] Mux GCLK [0:4] GCLK [15:19] GCLK PLL 1 PLL 4 Mux © 2009 Altera Corporation— Public 4 ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 42. Cyclone III PLL Functions Clock Multiplication & Division Clock Synthesis Phase Alignment & Phase Shift Output Clock C0 Pin Switchover Clock Inputs C0 [1..0] N Global PFD CP LF VCO C1 Clock C[4..0] Network C2 M C3 Feedback C4 Reconfigurable in user mode © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 43. Cascading PLLs Supply a clk to other devices Cyclone III PLL Output Pin 5 55Clock Clock GCLK Networks MUX Networks per PLL per PLL Supply a Cascade through global clock network clk to other devices Cyclone III PLL 5 Up to 10 internal & 2 external clocks GCLK from 1 clock source MUX Finer resolution multiplication/division & phase shifting Clean up low performance and noisy external clock sources © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 44. PLL Dynamic Phase Adjustment Dynamic adjustment of PLL phase setting Increase/decrease 1 step at a time − Step increments depend on PLL configuration inclk0 C0 Phasecounterselect[3:0] Phasedone Phaseupdown PLL Locked Phasestep Enables Auto-Calibrating PHY for External Memory Interfaces © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 45. Clock Switch Over Automatically switch from 1 clock to another in the event a clock stops Manually switch from 1 clock source to another Clock Switch Over Control Clock pins or CLK Cyclone III GCLK MUX PLL network © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 46. Compensation Modes PLL Mode Description Source Synchronous Clock-to-data relationship at input pin (setup/hold) maintained at the IOE register No Compensation No compensation for best jitter performance Normal Input clock delay fully compensated for alignment with clock at IOE or core register Zero Delay Buffer Input clock aligned with dedicated external clock output © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 47. PLL Feature Comparison Cyclone II Cyclone III Cyclone III Advantages Number of PLLs 2–4 2–4 Same Up to 8 additional global clocks Outputs per PLL 3 5 driven by PLLs Number of Global Combine required clock signals 8 – 16 10 – 20 Clocks into fewer PLLs Min, Max Broader range improves 10 – 400 5 – 440 Frequency (MHz) system flexibility Dynamic Frequency Improve system performance No Reconfiguration and Phase by removing device downtime Cascadable No Yes Increase PCB routing flexibility © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 48. Cyclone III Configuration Overview Comprehensive configuration and remote system upgrade solution − Simple, easy to use, & low cost − Available with option does not require external host − Altera serial configuration devices available for all densities Commodity Flash configuration − Free configuration solution if extra memory is available in a parallel Flash already on board Cyclone III serial & parallel Flash loader − In system programming of serial and parallel configuration devices through Cyclone III JTAG port © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 49. What’s New in Cyclone III Configuration? Active Parallel − Configuration with commodity parallel Flash already on board without a separate controller − First time for any Altera FPGA Remote System − No external host required Upgrade − Available with Active Serial or Active Parallel configuration mode Fast-On − Option to reduce maximum POR time to 9ms to meet automotive 100 ms “wake up” time requirements Fast Passive − Fastest configuration option Parallel − Allows 100 MHz clock with x8 data width © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 50. Configuration Mode Overview Programming Mode Cyclone III Cyclone I & II Stratix III Stratix II Stratix Active Serial Active Parallel Passive Serial Fast Passive Parallel JTAG Remote Update First time for Cyclone Family FPGAs Active: Controller in FPGA & Clock is from FPGA Passive: Controller outside of FPGA & Clock is supplied from outside controller © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 51. Understanding Configuration Timing Vcc Vcc ramp POR Time Configuration Time Cyclone III up time Fast: 3 to 9 ms Depends on configuration mode, in user mode Slow: 50 to 200 ms clock frequency & device density operation “Wake-up” Time Total time before Cyclone III is operational from power up Application with fast “Wake-up” time specification needs to utilize fast POR time and fast configuration modes POR time and configuration time user configurable with mode select pins(MSEL3..0) Fast POR option requires fast* Vcc ramp * Vcc ramp time needs to be faster than POR Time. Specification will be determined after characterization © 2009 Only major timings are shown above ** Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 52. Configuration Mode Comparison Additional # # of Data Configuration Ease of Config Remote Chips Cyclone III Compre- Mode Usea Speedb Required Pinsc ssion Upgrade Active Serial 1 292ms 1 4 Active Parallel 2 48ms 1 47 Passive Serial 3 117ms 2 2 Fast Passive Parallel 4 38ms 2 9 JTAGd 5 210ms 2 4 a. Ease of Use: Subjective rating based on number of chips, number of I/Os required, and additional knowledge requirement (1 being the easiest solution) b. Benchmark based on 3C80 at maximum frequency for each mode c. Pin count excluding MSEL3..0, nStatus, CONF_Done, nCE, and nCEO d.2009 Altera Corporation— Public © JTAG using an external controller and a Flash device ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 53. Configuration File Size & Time File Size* Compressed AS** Device AP (ms) FPP (ms) (Mbits) Size (Mbits) (ms) EP3C5 3.3 1.9 49 5 4 EP3C10 3.3 1.9 49 5 4 EP3C16 4.3 2.4 63 7 6 EP3C25 6.2 3.4 90 10 8 EP3C40 10.0 5.6 146 16 13 EP3C55 15.3 8.5 222 25 20 EP3C80 20.0 11.1 292 33 26 EP3C120 29.1 16.2 424 48 38 Clock Frequency for Active Serial (AS): 40Mhz***, Active Parallel (AP): 40Mhz***, Fast Passive Parallel (FPP): 100Mhz * Preliminary information ** Configuration Time using compressed data for AS mode *** Max/Typ/Min = 40Mhz/30Mhz/20Mhz, configuration times can be up to 2X longer than values in table for AS © and Altera Corporation— Public 2009 AP modes ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 54. Programming Flash in System Program or examine Flash device from Quartus II programmer window − Cyclone III works as a Flash programmer with Flash loader SOF − Quartus II downloads SOF automatically & programs Flash Eliminates additional hardware and software for on board Flash programming − Unique tool for Altera USB Flash Programmer* JTAG Parallel Flash Or Serial Configuration Cyclone III Device Flash Loader SOF USB User board © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. * ByteBlaster & EthernetBlaster works identically
- 55. Cyclone III Remote System Upgrade Allows multiple new application images in addition to factory image Built in recovery circuitry loads factory image if upgrade image fails to load No external host or processor required Customize with Nios II or user-defined control logic © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 56. Remote System Upgrade Utilize in application where time to market is critical − Ship initial product with minimum feature set − Remotely upgrade system without system being down due to upgrade failure − Can be used for bug fix and/or upgrade application Configuration Device Cyclone III 2 Application n Remote Source Store Send Update Update Application 1 Control Recovery 1 Logic Circuitry Factory Application Update 3 Cyclone III Device © 2009 Altera Corporation— Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Editor's Notes
- #3: Cyclone III is the latest in a long line of low-cost products from Altera. We continue not only to drive prices lower and continue our commitment to low-cost FPGAs, but also to add more functionality and features to every successive generation. In Cyclone III, we chose to lower power by 50% and increase the density to 120KLEs. This allows you to do more with less.
- #4: This slide shows the key features of the Cyclone III architecture and is a blueprint for the features that will be highlighted in the rest of this presentation. While this is a 65-nm low power process, the core voltage is 1.2V The highest density device contains 4 Mbits of RAM, divided into 9K blocks that were optimized for video buffering and other RAM intensive applications. In the largest device, there are 432 of these blocks that can be configured as single port, dual port, or true dual port RAM or ROM. The devices also support both parallel and serial configuration and offer a new feature that eliminates the need for an external microcontroller if you wish to do remote system upgrades. Because we’re adding new applications to the low cost market that are higher in density and require more RAM and DSP, we are also upgrading our PLLs to be a Stratix-class PLL. These new PLLs are dynamically reconfigurable in system, and feature up to 5 outputs per PLL. The larger devices have 4 PLLs while the two smaller devices have 2 PLLs each.
- #5: Form Factors, Cost Pressures, Doing More with Less Density, Memory, Multipliers, Nios II, Auto PHY Longevity Remote System Upgrade, Obselence proof.
- #6: You can further reduce the power consumption of your Cyclone design by using the power aware design flow in our free quartus II software. By simply turning on the feature, you can reduce dynamic power consumption by an additional 25%. The place-and-route engine will automatically examine your design to find opportunities to squeeze power out of the design – you don’t need to tweak anything by hand here.
- #8: Cyclone III devices offer a huge advantage in raw processing power over common DSP processors operating at much higher frequencies. For this comparison, processing power is measured as Giga Multiplies/s = Clock Frequency * # of 16x16 Hardware Multiplies Cyclone III devices actually have 18 x 18 multipliers but 16 x 16 multipliers are used for comparison to popular DSP processors. You have to explain this slide in context, it is not a traditional benchmark: Gigamultiplies per second is the theoretical maximum number of 16X16 multiply operations that can be done in a second if all multipliers were used at full bandwidth on the DSP device or the FPGA. For example, the TI DSP device has 2 multiply units that can run in parallel at 1GHz. Cyclone III devices have up to 288 multipliers that operate in parallel at up to 260 MHz. In practical applications you will not reach or require these utilization levels with the DSP devices or the FPGA. What this data shows is that even low-cost FPGAs now have a great deal of DSP horsepower and FPGAs offer benefits in applications requiring a lot of parallel multiplication operations such as a multi-channel applications including video surveillance systems, communications systems, and other spaces. Cyclone III devices can be used to complement DSP processing deficiencies or even replace 1 or more DSP processors entirely. The net benefit is to improve system performance, lower system cost, reduce board space, and/lower lower system thermal power dissipation. Note: Giga Multiplies/s = Clock Frequency * # of 16x16 Hardware Multiplies
- #9: If you look a little closer at the larger memory blocks, they enable Performance enhancements by reducing the need to cascade memory blocks Higher memory to logic ratios to allow users to select a smaller and lower cost device for memory intensive applications such as packet processing or processor code storage Better memory to multiplier ratio for video line buffers and to support DSP intensive applications such as general video and image processing Memory bandwidth is defined as Memory Blocks x ports (2 per) x width of ports (36b) x Frequency (260MHz) If you now compare CIII vs. CII: Cyclone III Blocks are increased Frequency increased And Port width is same leading to a significant increase in memory bandwidth.
- #10: In order to support the dense logic structure of Cyclone III FPGAs, these devices have either 10 or 20 global clocks, depending on device density. These clock lines are powered down if you are not using them to save power. We also completely rearchitected the global clock mux, to enable many of the new PLL features we are adding, as well as to simply timing closure on memory interfaces. The PLLs on Cyclone III are low jitter, very flexible PLLs. Each offers a up to 5 outputs per PLL. We’ve also increased the frequency range to as low as 5 MHz and as high as 440 MHz clock input signals. You can also dynamically change the frequency and phase of your PLL while the system is running if you want to switch clock frequencies without powering down your system. And finally, we’ve added cascading, which allows you to cascade PLLs together to get even more granularity on the clock frequency generated.
- #11: Every Cyclone III device has 8 banks of IO. 3C5 all the way up to a 3C120. Each of these banks can support any IO standard, but each bank has to be powered at a specific voltage. The voltages we support range from 1.2 up to 3.3V. We support a variety of IO standards on Cyclone III. We added RSDS, Mini-LVDS and PPDS to support the display market. Cyclone III devices support DDR2 up to 200 MHz, which means you can run 400 Mbps DDR2 interfaces on a low cost FPGA. These memory interfaces are also designed using our TimeQuest timing analyzer which allows you to, with the use of an pre-built block, allow this memory interface to compensate dynamically for process, voltage and temperature changes in system. There is documentation on Altera.com on how to do this.
- #12: With Cyclone III we’ve re-architected the memory interface design. Let’s face it, getting high speed memories to talk to FPGAs is pretty challenging, and it gets even trickier at 65nm.. The way we do this right now as an industry goes something like this. You can either buy a memory interface from a supplier, or you can roll your own. In the first case, you may not get the exact logic backend that you want, meaning it either has features you don’t want to use up your logic for, or it doesn’t have features that you need. In the second case, you’ll get exactly the right feature set, but you are going to invest lab time to get the timing to work properly – that means you are building timing constraints that are architecture, device, package and speed grade specifically – not the most levaragable engineering investment. So, in this round, we’ve made this decision really easy. We’ve split the memory controller in half. In this block diagram, the light blue “PHY IP” you get for free. It is the device-package-speed grade specific bit. The dark blue block is the memory controller logic. You can buy it or build it. Your choice. Either way, you’ll get the job done a lot faster than before.
- #13: Using the remote system upgrade feature you can directly connect a Cyclone III device to serial or parallel flash configuration device. The configuration device can be loaded with a factory image and one or more application images. At power up the known good factory image is loaded and the part goes into user mode. At some time in the future the users application can detect a new application image and trigger the device to reconfigure with the new application image. If the configuration finishes without error the device goes into user mode with the new image. If there is a problem during configuration the configuration controller will automatically revert back to loading the known good factory image so there is zero down time.
- #14: Note that our product strategy is more than just about the silicon. Productivity oriented development tools, IP and development kits are key to Altera’s ability to make customers successful.
- #15: The Cyclone III architecture will also support the Nios II embedded soft processor. The Nios II processor can achieve as much as 160 DMIPS of performance, and allows the user to build custom instructions as well as stitch together a custom set of peripherals using the Avalon interconnect fabric. Avalon is not a bus, it’s an interconnect, so it doesn’t introduce potential latency issues, as other on-chip bus solutions can. Over 15,000 Licensees World Wide (Less than 2.5% of a 3C25 device) Royalty-free
- #16: And now, finally, here is a look at the Cyclone III device family. It has 8 members ranging from 5 to 120 thousand logic elements. It will support 3 speed grades on each device, where 6 is fast and 8 is slow. The performance delta between speed grades is typically around 15-20% in core fmax, with IO performance changing in less generic ways because their performance is usually based on a standard like PCI. So it would change from 200 to 167MHz, as opposed to a percentage. This is the most aggressive low cost family plan we’ve ever done, and we’re excited to be able to ship the first 65nm low cost FPGA not only in ES but in production quantities very soon!
- #17: Pin Counts for M164 not yet finalized. These are estimates
- #21: Cyclone III devices include an abundance of embedded multipliers for mathematically intensive DSP applications. Having an abundance of multipliers operating in parallel offers FPGAs a unique advantages over DSP processors for video processing in broadcast and medical imaging applications. FPGAs also excel at lowering system costs for multi-channel applications such as video surveillance or communications systems. The Maximum performance of the Cyclone III embedded multiplier is increased to 260 MHz with support for one 18 bit or two 9 bit multipliers per block. 18x18 multipliers can also be cascaded to support 36x36 multiplication. The DSP block supports the following features: A base cell containing an 18bx18b multiplier features - One full-precision (36 bits) 18bx18b multiplier output Capability to split the base cell containing one 18bx18b multiplier into a cell containing two 9bx9b multipliers - Two full-precision (18 bits each) 9bx9b multiplier outputs Input and output registers to improve block speed. - The DSP block is targeted for 260MHz 18bx18b multiplication with both registers engaged and at the fastest speed grade. Input register banks can be set/bypassed in 9bit chunks. Similarly, the output register banks can be set/bypassed in 18bit chunks. 2 dynamic input signals (SIGNX and SIGNY) have input registers that can be set/bypassed independently of the data register banks. Differences between Cyclone III DSP and the Stratix III DSP block: Programmable inversion added for SIGNX and SIGNY signals
- #22: A key area of focus for the Cyclone III device family was optimizing memory to logic ratios for key high-volume, cost sensitive applications. Based on extensive customer design analysis and simulation the on-chip blocks in Cyclone III devices have been increased to 9Kbytes including parity bits. The performance was also increased from 216MHz to 260MHz. Other features were added to increase flexibility and ease of use of the feature. For example, Cyclone III adds the ability to provide new data or old data when performing a read during write operation in Dual-port mode. Quartus II software can take advantage of the extra clock enables to reduce power by shutting off parts of the memory block when not in use.
- #23: First, all 8 banks can interface to any I/O standard or memory. For example, restrictions on DQS signal placement has been largely removed. Certain banks are still optimized for highest performance for memory interfaces and LVDS communication. For example, Top and bottom banks are optimized for memory interface performance Left and right banks are optimized for LVDS performance 2 additional registers in the I/O cell increase DDR interface performance by improving the Write margin. Dedicated differential output buffers eliminate the need for external resistors for RSDS transmission in display applications. Cyclone III allows selection of 25ohm or 50ohm series termination values. This feature was not available in Cyclone II OCT. Adjustable slew rates can improve signal integrity by slowing down edge rates on non-performance critical I/O pins.
- #25: Cyclone III I/O and memory interfaces are designed to support a broad range of general purpose and specific end market applications. One thing to note, to the best of our knowledge, only Cyclone III devices support 3.3V I/O in a 65 nm low-cost FPGA device. Additional notes: Support is limited for up to 6 ma drive strengths which covers a majority of user applications. For 3.3V PCI support Cyclone III offers a 3.0V I/O setting to support the higher required drive strengths required for PCI and remain compatible with PCI voltage swing requirements. Also note that LVDS performance has been increased to a maximum of 875 Mbps performance. PCI Express and Serial rapid I/O standards continue to be supported via the use of external PHY devices and easy to use IP cores available from Altera and partners.
- #32: Customers advised to use 333MHz DDR2 for 200MHz performance until characterization data is available to remove this restriction. 3 major memory supplies confirmed that no price premiums are expected for 333MHz memory over 200 MHz memory in 2008 and forward time frame; see backup slide for more information.
- #33: Cyclone III devices support SDRAM, DDR/DDR2, and QDR/QDR II external memory interfaces. Autocalibrated PHY is supported by TimeQuest and Cyclone III starting with Quartus II v6.1. To increase flexibility Cyclone III has separated the Controller and PHY IP, which provides the customer with more flexibility to self-design the Controller (in C). Altera can provide the Controller as well. The I/O PHY is provided free with Quartus II software as a MegaWizard function. The new PHY eases timing closure requirements and eliminates PVT variations using an autocalibration feature. This feature recalibrates the optimal sampling window ever 128 ms. To ease PCB layout Cyclone III devices largely reduces constraints on DQS signal pin placements. Another enhancement is that DDR/II x32 mode is supported using only 1 DQS pin which is key for newer display application designs. Cyclone III memory interface support schedule for calibrated, non-DQS: DDR/DDR2 will be supported in quartus II v6.1 QDR II/SRAM will be supported in Quartus II v7.1
- #42: Dedicated clock pins can directly feed the global clock muxes or the PLLs.
- #43: PLL functions include clock multiplication and division, clock synthesis of multiple clcoks from a single clock source, and phase alignment or phase shifting of clocks. A major enhancement to the Cyclone III PLL is the ability to store addiotnal PLL configurations in on chip memory and reconfigure the PLL to a different setting. You can also dynamically adjust the phase shift in system.
- #44: In previous generations of the Cyclone series devices, if you wanted to cascade 2 PLLs you would have to route an output pin off chip and route it on the PCB to another PLL. With Cyclone III you can directly cascade PLLs without going off chip which conserves IO pins and makes PCB routing and layout easier.
- #45: Additional control signals on the Cyclone III PLL enable users to dynamicaly adjust the phase shift one step at time without reconfiguring the PLL. The smallest step possible is 96 ps but the step resolution depends on the current configuration of the PLL. This features enables the autocalibration feature for Cyclone III external memory interfaces.
- #48: To summarize the Cyclone III clocking and PLL advantages over Cyclone II: Outputs per PLL are increased from 3-5 to gain 8 additional PLL generated clocks. Total number of clocks is increased from 8-16 to 10-20 clocks per device. Frequency extended on lower end to support low-cost clocks and on higher end for higher performance. PLLs can be dynamically configured with values stored in the M9K blocks. Enables auto-calibration feature on DDR interfaces for higher performance and easier timing closure process. Cascading PLLs saves I/Os and eases PCB routing by eliminating the need to bring the clock off the chip and then back onto the device. Cascading clocks through multiple PLLs also reduces jitter.
- #49: Cyclone III many different configuration options to meet all customers’ need. Altera is unique to offer configuration device to all of its FPGAs
- #50: Remote system upgrade is same as Stratix series FPGAs. It is the first time in Cyclone series FPGA. Fast-On is similar to Cyclone IIA but it is standard option for all Cyclone III
- #51: Remote update was always possible with external control but new FPGAs are available without external host.
- #55: Xilinx’s solution is limited to a reference design. So, customer needs to use MicroBlaze and reference design to make equivalent design Quartus II v6.1 has this feature for serial flash. Parallel flash version will be available in Quartus II v7.1