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Logic Mind Technologies
Vijayangar (Near Maruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Data Encoding Techniques for Reducing
Energyb Consumption in Network-on-Chip
Abstract—As technology shrinks, the power dissipated by the links of a network-
on-chip (NoC) starts to compete with the power dissipated by the other elements of
the communication subsystem, namely, the routers and the network interfaces
(NIs). In this paper, we present a set of data encoding schemes aimed at reducing
the power dissipated by the links of an NoC. The proposed schemes are general
and transparent with respect to the underlying NoC fabric (i.e., their application
does not require any modification of the routers and link architecture).
Experiments carried out on both synthetic and real traffic scenarios show the
effectiveness of the proposed schemes, which allow to save up to 51% of power
dissipation and 14% of energy consumption without any significant performance
degradation and with less than 15% area overhead in the NI.
SOFTWARE REQUIREMENT:
 ModelSim6.4c.
 Xilinx 9.1/13.2.
HARDWARE REQUIREMENT:
 FPGA Spartan 3.
PROJECT FLOW:
First Review:
Literature Survey
Paper Explanation
Design of Project
Project Enhancement explanation
Second Review:
Implementing 40% of Base Paper
Third Review
Implementing Remaining 60% of Base Paper with Future Enhancement (Modification)
For More Details please contact
Logic Mind Technologies
Vijayangar (NearMaruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Mail: logicmindtech@gmail.com

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Data encoding techniques for reducing energyb consumption in network on-chip

  • 1. Logic Mind Technologies Vijayangar (Near Maruthi Medicals), Bangalore-40 Ph: 8123668124 // 8123668066 Data Encoding Techniques for Reducing Energyb Consumption in Network-on-Chip Abstract—As technology shrinks, the power dissipated by the links of a network- on-chip (NoC) starts to compete with the power dissipated by the other elements of the communication subsystem, namely, the routers and the network interfaces (NIs). In this paper, we present a set of data encoding schemes aimed at reducing the power dissipated by the links of an NoC. The proposed schemes are general and transparent with respect to the underlying NoC fabric (i.e., their application does not require any modification of the routers and link architecture). Experiments carried out on both synthetic and real traffic scenarios show the effectiveness of the proposed schemes, which allow to save up to 51% of power dissipation and 14% of energy consumption without any significant performance degradation and with less than 15% area overhead in the NI.
  • 2. SOFTWARE REQUIREMENT:  ModelSim6.4c.  Xilinx 9.1/13.2. HARDWARE REQUIREMENT:  FPGA Spartan 3. PROJECT FLOW: First Review: Literature Survey Paper Explanation Design of Project Project Enhancement explanation Second Review: Implementing 40% of Base Paper Third Review Implementing Remaining 60% of Base Paper with Future Enhancement (Modification) For More Details please contact Logic Mind Technologies Vijayangar (NearMaruthi Medicals), Bangalore-40 Ph: 8123668124 // 8123668066 Mail: logicmindtech@gmail.com