Data-Centric Parallel Programming

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Data-Centric Parallel Programming
Torsten Hoefler, Keynote at AsHES @ IPDPS’19, Rio, Brazil
Alexandros Ziogas, Tal Ben-Nun, Guillermo Indalecio, Timo Schneider, Mathieu Luisier, and Johannes de Fine Licht
and the whole DAPP team @ SPCL
https://eurompi19.inf.ethz.ch

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2
Changing hardware constraints and the physics of computing
[1]: Marc Horowitz, Computing’s Energy Problem (and what we can do about it), ISSC 2014, plenary
[2]: Moore: Landauer Limit Demonstrated, IEEE Spectrum 2012
130nm
90nm
65nm
45nm
32nm
22nm
14nm
10nm
0.9 V [1]
32-bit FP ADD: 0.9 pJ
32-bit FP MUL: 3.2 pJ
2x32 bit from L1 (8 kiB): 10 pJ
2x32 bit from L2 (1 MiB): 100 pJ
2x32 bit from DRAM: 1.3 nJ
…
Three Ls of modern computing:
How to address locality challenges on standard architectures and programming?
D. Unat et al.: “Trends in Data Locality Abstractions for HPC Systems”
IEEE Transactions on Parallel and Distributed Systems (TPDS). Vol 28, Nr. 10, IEEE, Oct. 2017

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3
Control in Load-store vs. Dataflow
Memory
Cache
RegistersControl
x=a+b
ld a, r1
ALU
ald b, r2 badd r1, r2
ba
x
bast r1, x Memory
+
c d y
y=(a+b)*(c+d)
a b
+
x
a b c d
a+b c+d
y
Turing Award 1977 (Backus): "Surely there must be a less primitive
way of making big changes in the store than pushing vast numbers
of words back and forth through the von Neumann bottleneck."
Load-store (“von Neumann”)
Energy per instruction: 70pJ
Source: Mark Horowitz, ISSC’14
Energy per operation: 1-3pJ
Static Dataflow (“non von Neumann”)
Very Low High

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Still Lower
Control Locality
4
Single Instruction Multiple Data/Threads (SIMD - Vector CPU, SIMT - GPU)
Memory
Cache
RegistersControl
ALUALU
ALUALU
ALUALU
ALUALU
ALUALU
45nm, 0.9 V [1]
Random Access SRAM:
8 kiB: 10 pJ
32 kiB: 20 pJ
1 MiB: 100 pJ
Memory
+
c d ya b
+
x
a b c d
45nm, 0.9 V [1]
Single R/W registers:
32 bit: 0.1 pJ
[1]: Marc Horowitz, Computing’s Energy Problem (and what we can do about it), ISSC 2014, plenary
High Performance Computing really
became a data management challenge

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5
Data movement will dominate everything!
Source: Fatollahi-Fard et al.
 “In future microprocessors, the energy expended for data movement will have a critical effect on
achievable performance.”
 “… movement consumes almost 58 watts with hardly any energy budget left for computation.”
 “…the cost of data movement starts to dominate.”
 “…data movement over these networks must be limited to conserve energy…”
 the phrase “data movement” appears 18 times on 11 pages (usually in concerning contexts)!
 “Efficient data orchestration will increasingly be critical, evolving to more efficient memory
hierarchies and new types of interconnect tailored for locality and that depend on
sophisticated software to place computation and data so as to minimize data movement.”
Source: NVIDIA
Source: Kogge, Shalf

spcl.inf.ethz.ch
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 Well, to a good approximation how we programmed yesterday
 Or last year?
 Or four decades ago?
 Control-centric programming
 Worry about operation counts (flop/s is the metric, isn’t it?)
 Data movement is at best implicit (or invisible/ignored)
 Legion [1] is taking a good direction towards data-centric
 Tasking relies on data placement but not really dependencies (not visible to tool-chain)
 But it is still control-centric in the tasks – not (performance) portable between devices!
 Let’s go a step further towards an explicitly data-centric viewpoint
 For performance engineers at least!
6
“Sophisticated software”: How do we program today?
Backus ‘77: “The assignment statement
is the von Neumann bottleneck of programming
languages and keeps us thinking in word-at-a-time
terms in much the same way the computer’s
bottleneck does.”
[1]: Bauer et al.: “Legion: expressing locality and independence with logical regions”, SC12, 2012

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7
Performance Portability with DataCentric (DaCe) Parallel Programming
Preprint (arXiv): Ben-Nun, de Fine Licht, Ziogas, TH: Stateful Dataflow Multigraphs: A Data-Centric Model for High-Performance Parallel Programs
SystemDomain Scientist Performance Engineer
High-Level Program
Data-Centric Intermediate
Representation (SDFG, §3)
𝜕𝑢
𝜕𝑡
− 𝛼𝛻2 𝑢 = 0
Problem Formulation
FPGA Modules
CPU Binary
Runtime
Hardware
Information
Graph Transformations
(API, Interactive, §4)
SDFG Compiler
Transformed
Dataflow
Performance
Results
Thin Runtime
Infrastructure
GPU Binary
Python /
NumPy
𝑳 𝑹
*
*
*
*
*
*
TensorFlow
DSLs
MATLAB
SDFG Builder API

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8
DAPP – Data Centric Programming Concepts
• Store volatile (buffers, queues, RAM) and
nonvolatile (files, I/O) information
• Can be sources or sinks of data
• Stateless functions that perform computations at
any granularity
• Data access only through ports
• Data flowing between containers and tasklets/ports
• Implemented as access, copies, streaming, …
• Map scopes provide parallelism
• States constrain parallelism outside of datatflow
Data Containers Computation
Data Movement / Dependencies Parallelism and States

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A first example in DaCe Python

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DIODE User Interface
10
Source Code Transformations
SDFG
(malleable)
SDFGGenerated Code Performance

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11
Performance for matrix multiplication on x86
SDFG
Naïve

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SDFG
MapReduceFusionNaïve

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SDFG
LoopReorder

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SDFG
BlockTiling
LoopReorder

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RegisterTiling
BlockTiling
LoopReorder

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LocalStorage
RegisterTiling
BlockTiling
LoopReorder

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PromoteTransient
LocalStorage
RegisterTiling
BlockTiling
LoopReorder

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Intel MKL
OpenBLAS
25% difference
DAPP
With more tuning: 98.6% of MKLBut do we really care about MMM on x86 CPUs?

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Hardware Mapping: Load/Store Architectures
 Recursive code generation (C++, CUDA)
 Control flow: Construct detection and gotos
 Parallelism
 Multi-core CPU: OpenMP, atomics, and threads
 GPU: CUDA kernels and streams
 Connected components run concurrently
 Memory and interaction with accelerators
 Array-array edges create intra-/inter-device copies
 Memory access validation on compilation
 Automatic CPU SDFG to GPU transformation
 Tasklet code immutable
19

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Hardware Mapping: Pipelined Architectures
 Module generation with HDL and HLS
 Integration with Xilinx SDAccel
 Nested SDFGs become FPGA state machines
 Parallelism
 Exploiting temporal locality: Pipelines
 Exploiting spatial locality: Vectorization, replication
 Replication
 Enables parametric systolic array generation
 Memory access
 Burst memory access, vectorization
 Streams for inter-PE communication
20

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Performance (Portability) Evaluation
 Three platforms:
 Intel Xeon E5-2650 v4 CPU (2.20 GHz, no HT)
 Tesla P100 GPU
 Xilinx VCU1525 hosting an XCVU9P FPGA
 Compilers and frameworks:
 Compilers:
GCC 8.2.0
Clang 6.0
icc 18.0.3
 Polyhedral optimizing compilers:
Polly 6.0
Pluto 0.11.4
PPCG 0.8
 GPU and FPGA compilers:
CUDA nvcc 9.2
Xilinx SDAccel 2018.2
 Frameworks and optimized libraries:
HPX
Halide
Intel MKL
NVIDIA CUBLAS, CUSPARSE, CUTLASS
NVIDIA CUB
21

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Performance Evaluation: Fundamental Kernels (CPU)
 Database Query: roughly 50% of a 67,108,864 column
 Matrix Multiplication (MM): 2048x2048x2048
 Histogram: 8192x8192
 Jacobi stencil: 2048x2048 for T=1024
 Sparse Matrix-Vector Multiplication (SpMV): 8192x8192 CSR matrix (nnz=33,554,432)
22
99.9% of MKL8.12x faster 98.6% of MKL 2.5x faster 82.7% of Halide

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Performance Evaluation: Fundamental Kernels (GPU, FPGA)
23
GPU
FPGA 309,000x
19.5x of Spatial
90% of CUTLASS

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Performance Evaluation: Polybench (CPU)
 Polyhedral benchmark with 30 applications
 Without any transformations, achieves 1.43x (geometric mean) over
general-purpose compilers
24

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Performance Evaluation: Polybench (GPU, FPGA)
 Automatically transformed from CPU code
25
GPU
(1.12x geomean speedup)
FPGA
The first full set of placed-and-routed Polybench
11.8x

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Case Study: Parallel Breadth-First Search
 Compared with Galois and Gluon
 State-of-the-art graph processing frameworks on CPU
 Graphs:
 Road maps: USA, OSM-Europe
 Social networks: Twitter, LiveJournal
 Synthetic: Kronecker Graphs
26
Performance portability – fine, but who cares about microbenchmarks?

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27
Remember the promise of DAPP – on to a real application!
SystemDomain Scientist Performance Engineer
High-Level Program
Data-Centric Intermediate
Representation (SDFG, §3)
𝜕𝑢
𝜕𝑡
− 𝛼𝛻2 𝑢 = 0
Problem Formulation
FPGA Modules
CPU Binary
Runtime
Hardware
Information
Graph Transformations
(API, Interactive, §4)
SDFG Compiler
Transformed
Dataflow
Performance
Results
Thin Runtime
Infrastructure
GPU Binary
Python /
NumPy
𝑳 𝑹
*
*
*
*
*
*
TensorFlow
DSLs
MATLAB
SDFG Builder API

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28
Next-Generation Transistors need to be cooler – addressing self-heating

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 OMEN Code (Luisier et al., Gordon Bell award finalist 2011 and 2015)
 90k SLOC, C, C++, CUDA, MPI, OpenMP, …
29
Quantum Transport Simulations with OMEN
Electrons 𝑮 𝑬, 𝒌 𝒛 Phonons 𝑫 𝝎, 𝒒 𝒛
GF
SSE
SSE
Σ 𝐺 𝐸 + ℏ𝜔, 𝑘 𝑧 − 𝑞 𝑧 𝐷 𝜔, 𝑞 𝑧 𝐸, 𝑘 𝑧
Π 𝐺 𝐸, 𝑘 𝑧 𝐺 𝐸 + ℏ𝜔, 𝑘 𝑧 + 𝑞 𝑧 𝜔, 𝑞 𝑧
𝐸 ⋅ 𝑆 − 𝐻 − Σ 𝑅
⋅ 𝐺 𝑅
= 𝐼
𝐺<
= 𝐺 𝑅
⋅ Σ<
⋅ 𝐺 𝐴
𝜔2
− Φ − Π 𝑅
⋅ 𝐷 𝑅
= 𝐼
𝐷<
= 𝐷 𝑅
⋅ Π<
⋅ 𝐷 𝐴
NEGF

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30
All of OMEN (90k SLOC) in a single SDFG – (collapsed) tasklets contain more SDFGs
𝐻
𝑘 𝑧, 𝐸
RGF
Σ≷
convergence
𝐺≷
Φ
𝑞 𝑧, 𝜔
RGF
Π≷
𝐷≷
𝑏
𝛻𝐻
𝑘 𝑧, 𝐸, 𝑞 𝑧, 𝜔, 𝑎, 𝑏
SSE
Π≷
G≷
Σ≷
D≷
Not 𝑏
𝑏
GF
SSE
𝑖++𝑖=0 𝑞 𝑧, 𝜔𝑘 𝑧, 𝐸
𝐻[0:𝑁𝑘 𝑧
] Φ[0:𝑁𝑞 𝑧
]Σ≷
[0:𝑁𝑘 𝑧
,0:𝑁𝐸]
𝐼𝑒 𝐼 𝜙
Π≷
[0:𝑁𝑞 𝑧
,
1:𝑁 𝜔]
𝐻[𝑘 𝑧] Φ[𝑞 𝑧]Σ≷
[𝑘 𝑧,E] Π≷
[𝑞 𝑧,𝜔]
𝐺≷
[𝑘 𝑧,E] 𝐷≷
[𝑞 𝑧,𝜔]𝐼Φ (CR: Sum)
𝐼Φ (CR: Sum)𝐼e (CR: Sum)
𝐼e (CR: Sum)
𝐷≷
[0:N 𝑞 𝑧
,
1:N 𝜔]
G≷
[0:𝑁𝑘 𝑧
,0:𝑁𝐸]
𝛻𝐻 G≷
D≷
Π≷
(CR: Sum)Σ≷
(CR: Sum)
Σ≷
[…]
(CR: Sum)
Π≷
[…]
(CR: Sum)
𝛻𝐻[…] G≷
[…] D≷
[…]
𝑘 𝑧, 𝐸, 𝑞 𝑧, 𝜔, 𝑎, 𝑏
𝐼e 𝐼Φ
𝑏

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31
Zooming into SSE (large share of the runtime)
DaCe
Transform
Between 100-250x less communication at scale! (from PB to TB)

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32
Additional interesting performance insights
Python is slow! Ok, we knew that – but compiled can be fast!
Piz Daint single node (P100)
cuBLAS can be very inefficient (well, unless you floptimize)
Basic operation in SSE (many very small MMMs)
5k atoms
Piz Daint Summit

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33
10,240 atoms on 27,360 V100 GPUs (full-scale Summit)
- 56 Pflop/s with I/O (28% peak)
Already ~100x speedup on 25%
of Summit – the original OMEN
does not scale further!
Communication time reduced
by 417x on Piz Daint!
Volume on full-scale Summit
from 12 PB/iter  87 TB/iter

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34
An example of fine-grained data-centric optimization (i.e., how to vectorize)

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35
Overview and wrap-up
This project has received funding from the European Research Council (ERC) under grant agreement "DAPP (PI: T. Hoefler)".

Data-Centric Parallel Programming

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