cplds
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This document discusses CPLDs and the Altera MAX architecture. It describes how CPLDs integrate multiple PALs onto a single chip for more complex logic than a single PAL can provide. It then details the key components of the Altera MAX architecture, including Logic Array Blocks containing macrocells with programmable AND and OR arrays. Logic expanders allow implementing functions requiring more product terms. Programmable inversion can further reduce needed product terms. The MAX 7000 series uses this architecture with additional programmable interconnect and I/O control blocks.
cplds
- 1. CPLDs Dr. D. V. Kamath Professor, Department of E&C Engg., Manipal Institute of Technology, Manipal 1
- 2. 2 CPLDs Complex Programmable Logic Device (CPLD) Multiple PALs integrated together More Complex PAL Higher capacity devices Single PAL architecture is not feasible CPLDs are an extension of the PAL concept
- 5. 5 Altera CPLD Two Altera versions are available Altera Flex structure(Flex 8000 series) Altera Max structure (MAX 5000, MAX 7000, MAX 9000 series)
- 6. 6 Altera MAX architecture (a) Chip floor plan (b) MAX family Logic Array Block(LAB) (c) MAX family macro cell
- 7. 7 Altera MAX architecture The basic features of Altera MAX architecture are as follows: Altera MAX CPLD consists of LAB(Logic Array Block)s and chipwide interconnect Max family LAB consists of LA(local array) and macro cells LA consists of wide programmable AND array The basic logic cell for the Altera MAX architecture, a macrocell, is a descendant of the PAL. Macro cells comprise of narrow fixed OR array, logic expanders, and programmable inversion
- 8. 8 Altera MAX architecture- Logic expander Logic expanders Logic expander is used to generate extra logic terms Using the logic expander, it is possible to implement functions that require more product terms than are available in a simple PAL macrocell. The SOP(Sum of Product) expression can be rewritten as “sum of products of products”. We can use logic expanders to implement the extra product terms (called expander terms or helper terms). These extra product terms can be shared among other macrocells if needed. Hence, these extra logic gates that form these shareable product terms are called as shared logic expander , or just shared expander .
- 9. 9 Altera MAX architecture-Logic expander Consider the function 𝐹 = 𝐴 CD + 𝐵 CD + AB + B 𝐶 F has 4 product terms and thus F cannot be implemented using a macrocell that has only a 3-wide OR array F can be rewritten as 𝐹 = 𝐴 + 𝐵 CD + 𝐴 + 𝐶 𝐵 𝐹 = 𝐴. 𝐵 𝐶. 𝐷 + 𝐴. 𝐶 .𝐵 The 𝐴. 𝐵 and 𝐴. 𝐶 are the expander terms
- 10. 10 Altera MAX architecture-Logic expander
- 11. 11 Altera MAX architecture- Logic expander Logic expanders The disadvantage of the shared expanders is the extra logic delay incurred because of the second pass that may need to take through the product-term array. Before the logic assignment stage (assigning logic to macrocells by logic tools), it is not possible to predict whether the design need to use the logic expanders. The timing of the Altera MAX architecture is not strictly deterministic (i.e., it is not possible to predict the exact timing).
- 12. 12 Altera MAX architecture - Programmable inversion Programmable inversion allows the logic assignment stage to reduce the number of product terms needed
- 13. 13 Altera MAX architecture - Programmable inversion Use of programmable inversion to simplify the logic The function F = A · B' + A · C' + A · D' + A' · C · D requires 4 product terms But, F ' = A · B · C · D + A' · D' + A' · C' requires only 3 product terms
- 14. 14 MAX 7000 Altera CPLD Altera MAX 7000 The MAX 7000 family of high-density, high-performance CMOS CPLDs is based on Altera’s second-generation MAX architecture. MAX 7000 series is widely used and offers state-of-the-art logic capacity and speed performance. MAX 5000 is an older technology and MAX 9000 is similar to MAX 7000, except that MAX 9000 offers higher logic capacity MAX 7000 devices are available both based in EPROM and EEPROM technology
- 15. 15 MAX 7000 Altera CPLD Altera 7000 series architecture
- 16. 16 MAX 7000 Altera CPLD Altera 7000 series architecture comprises of LAB(Logic Array Block)s, PIA(Programmable Interconnect Array) and I/O control blocks PIA is capable of connecting any LAB input or output to any other LAB Also, the inputs and outputs of the chip connect directly to the PIA and to LABs Each LAB consists of 16 (two sets of 8) macro cells Each MAX 7000 LAB has 36 inputs from the chip-wide interconnect and 16 outputs to PIA . From 8 to 16 outputs from each LAB can be routed to the I/O pins through the I/O control block. From 8 to 16 inputs from the I/O pins can be routed through the I/O control block to the PIA
- 17. 17 MAX 7000 Altera CPLD
- 18. 18 MAX 7000 Altera CPLD The global clock input (GCLK) and global clear input (GCLRn) connect to all macro cells Two output enable signals (OE1n and OE2n) connect to all I/O control blocks The vertical lines in the logic array are common to all of the macro cells in a LAB The vertical lines are driven with programmable interconnect lines from the PIA and from shared expanders
- 19. 19 MAX 7000 Altera CPLD - LAB
- 20. 20 MAX 7000 Macro cell ACTEL ACT1 Logic module (LM)
- 21. 21 MAX 7000 Altera CPLD LAB and macro cell Each macro cell comprises a set of programmable AND plane that feeds an OR-gate and a programmable flip-flop. The flip-flops can be configured as D type, JK, T, SR, or can be transparent The number of inputs to the OR gate in a macro cell is variable; the OR gate can be fed from any or all of the 5 product terms within the macro cell, and in addition can have up to 15 extra product terms from macro cells in the same LAB. The product term flexibility makes the MAX 7000 series LAB more efficient in terms of the chip area(The typical logic functions that don't need more than 5 product terms, and the architecture supports wider functions when they are needed)
- 22. 22 Altera Flex architecture (a) Chip floor plan (b) Flex family Logic Array Block(LAB) (c) Details of the Logic Element(LE)