Design, Modeling and control of modular multilevel converters (MMC) based hvdc systems ghazal falahi

Design, Modeling and Control of Modular
Multilevel Converter Based HVDC Systems
Ghazal Falahi
December 2014

Background
3
Udc/2
Udc/2
Vconv
2

n

(n+1)
(n+2)
1
(2n)
Ud Uac
Desired voltage Achieved voltage
Achieved voltageDesired voltage
V.S.
ü  Modular arrangement
with identical power
modules
ü  Low level of
harmonics
ü  Lower switching
losses compared with
2level converters
ü  low component count
and compact size
X  More complex control algorithmsX  High losses
X  High harmonics
X  No redundancy
ü  Simple control

State of the Art
4
[1] M. Davies, M. Dommaschk, J. Dorn, J. Lang, D. Retzmann, D. Soerangr , „HVDC PLUS –Basics and Principle of Operation, Siemens Technical Article”
Majority of HVDC manufacturers use IGBT
2. high losses
Switching
Frequency
(modulation)
Semiconductor
Devices
1. Low power capacity
Issues:

MMC-HVDC loss (state of the art)
5
•  Candidate devices for high power levels
IGCT ETO
•  MMC-HVDC systems are operated at
much lower switching frequencies
[1] Buschendorf, Martin, Jens Weber, and Steffen Bernet. "Comparison of IGCT and IGBT for the use in the modular multilevel converter for HVDC applications." Systems, Signals and Devices
(SSD), 2012 9th International Multi-Conference on. IEEE, 2012.
[2] M. Davies, M. Dommaschk, J. Dorn, J. Lang, D. Retzmann, D. Soerangr , „HVDC PLUS –Basics and Principle of Operation, Siemens Technical Article”
Station losses close to 1%
(designs with IGBT)
•  Losses are still higher than thryistor based HVDC systems
•  Power rating is still lower
1.  Possible power
2.  Losses
Lower losses than IGBT
4% less losses compared
to IGBT [1] = 0.96% per station

Design procedure
6
1
•  Analyze ETO based MMC losses and potential power
2
•  MMC operation and control
3
•  Modulation
4
•  Thermal analysis
5
•  Design of MMC sub-module with ETO

Modular Multilevel Converter (MMC)
7
State S1 S2 Vsm
1 ON OFF Vc
2 OFF ON 0
q  MMC mathematical model:
q  MMC grid connection dynamic:
icirc =
ip +in
2
varm = vSM
i=0
n
∑ + Larm
diarm
dt
+ Rarmiarm
SM
2
SM
n
SM
(n+1)
SM
(n+2)
SM
1
SM
(2n)
DC

link
va
vb
vc
u0
ipa
Udc/2
Udc/2
ia
ib
ic
Larm
La
Lb
Lc
ipb ipc
ua
ub
uc
Rarm
D1
D2
S1
S2
ipa Vc
incinbina
Larm Larm
Rarm
Rarm
Larm
Rarm
Larm Larm
Rarm
Rarm
uk − u0 = varm
uk − (vk + u0 ) = varm K= a, b, c

uk (t) =
Udc
2
mk (t)

8
va
vb
vc
u0
ia-‐up
ia-‐low
Udc/2
Udc/2
ia
ib
ic
Larm
La
Lb
Lc
ib-‐up ic-‐up
ib-‐low ic-‐low
ua
ub
uc
Rar
m
Larm Larm
Larm Larm Larm
Rar
m
Rarm
Rarm Rarm Rarm
Inner
voltage
Inner
voltage
Inner
voltage
Inner
voltage
Inner
voltage
Inner
voltage
Required number of sub-modules
in each arm
N ≥
320KV
2.5KV
=128
§  Number of sub-modules
MMC sub-module devices used in power
stage design :
•  Switches (S1 & S2): 4.5KV,4KA Gen-4 ETO
•  Antiparallel diodes (D1 & D2): ABB fast
recovery diode 5SDF 16L4503
§  Semiconductor device
VAC 138KV
VDC-link 320KV
Nominal frequency 60HZ
Modular Multilevel Converter operation

iarm>0 S1 or D2
S1
D2
iarm<0 S2 or D1
D1
S2
Sub-module operation principal in MMC
9
•  Operation principal of MMC
Varm,ref
iarm
)cos(
22
)(,_ t
V
m
V
tV dcdc
refkarm ω−=
)cos(
23
)( ϕω −+= t
II
ti adc
arm
•  Logic of operation
Upper arm reference voltage
Arm current
The arm current flowing out of the sub-module is considered as positive (a) and the current flowing into sub-module is
considered as negative
D1
D2
S1
S2
ipa
Vc
D1
D2
S1
S2
ipa
Vc
D1
D2
S1
S2
ipa
Vc
D1
D2
S1
S2
ipa
Vc
(a) iarm>0
(b) iarm<0
0
,
>
dt
dV refarm
0
,
<
dt
dV refarm
0
,
>
dt
dV refarm
0
,
<
dt
dV refarm

Modular Multilevel Converter Control [1]
10
1.  An individual capacitor voltage controller
2.  The averaging controller
3.  The system controller
4.  Modulation reference generation
PI PI
1/2
Vc*
Vcu
Ik-‐low
Ik-‐up
Icir*
Icir
VAu*
Total DC voltage controller
PI
Vc*
Vcju

(j=1-‐2n)
±
-1 :-Ik-up , Ik-low ≥ 0
+1 :-Ik-up , Ik-low ≤ 0
VBju*
Individual DC voltage controller
Vmk(k=a,b,c)
PI
i*dref
Vod
iod
PI
i*qref
ω0Leq
ω0Leq
ioq
Voq
3dq/abc
System controller !
[1] Hagiwara, Makoto, and Hirofumi Akagi. "Control and experiment of pulsewidth-modulated modular multilevel
converters." Power electronics, IEEE Transactions on 24.7 (2009): 1737-1746.
VAu*
VBju* Vi/n E/(2n)
Vju*
(j=1-‐n)
dAneg
VAu*
VBju* Vi/n E/(2n)
Vju*
(j=n+1-‐2n)
dAneg
Modulation reference generation

Multilevel
Modulation
Fundamental switching
frequency
High switching
frequency
Space vector
PWM
Sinusoidal
PWM
Level shifted
PWM
Phase shifted
PWM
Space vector
control SHENLM
Modified NLM
MMC modulation methods
11
[1] Wang, Jun, Rolando Burgos, and Dushan Boroyevich. "A survey on the modular multilevel converters—Modeling,
modulation and controls." Energy Conversion Congress and Exposition (ECCE), 2013 IEEE. IEEE, 2013.
Choosing modulation method for the proposed structure
Advantages
ü  Fundamental frequency switching
ü  Lower losses
ü  Online calculation of switching angles
Issues
× High losses
× Complex vector calculation and selection
× Relying on look up tables (offline calculation
of switching angles

Proposed 60Hz modulation for MMC-HVDC
12
Vdc
N
2
Vdc
N
3
Vdc
N
0
ta
tb
Varm_k,ref (t)
Varm_ AV (t)
Switching angle calculation in each discrete step:
(ωt +φarm_k ) = arccos
n.
Vdc
N
−
Vdc
2
m
Vdc
2
"
#
$
$
$
%
&
'
'
'
Varm_k,ref (t) =
Vdc
2
+ m
Vdc
2
cos(ωt +φarm_k )
Varm_k,High =Varm_k,Low +
Vdc
n
n = round(
Varm_k,ref
USM _ave
)
N : number of sub-modules in arm

n : number of active sub-modules

USM_ave: average SM voltage
A piece of MMC reference arm voltage

Each level is Vdc/n more than the previous level
Switching instants
ωti = arccos
n.
Vdc
N
−
Vdc
2
m
Vdc
2
"
#
"
"
"
$
%
$
$
$
−φarm_k
ωti+1 = arccos
n.
Vdc
N
−
Vdc
2
m
Vdc
2
"
#
#
#
#
$
%
%
%
%
−φarm_k

Implementation of 60Hz modulation
13
0 0.5 1 1.5 2 2.5
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
time (secs)
Submodulecapacitorvoltages(pu)
Capacitor Voltage balancing
Nearest level modulation
MMC system controller
1.  Active/reactive power
2.  Individual capacitor voltage
3.  Circulating current
4.  Negative/zero sequence and LVRT, etc.
Vmodulation_arm three phases a, b, c
Switching angles θ1, θ2,.., θi
Switching pulses P1, P2,.., Pi
Switching pulses
Switching index
?
Sub-module capacitor voltages are unbalanced

Capacitor voltage sorting and balancing
14
D1
D2
S1
S2
ipa
Vc
D1
D2
S1
S2
ipa
Vc
D1
D2
S1
S2
ipa
Vc
D1
D2
S1
S2
ipa
Vc
iarm>0
iarm<0
Capacitor bypassed
Capacitor bypassed
Capacitor discharge
Capacitor charge
Modifications:
1.  Only remaining Sub-modules are considered to reduce equivalent switching frequency
2.  Circulating current error is added to the modulation reference to make balancing faster
3.  Number of active sub-modules calculated by using average measured capacitor voltages to
increase accuracy
Iarm>0 Iarm<0
Sub-modules with
maximum
capacitor voltages
turn on first
Sub-modules with
minimum
capacitor voltages
turn on first
Vdc1
Vdcn
Sorting
Vdc_sorted = Vdc_max • • • Vdc_max
!
"#
$
%&
Vdc_index = ni_vdc_max • • • ni_vdc_max
!
"#
$
%&

Semiconductor loss calculation for a
500MW MMC-HVDC system
15
Gen-4 ETO power loss characteristics
ETO :
EOFF (I) = a × I + b = 0.0041× I + 0.21
VON(I) = c× I + d = 0.0014× I +1.1
Diode:
Eswitching(I)=e× I + f=0.00018×I+0.8
Von(I)=g × I + h=0.79×10-3×I+1.9
[1] Li, J., A.Q. Huang, and W. Jing. 7MVA ETO Light NPC converter for multi-MW direct-driven wind turbine application. in Power
Electronics and Machines in Wind Applications, 2009. PEMWA 2009. IEEE. 2009. IEEE.
Ploss−Switch = (PcondS1 + PcondS2 + PSwitchingS1 + PSwitchingS2 )
Ploss−Diode = (PcondD1 + PcondD2 + PSwitchingD1 + PSwitchingD2 )
EOFF (reverse recovery loss)
EOFF+EON (snubber loss)
1. Switch losses
2. Switch losses

Proposed loss estimation method for 60Hz
modulation
16
Diode D2 Switch S1 Diode D1 Switch S2
t1t2t3
0
Varm
iarm
m=1
φ=0
!

Losses=[0 0 0 0 0 0 0 0]
Losses=[0 X 0 0 0 0 0 0]
Losses=[0 X 0 0 0 X 0 0]
Losses=[0 X 0 X 0 X 0 0]
Losses=[X X X X X X X X]
ti! ti+1!
!
Pcond =
1
T
nPD_cond (−ipa )+(N − n)PSwitch_cond (−ipa )"# $%t2
t1
∫ dt + nPSwitch_cond (ipa )+(N − n)PD_cond (ipa )"# $%t3
t2
∫ dt
Number of small intervals
(sampling rate)
ni =
Varm,ref
Vsm_ave
!
"
!
#
$
#
t=tup
−
Varm,ref
Vsm_ave
!
"
!
#
$
#
t=tlow

Loss calculations
17
n× PD_cond (−ipa )( )dt + PD_cond (−ipa )( )dt + PD_cond (−ipa )( )dt +...+ PD_cond (−ipa )( )dt
tk+i
t1
∫
tk+1
tk+2
∫
tk
t k+1
∫
t2
tk
∫
$
%
&&
'
(
))
+(N − n) PSwitch_cond (−ipa )( )
t2
tk
∫ dt + PSwitch_cond (−ipa )( )
tk
tk+1
∫ dt +...+ PSwitch_cond (−ipa )( )
tk+i
t1
∫ dt
$
%
&&
'
(
))
Esw (i) = Esw (θi )
tlow<t<tup
∑
n.PD_cond (−ipa )+(N − n)PSwitch_cond (−ipa )( )dt
t2
t1
∫
#
$
%%
&
'
((
n
n≤N
∑ = n. PD_cond (−ipa )( )dt
t2
t1
∫ +(N − n) PSwitch_cond (−ipa )( )
t2
t1
∫ dt
Esw_total = ESW (i)× fsw
System
Controller
1. Number of ON sub-modules 1. Sub-module capacitor
voltage sorting
2. Sub-module selection
based on sorted Vdc vector
Vdc1
Vdcn
nactive P1
Pn
P2
2. Switching angle calculation
Vmod,ref
nactive = round(
Varm,ref
Vsm
)
θi =
2Varm
Vdc
−1
m
−φarm
Loss
calculations
Individual
device
losses
iarm
PS11
PS18
PD11
PD18
Proposed modulation and loss calculation diagram

Individual device losses – S1 in sub-modules (1- 4)
18
0 10 20 30 40 50 60 70 80 90 100 110
-1000
0
1000
2000
3000
4000
5000
6000
0 10 20 30 40 50 60 70 80 90 100 110
-1000
0
1000
2000
3000
4000
5000
6000
0 10 20 30 40 50 60 70 80 90 100 110
-1000
0
1000
2000
3000
4000
5000
6000
0 10 20 30 40 50 60 70 80 90 100 110
-1000
0
1000
2000
3000
4000
5000
6000
Is loss balancing an issue?

19
0 10 20 30 40 50 60 70 80 90 100 110
-1000
0
1000
2000
3000
4000
5000
6000
0 10 20 30 40 50 60 70 80 90 100 110
-1000
0
1000
2000
3000
4000
5000
6000
0 10 20 30 40 50 60 70 80 90 100 110
-1000
0
1000
2000
3000
4000
5000
6000
0 10 20 30 40 50 60 70 80 90 100 110
-1000
0
1000
2000
3000
4000
5000
6000
Individual device losses – S1 in sub-modules (5- 8)
Sorting and swapping sub-modules eventually makes device losses balanced

Averaged device losses over 200 cycles
20
Device Loss (PF= -0.95) Loss (PF= 1) Loss(PF=+0.95)
D1 799 812 839
D2 1598 1587 1366
S1 1975 1960 2219
S2 1259 1156 1184
Each sub-module losses 5631 5515 5608
Total MMC loss (per station) 4.32 MW 4.2 MW 4.3 MW
Total MMC losses per station in design with IGBT [1] 4.6 MW
0
2000
4000
6000
D1 D2 S1 S2 SM loss
PF=-0.95
PF=+0.95
PF=1
[1] Yang, Liu, Chengyong Zhao, and Xiaodong Yang. "Loss calculation method of modular multilevel HVDC converters." Electrical
Power and Energy Conference (EPEC), 2011 IEEE. IEEE, 2011.
9% lower losses
compared to design
in [1]
Conventional MMC-HVDC
system semiconductor loss
per station = more than 1%
ETO based MMC-HVDC
semiconductor loss per
station = 0.84 %
16% less losses
Around 1%
efficiency
improvement

Thermal Analysis of ETO based sub-module
21
Heat pipe based cooling
Junction temperature of ETOs and diodes much lower than 110°
Device Junction temperature (°C)
D2 61.9
S2 67.4
S1 81.6
D1 54.4
ETO can be used for higher power ratings
Power capacity of ETO based MMC-HVDC system can reach more than 1000MW
Device Junction temperature (°C)
D2 82.9
S2 90.6
S1 109.2
D1 70.1
500MW
operation
Potential power =1000MW
Device temperature for designed ETO based MMC-HVDC
[1] Li, Yuxin, Alex Q. Huang, and Kevin Motto. "Experimental and numerical study of the emitter turn-off thyristor (ETO)." Power Electronics,
IEEE Transactions on 15.3 (2000): 561-574.
[2] Li, Jun, et al. "ETO light multilevel converters for large electric vehicle and hybrid electric vehicle drives." Vehicle Power and Propulsion
Conference, 2009. VPPC'09. IEEE. IEEE, 2009.

Proposed ETO based MMC-HVDC
22
Characteristic ETO IGCT IGBT GTO
Conduction loss Low Low High Low
Switching time Fast Fast Medium Slow
Turn-off capability High High Low Low
Self-power function Yes No No No
Built-in sensor Yes No No No
Positive temperature
Coefficient
Best Poor Good Poor
Semiconductor device selection [1]
[1] Li, Yuxin, Alex Q. Huang, and Kevin Motto. "Experimental and numerical study of the emitter turn-off thyristor (ETO)." Power
Electronics, IEEE Transactions on 15.3 (2000): 561-574.
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
0
0.05
0.1
0.15
0.2
0.25
0.3
time (secs)
Circuatingcurrent(pu)
Cdc
S1
S2
iaarm
VSM
D1
Rclamp
Cclamp
Lclamp
Cdc
RclampS1
S2 Cclamp
iaarm
D1
Lclamp
cc
A
cc
c
B
Cdc
L
R D S1
S2
C
𝑑𝑖
𝑑𝑡
=
𝑉𝐷𝐶 − 𝑉𝐶𝑐𝑙𝑎𝑚𝑝
𝐿
𝑃𝑐𝑙𝑎𝑚𝑝 =
1
2
𝐿𝑖 𝑝𝑒𝑎𝑘
2
.
𝑉𝐶𝑐𝑙𝑎𝑚𝑝
𝑉𝐷𝐶 − 𝑉𝐶𝑐𝑙𝑎𝑚𝑝
. 𝑓𝑠
𝐶𝑐𝑙𝑎𝑚𝑝 =
𝑉𝐶𝑐𝑙𝑎𝑚𝑝
∆𝑉𝐶𝑐𝑙𝑎𝑚𝑝 . 𝑅. 𝑓𝑠
𝑅 =
𝑣 𝑐𝑙𝑎𝑚𝑝
2
𝑃𝑐𝑙𝑎𝑚𝑝
Leq = nactive.Lclamp ≥128× Lclamp

24
Simulated MMC-HVDC system
System is controlled in two different
scenarios
(1)
(2) Side 1: DC link voltage control, AC voltage control
Side 2: active and reactive power control
Side 1: DC link voltage control, reactive power control
Side 2: active and reactive power control
VAC 138KV
VDC-link 320KV
Fundamental frequency 60HZ
Number of SMs 16
Fsw 60Hz

MMC equations under fault operating condition
25
The system mathematical equations can be decomposed to positive, negative and zero components[1]:
!
!!!"#
!
(!)
!"
+ !!!"#
!
(!) = !!"#
!
(!) − !!"#
!
(!)
!
!!!"#
!
(!)
!"
+ !!!"#
!
(!) = !!"#
!
(!) − !!"#
!
(!)
!
!"!
(!)
!"
+ !!!
! = !!
! − (!!
! + !!(!))
!!! + !!! + !!!
3
= !!
Zero-sequence component extraction
!!!
!
(!)
!"
= −
!
!
!!
!
+ !!!
!
+
1
!
!!
!
−
1
!
!!
!
!!!
!
(!)
!"
= −
!
!
!!
!
− !!!
!
+
1
!
!!
!
−
1
!
!!
!
!!!
!
(!)
!"
= −
!
!
!!
!
− !!!
!
+
1
!
!!
!
−
1
!
!!
!
!!!
!
(!)
!"
= −
!
!
!!
!
+ !!!
!
+
1
!
!!
!
−
1
!
!!
!
Active and reactive powers at PCC
Three-phase positive and negative sequence
subsystems in synchronous reference frame
! = !! + !!! sin 2!" + !!! cos 2!" + 3!!!!
! = !! + !!! sin 2!" + !!! cos 2!"
!!
!!
!!!
!!!
!!!
!!!
=
3
2
!!
!
!!
!
!!
!
−!!
!
!!
!
−!!
!
!!
!
!!
!
!!
!
−!!
!
−!!
!
!!
!
!!
!
!!
!
−!!
!
−!!
!
!!
!
−!!
!
!!
!
!!
!
!!
!
!!
!
!!
!
−!!
!
!!
!
!!
!
!!
!
!!
!
! = 1.5!!
!
!!
!
! = −1.5!!
!
!!
!
Cell
2
Cell
n
Cell
(n+1)
Cell
(n+2)
Cell
1
Cell
(2n)
DC

link
va
vb
vc
DC

link
u0
ia-‐up
ia-‐low
Udc/2
Udc/2
ia
ib
ic
2L
2L
2L 2L
2L 2L
La
Lb
Lc
ib-‐up ic-‐up
ib-‐low ic-‐low
ua
ub
uc
S1
S2
VS
M
Vc
2R 2R 2R
2R2R2R
[1] Guan, Minyuan, and Zheng Xu. "Modeling and control of a modular multilevel converter-based HVDC system under
unbalanced grid conditions." Power Electronics, IEEE Transactions on 27.12 (2012): 4858-4867.

Operation of the simulated MMC-HVDC system
26
Dynamic response of the system to step
change in active power
PSCAD simulation results
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-3
-2
-1
0
1
2
3
time (sec)
P1&P2(pu)
p1
p2
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-1
-0.5
0
0.5
1
time (sec)
Q1&Q2(pu)
Q1
Q2
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-1
-0.5
0
0.5
1
time (sec)
Q1&Q2(pu)
Q1
Q2
Dynamic response of the system to step
change in reactive power
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-3
-2
-1
0
1
2
3
time (sec)
P1&P2(pu)
P1
P2
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
2
2.5
3
3.5
4
time (sec)
Vdc(pu)
Vdc

27
0 0.1 0.2 0.3 0.4 0.5 0.6
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
time (sec)
Q1&Q2(pu)
Q1
Q2
Dynamic response of the system to
active and reactive power reversal
at t=0.3sec and t=0.5sec
respectively
Dynamic response of the system to
AC voltage change from 1pu to 1.1
PSCAD simulation results
0.2 0.25 0.3 0.35 0.4 0.45 0.5
-1
-0.5
0
0.5
time (sec)
Q1&Q2(pu)
Q1
Q2
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
Time (sec)
Activeandreactivepower
reversalside1&2(pu)
0.2 0.25 0.3 0.35 0.4 0.45 0.5
-3
-2
-1
0
1
2
3
time (sec)
P1&P2(pu)
P1
P2
0.2 0.25 0.3 0.35 0.4 0.45 0.5
-1.5
-1
-0.5
0
0.5
1
1.5
time (secs)
Vabc(pu)

28
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-1
0
1
2
3
4
5
Time (secs)
Vdc(pu)
Vdc ref
Vdc
Dynamic response of the step change in DC voltage
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
3Phasecurrentsside2(pu)
ia
ib
ic
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-3
-2
-1
0
1
2
3
time (sec)
Iabcside1(pu)
ia
ib
ic

Single line to ground (SLG) fault on AC line
side 2
29
Issues:
1. Negative and zero sequence terms are present in currents
2. Active and reactive powers oscillate at double fundamental frequency
3. DC link has ripples with double fundamental frequency
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
-3
-2
-1
0
1
2
3
time (sec)
P1&P2(pu)
P1
P2
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
-2
-1
0
1
2
time (sec)
Iabcside2(pu)
ia
ib
ic
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
-2
-1
0
1
2
time (sec)
Iabcside1(pu)
ia
ib
ic
Fault
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
-0.5
0
0.5
1
time (sec)
Idqneg(pu)
id neg
iq neg
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
-0.4
-0.2
0
0.2
0.4
time (sec)
Zerosequencecurrent(pu)
i zero
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
2.5
3
3.5
time (sec)
Vdc(pu)
Vdc
Fault

State of the art
1.  Calculation of reference positive and negative sequences
2.  Using additional PI and PR
controllers to eliminate positive,
negative and zero sequences
3. Using both positive and negative phase locked loop (PLL)
30
[1] Timofejevs, Artjoms, et al. "Control of transformerless MMC-HVDC during asymmetric grid faults." Industrial
Electronics Society, IECON 2013-39th Annual Conference of the IEEE. IEEE, 2013.
Issues:
Makes the MMC control more complicated
Slow response time (50ms)

Proposed control structure
31
dazero
Zero
sequence

calculation dbzero
dczero
n
n
n
Ea
Eb
Ec
Ea0
Eb0
Ec0
daneg
Vcju
Eliminating

zero

sequence
Eliminating

positive

sequence
Vcjv
Vcjw
dbneg
dcneg
n
n
n
Step1. Real-time calculation of zero and negative sequence
components based on Analytical Equations
!!!
!!!
!!!
= !!
!!
!!
!!
!!"
!!"
!!"
=
!!
!!
!!
− !!!!
!!
!!
!!
!!=
!
!
2 −1 −1
−1 2 −1
−1 −1 2
!!=
!
!
!!
!! !
!
!! !
−1 0 −1
!!
!! !
!
!! !
!
!

Negative and zero sequence voltage components calculated
from PCC voltages –controller references
32
Step2. Updating the modulation to eliminate the effect of
zero and negative sequence components in the system
VAu*
VBju* Vi/n E/(2n)
Vju*
(j=1-‐n)
dAneg dAzero
VAu*
VBju* Vi/n E/(2n)
Vju*
(j=n+1-‐2n)
dAneg dAzero
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Negativesequencevoltages(pu)
Ea
Eb
Ec
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Zerosequencevoltages(pu)
E0a
E0b
E0c

MMC-HVDC system response to SLG fault with
proposed controller
33
Negative sequence currents in dq frame when SLG fault is applied
Zero sequence currents when SLG fault is applied
Fault with conventional controller
Suppressed negative and zero components
with proposed controller
0.1 0.2 0.3 0.4 0.5 0.6
-0.1
0
0.1
0.2
0.3
0.4
0.5
time (sec)
Idqneg(pu)
id neg
iq neg
0.1 0.2 0.3 0.4 0.5 0.6
-0.05
-0.025
0
0.025
0.05
Id&Iqnegativesequence(pu)
Idneg ref
Idneg
0.1 0.2 0.3 0.4 0.5 0.6
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
time (sec)
Zerosequencecurrent(pu)
i zero
0.1 0.2 0.3 0.4 0.5 0.6
-0.05
-0.025
0
0.025
0.05
Zero-sequencecurrent(pu)
izero
Fault Fault

34
MMC-HVDC system response to SLG fault with proposed
controller- arm circulating current
Conventional controller
Proposed controller
Before fault Fault
0.2 0.25 0.3 0.35 0.4 0.45 0.5
0
0.2
0.4
0.6
0.8
1
time(secs)
icirc(pu)
0.2 0.25 0.3 0.35 0.4 0.45 0.5
-0.2
0
0.2
0.4
0.6
0.8
time (secs)
icirc(pu)

35
MMC-HVDC system response to SLG fault with proposed
controller- sub-module capacitor voltages
Conventional controller
Proposed controller
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0.34
0.35
0.36
0.37
0.38
0.39
0.4
time (secs)
Sub-modulecapacitorvoltages(pu)
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0.34
0.35
0.36
0.37
0.38
0.39
0.4
time (secs)
Before fault Fault

36
MMC-HVDC system response to unbalance condition
with proposed controller
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-1.5
-1
-0.5
0
0.5
1
1.5
time (secs)
3phasevoltagse(pu)
Va
Vb
Vc
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
time (secs)
3phasecurrents(pu)
ia
ib
ic
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
time (secs)
DCcurrent(pu)
idc
Before fault Fault Fault with proposed controller

MMC-HVDC system dynamic response to three phase
fault at inverter side- constant power control
37
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
time (sec)
Vabcside2(pu)
ia
ib
ic
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-3
-2
-1
0
1
2
3
time (sec)
Iabcside1(pu)
ia
ib
ic
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-3
-2
-1
0
1
2
3
time (sec)
Iabcside2(pu)
ia
ib
ic
Fault at converter 2
side at t=0.3-0.4sec
Fault

MMC-HVDC system dynamic response to
three phase fault at inverter side
38
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time (sec)
Vdc(pu)
Vdc
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-3
-2
-1
0
1
2
3
time (sec)
P1&P2(pu)
P1
P2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-1
-0.5
0
0.5
1
time (sec)
Q1&Q2(pu)
Q1
Q2
Fault

MMC-HVDC system response to 50% voltage
sag on both sides
39
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
time (sec)
Iabcside2(pu)
ia
ib
ic
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-3
-2
-1
0
1
2
3
time (sec)
Iabcside1(pu)
ia
ib
ic
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-4
-3
-2
-1
0
1
2
3
4
time (sec)
P1&P2(pu)
P1
P2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
time (sec)
Q1&Q2(pu)
Q1
Q2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0.8
0.85
0.9
0.95
1
1.05
1.1
1.15
time (sec)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
1
2
3
4
5
time (sec)
Vdc(pu)
Vdc
Dynamic response of the system to 50% for 0.1 sec
(t=0.3-0.4) voltage sag on both rectifier and inverter sides
Issues:
1. AC currents increase
2. DC link voltage oscillates

Proposed LVRT control
40
V*ac
Vmk(k=a,b,c)
PI
i*odref
Vod
iod
PI
i*qref
ω0Leq
ω0Leq
ioq
Voq
3dq/abc
System controller
Normal
operation
LVRT
Pref
Pref-‐LVRT
PI
V*dc
Vdc
Q*ref
PI
Vac Qref-‐LVRT
!!"#$% = 0 vac >0.85 pu
!!"#$% = −2
!!"
!!"#$%&
+ 2 0.5< vac ≤0.85pu
!!"#$% = 0 vac ≤0.5 pu
!!"#$% = 1 − !!"#$%
2
3
4
Time
Voltage
Vmin
tmin t1 t20
V1
V2
Vnom
1
Low voltage ride through curve defined by grid code
Ireactive/Irated(%)
Voltage(%)
0.2pu
50 90
1pu
110
Normal
operationFault
operation
The required percentage of reactive current during LVRT
Changes in the system controller
[1] R.P.S. Leão1, J.B. Almada1, P.A. Souza2, R.J. Cardoso1, R.F. Sampaio1, F.K.A. Lima1, J.G. Silveira2 and L.E.P. Formiga , “The
Implementation of the Low Voltage Ride-Through Curve on the Protection System of a Wind Power Plant” , International Conference
on Renewable Energies and Power Quality (ICREPQ’11) Las Palmas de Gran Canaria (Spain), 13th to 15th April, 2010

Fault performance with the proposed
LVRT control
41
1. AC currents stay constant
2. Less increase in DC link voltage
3. Simple implementation
Solution
advantages:
With proposed controller

Applying LVRT profile
42
1. Active power reference
decreased to avoid instability
2. Reactive power is injected to
maintain voltage
Solution:
2
3
4
Time
Voltage
Vmin
tmin t1 t20
V1
V2
Vnom
1

MMC-HVDC operation under DC fault
43
SMs
SMs
SMs SMs
SMs SMs
DC

link
ia-‐up
ia-‐low
Udc
ia
ib
ic
Larm
Larm
Larm Larm
Larm Larm
La
Lb
Lc
ib-‐up ic-‐up
ib-‐low ic-‐low
ua
ub
uc
idcLcableRcable
ic
CB
CB
CB
D1
D2
S1
S2
ipa Vc
Stage1. MMC operational and AC circuit breakers still closed
Stage2. MMC not operating (blocked), AC side CB still closed
Stage3. MMC not operating, AC circuit breaker closed
Stage1:
§  sub-module capacitors
discharge through S1 for a very
short time until MMC pulses are
blocked
§  The sub-module capacitor
discharge time is very short so
sum of sub-module voltages
stays close to Vdc

0.19 0.195 0.2 0.205 0.21 0.215 0.22
0
2
4
6
8
10
12
time (secs)
Idc(KA)
MMC-HVDC operation under DC fault
44
LcableRcable
2Larm/3
idc
ic
icable
Vsub-‐module

caps
~
Udc
Equivalent circuit during stage1
The Vdc oscillation frequency at each stage is found by
eqeqCL
1
0 =ω
3/2..
3/22
0
armcable
armcable
LLC
LL +
=ω
0.19 0.195 0.2 0.205 0.21 0.215 0.22
100
150
200
250
300
350
time (secs)
Vdc(KV)
FaultNormal operation

stage 2 : MMC PWM blocked, AC circuit breaker closed
45
Stage2. MMC blocked (pulses off) AC side circuit breakers closed,
D2 conducts and passes AC current to the fault side
ü  Some of the diodes turn off as the arm current reaches the
zero crossing point
eqeqCL
1
0 =ω
The Vdc oscillation frequency
Leq depends on number of
conducting diodes
Equivalent circuit during stage2
DC

link
ia-‐up
ia-‐low
Udc
ia
ib
ic
Larm
Larm
Larm Larm
Larm Larm
La
Lb
Lc
ib-‐up ic-‐up
ib-‐low ic-‐low
ua
ub
uc
idcLcableRcable
ic
CB
CB
CB
Fast AC breaker required!
Design consideration:
D2 has to withstand 2pu current
for around 5 cycles
ABB fast recovery diode 5SDF 16L4503

0.2 0.25 0.3 0.35 0.4 0.45 0.5
-3
-2
-1
0
1
2
3
time (secs)
Idc(pu)
stage 3 : MMC blocked, AC circuit breaker tripped
46
Stage3. MMC blocked (pulses off) and AC side circuit breakers open
Equivalent circuit during this stage3
LcableRcable
2Larm
idc
2Larm 2Larm
LcableRcable
2Larm/3
idc
t
LL
R
dcdc
cable
cable
eIi
)
3/2
(
0
0+
−
=
Fault current
Fault applied AC CB
tripped5cycles
0.2 0.25 0.3 0.35 0.4 0.45 0.5
0
0.5
1
1.5
2
2.5
3
3.5
time (secs)
Vdc(pu)
MMC blocked
MMC controller blocks pulses when Idc>2pu

Solutions to DC fault
47
2. ABB hybrid DC circuit breaker (operates in 5msec)
3. Alstom ultrafast mechatronic HVDC DC
circuit breaker (operates in 5msec)
4. Alstom hybrid MMC structure uses FB sub-
modules to suppress DC faults
1. A lot of designs use AC circuit breakers to suppress DC side faults
If the fast DC breaker is used fault current
is suppressed in 5ms

Proposed MMC with unequal DC values
48
time
(sec)

0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18
-400
-300
-200
-100
0
100
200
300
400
time (sec)
Outputvoltage(volts)
Vo
Vdc/2S

3Vdc/2S

2Vdc/2S

time
(sec)

Vdc/2S

3Vdc/2S

2Vdc/2S

0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18
-400
-300
-200
-100
0
100
200
300
400
time (sec)
Outputvoltage(volts)
Vo
Conventional
MMC using
CSPWM
Conventional
MMC using
minimal THD
Modulation
MMC with
unequal DC
sources using
minimal THD
modulation
15.4%
11.3%
7.3%
System
Controller
Minimal THD
modulation
(calculation of
switching
angles)
m
ωt
θ1
θs
θ2
Target
waveform
generation
(Determine
the number of
required SM
and
generation of
firing pulses)
S1
S2
S2s
SM1
SM2
SMs
SM(s+1)
SM5
SM2s
Vdc/2s
2Vdc/2s
3Vdc/2s
Advantages of the proposed
configuration
ü  Lower THD
ü  60HZ modulation with small
number of sub-modules

References
[1] Falahi, Ghazal. "Design, Modeling and Control of Modular Multilevel Converter based HVDC
Systems." PhD Dissertation NCSU (2014).
[2] Falahi, Ghazal, and Alex Q. Huang. "Design consideration of an MMC-HVDC system based on
4500V/4000A emitter turn-off (ETO) thyristor." Energy Conversion Congress and Exposition (ECCE),
2015 IEEE. IEEE, 2015.
[3] Falahi, Ghazal, and Alex Huang. "Control of modular multilevel converter based HVDC systems
during asymmetrical grid faults." Industrial Electronics Society, IECON 2014-40th Annual Conference
of the IEEE. IEEE, 2014.
[4] Falahi, Ghazal, Wensong Yu, and Alex Q. Huang. "THD minimization of modular multilevel
converter with unequal DC values." Energy Conversion Congress and Exposition (ECCE), 2014 IEEE.
IEEE, 2014.
[5] Falahi, Ghazal, and Alex Huang. "Low voltage ride through control of modular multilevel converter
based HVDC systems." Industrial Electronics Society, IECON 2014-40th Annual Conference of the
IEEE. IEEE, 2014.
49

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