![CCFE is the fusion research arm of the United Kingdom Atomic Energy Authority.
This work was funded by the RCUK Energy Programme [grant number EP/I501045] .
Developing new Zynq based
instruments using
Koheron-SDK
graham.naylor@ccfe.ac.uk](https://image.slidesharecdn.com/developingnewzynqbasedinstrumentsusing-170424105332/85/Developing-new-zynq-based-instruments-1-320.jpg)
Developing new zynq based instruments
- 1. CCFE is the fusion research arm of the United Kingdom Atomic Energy Authority. This work was funded by the RCUK Energy Programme [grant number EP/I501045] . Developing new Zynq based instruments using Koheron-SDK graham.naylor@ccfe.ac.uk
- 2. • Why use an FPGA and what is Zynq? • Setting up the Koheron-SDK • Looking around the SDK • Using IP integrator and writing new IP cores • Define our instrument • Red Pitaya • Build and develop the instrument (add DSP) • Make the instrument on the target board • Test the instrument Building an instrument from scratch Slide 2 Developing Zynq based instruments using Koheron-SDK April 2017
- 3. • FPGAs now contain a huge number of logic gates for computation (Modern high end CPUs and GPUs have up to 15 billion transistors – current FPGAs can have over 30 billion and continue to scale) • Good at doing ultra fast hard real-time, with DSP throughput way exceeding that of CPUs and GPUs • Zynq incorporates 1 - 4 ARM cores and can run a full OS to interface with high level applications (UI) Why use an FPGA and what is Zynq? Slide 3
- 4. The challenge is to seamlessly make use of the FPGA (logic part) and the CPU (software programmed). Many tools exist and Xilinx provide so called ‘High Level Synthesis’ and ‘SDSoC’ (Software Defined System on a Chip) in order to provide an easy way in for software programmers used to C/C++. This does however require the use of a relatively small library set of functions (IP) provided with a logical description (that will effectively provide an accelerated function). This functions are then orchestrated from the software level. Integrating IP using a tool from Xilinx called ‘IP Integrator’ works at the logical level and allows more tightly integrated hardware processes for very high speed digital signal processing with complex functions. The Koheron-SDK allows the use of IP integrator, while providing a clean interface to a C++/python environment on the processor, without writing any code in an HDL (Hardware Definition Language). Which development environment to use? Slide 4
- 5. The Koheron Instrument build procedure This is the title of the slide and the date it was written Slide 5 Build of instrument from definition files on the left orchestrated by a make file Build of instrument from definition files on the left orchestrated by a make file
- 6. • Visit https://www.koheron.com/software-development-kit/ • Builds on methodology developed by Pavel Demin (https://github.com/pavel-demin/red-pitaya-notes) • Runs on Ubuntu (Works well on a virtual machine) • Follow instructions on Koheron site to install dependencies and clone repository from Github -essentially clone repository and run: sudo –H make setup Setting up the Koheron-SDK Slide 6
- 7. • -> Look at directory structure: fpga/cores, examples/xxx (formerly instruments/xxx), tmp/, boards/redpitaya (xdc in config) Depending on which version of Vivado (eg 2016.2) you have, may need to edit fpga/settings64.sh to match (currently expects 2016.4). Various build activities co-ordinated by ‘make’ commands Note make files currently (April 17) work in Python 2.7 or 3.5 (Anaconda allows switching between python installations). You can set up environments to be able to switch: conda create –n py27 python=2.7 conda create –n py35 python=3.5 switch to it using source activate py27 If using vivado 2016.2 use the version switch when using ‘make’ commands (eg- make VIVADO_VERSION=2016.2 CONFIG=examples/led-blinker/config.yml ) Looking around the SDK Slide 7
- 8. The whole logic part of the design is encapsulated in the IP integrator ‘Block Diagram’. No design is held outside this diagram, but is automatically wrapped in an HDL wrapper. Connections to physical pins needs to be defined – this is contained in the xdc files provided. To write a new core block to be used in the block diagram: Create a new directory for your block definition: ../fpga/cores/newcore_vx_x Insert: hdl definition – eg ‘newcore.v’ ‘core_config.tcl’ (see another core for an example) ‘newcore_tb.v’ (if you wish to test it) To test it use: make CORE=fpga/modules/newcore_vx_x test_core Include core name in the config.yml file of the instrument using it (then will build automatically) Using IP integrator and writing new IP cores Slide 8
- 9. Create a new directory for your new instrument: ../instruments/my_instrument Three files are needed: config.yml (board to be used, required cores, memory map, configuration and status registers required, fixed parameters, relevent xdc constraint files for the board being used, and the server and drivers required – work from an existing example) block_design,tcl (work from an instrument with similar needs and remove what is not needed and edit – see later) my_instrument.hpp (again work from an existing instrument and edit to include the controls needed) Optionally: test.py ( a test python script to test or make use of the required functions – see existing examples in other instruments) Web interface defined by one or more typescript files Define a new instrument Slide 9
- 10. • Start with a block_diagram.tcl copied from a similar instrument example (ie has the interfaces you might need). Remove the bits you don’t need. What is missing can be created in ip-integrator (Vivado tool). • Create the block diagram using: make CONFIG=instruments/my_instrument block_design - This opens Vivado Once you have the design in Vivado with the block diagram open: • Edit the block diagram and add the IP you need and connect up. • Export the block diagram to a tcl file in the instrument directory and call it ‘block_diagram.tcl’, replacing the original using file>export>Export Hardware…, or the command: write_bd_tcl -force <path to:->/koheron- sdk/instruments/sdr/block_design.tcl> • Exit Vivado Create the block diagram Slide 10
- 11. • An SD card on the Red Pitaya host is needed with the Linux OS set up. A pre- made SD card image can be downloaded from the Koheron web site, or the full SD card built using (where <my_instrument> is the name of the specific instrument directory containing the design of the instrument to be created): make CONFIG=instruments/<my_instrument>/config.yml all # instrument, os, (device tree, U-boot and Linux kernel), drivers + web server. sudo bash ./os/scripts/ubuntu-development.sh tmp/<my_instrument> ./os tmp/<my_instrument>/os <my_instrument> # SD card image with Ubuntu 16.04 root file system Copy image from tmp/<my_instrument> directory on to an SD card using image writing software (eg dd on linux or HDD Raw copy tool on Windows) – warning, sd card images tend to be rather large and you shouldn’t really need to keep more than one. • If updating the instrument bitfile or adding a new one run: make CONFIG=instruments/<my_instrument>/config.yml HOST=<IP address> run This builds and downloads the required bit file and drivers to the target board • In case of problems in bit file generation, open the created xpr file: tmp/<instrument name>.xpr • Locate errors and change implementation strategy if necessary (due to failure to close timing for example), eg to ‘Performance ExplorePostRoutePhysOpt’ Create the instrument and send to target Slide 11
- 12. • Aim is not to build a high performance polished instrument (for that see http://pavel-demin.github.io/red-pitaya-notes/) • Purpose is to show how to build an instrument using signal processing techniques within IP integrator of Vivado and deploy on the Red Pitaya as an example to show how quickly it can be done. • Walk through video of the steps in the videos (links at end of this presentation). • Based on a Software Defined Radio (SDR) which uses a homodyne receiver demodulating an AM signal with the layout below performed in logic on the FPGA: Hands-on example of a software defined radio on the Red Pitaya Slide 12 ADC decode ADC decode Local Oscillator Local Oscillator LPFLPF LPFLPF CORDICCORDIC DAC output DAC outputAntenna In I Q I Q A φ FM demodulation/QPSKdecode/…. To speaker PS controlPS control LPFLPF
- 13. • Loop aerial uses about 1.5m of 10 way ribbon cable in a loop with the connections staggered to make 10 turns. Ribbon cable reduces the parasitic capacitance of the loop and parallel capacitance is added to achieve resonance at the frequency required. In our case around 400pF and a 60pF adjustable capacitor were used to tune to 909kHz • An adapter was used to adapt from the SMA output of the DAC and a 3.5mm jack socket to connect a headset (or speakers) Assemble loop aerial and headset connection This is the title of the slide and the date it was written Slide 13
- 14. • Open the web site http://koheron/ if connected on the same subnet. Find the ip address by typing: nslookup koheron on a local machine if wishing to connect to it remotely. • The web page will allow the configuration parameters to be set and the status values to be read. • Test other functionality using python test programs, such as in the examples. • For streaming of large volumes of fast data, the python program could be run on the Zynq ARM and connecting to 127.0.0.1 • For high bandwidth data acquisition, the FPGA program should store directly to DDR and the ARM read the data post-shot (via DMA or direct write through a memory interface ‘MIG’ on the PL part of the Zynq). Hands-on video at: Files required for this design at: https://my.pcloud.com/publink/show?code=kZhxrAZ8srvxsa0SKBTue6ITJDmvySgGXkX Test the instrument Slide 14
- 15. Download SD card image from Koheron site and extract to a .img file. Insert SD card and unmount: sudo fdisk –l (To find name of drive eg /dev/mmcbkl0 ) sudo umount /dev/mmcbkl0 (or whatever drive name from above) Copy image on to SD card: sudo dd if=/dev/mmcblk0 of=……/<sd-card-copy>.img Copying file to SD card using dd on Linux This is the title of the slide and the date it was written Slide 15
- 16. • Index.html at /usr/local/www on Koheron instrument target • Type script pages (.ts files) defined on development machine in <instrumentName>/web and listed in app.ts are zipped (by the make process) and sent over to the target and compiled in to app.js at run time for the live instrument in /tmp/live-instrument/ on the target to provide an interactive web page. Web interface This is the title of the slide and the date it was written Slide 16
- 17. • Currently 3 hands on videos are available: i) Looking round the Koheron-SDK ii) Building the Software Defined Radio in IP integrator iii) Building the SDR instrument using Make files and testing using a simple client application iv) Web interface (TBD) Tutorial videos This is the title of the slide and the date it was written Slide 17