Distortion Analysis of Differential Amplifier

IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)
e-ISSN: 2278-2834,p- ISSN: 2278-8735.Volume 6, Issue 6 (Jul. - Aug. 2013), PP 45-51
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Distortion Analysis of Differential Amplifier
Ms. Archana Y. Patil, Prof. Ms. S. B. Patil
(Dept. of E&TC, Sinhgad College of Engineering, Pune University,India)
(Dept. of E&TC, Sinhgad College of Engineering, Pune University, India)
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper
the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog
integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic
distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that
can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3
SPICE model from 0.13-µm CMOS process technology. HSPICE circuit simulator tool is used for distortion
analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source
capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with
simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-
channel effects, small signal analysis, transient analysis.
I. Introduction
The rise in use of MOS devices in analog circuit design is because of its high linearity feature i.e. low
distortion behaviour. But, distortion is a key measure of performance for CMOS circuits, because in saturated
MOS transistors the drain current approximately depends on the square of the gate-source voltage. Therefore,
circuits made up with MOS transistors or, more generally, with real active components exhibit a certain amount
of nonlinearity, and this means that the relationship between their input and the output variables is not so ideally
linear. Distortion is one of the most important undesired effects that appear in analog circuits due to non-
linearities in the characteristics of the transistors or from the influence of the associated circuit (coupling
component or load). The main goal of this project is to build a mechanism to analyze the distortion of CMOS
circuits in deep submicron technology that can be easily used to detect the distortion. In analog integrating
circuits, replacing the bipolar transistors with MOS transistors, the problem of relatively large values of the
input bias, input offset currents and of the small value of the input impedance was solved, with the disadvantage
of reducing the voltage gain caused by the quadratic characteristic of the MOS transistor working in saturation
region. This fact reveals the problem of applied input voltage levels. As the technology is now shrink to
nanometer range, there are some additional problems arise due to short channel effects such as body effects,
channel-length modulations, signal-dependent capacitive effects and frequency-dependent distortions arising
from the capacitive load in the CMOS circuits.
The first step is to select the CMOS circuits on which distortion analysis will be performed and
determine the parameters responsible for distortion in the circuits. This step has been completed in literature
survey process. The next step is to check the applicability of MOSFET models, which are compatible in deep
submicron technology. This issue has been also solved by choosing the TSMC MOSFET models. The next step
is to do correct coding of CMOS circuits by considering different parameters such as input biasing voltage,
supply voltage, operating frequency range, load value, working temperature etc. and simulate the circuits on the
required tools. The simulated results should be validated with theoretical one
The proposed CMOS circuit on which distortion analysis will be performed is CMOS Differential Amplifier
Circuit.
The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-µm CMOS process
technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits.
II. Literature Review
As the technology is shrinking to nanometer range, different techniques have been proposed by
different designers for distortion analysis of CMOS circuits and for finding linearization techniques based on the
same. To minimize the distortion, a linearization technique for CMOS differential amplifiers based on the
compensation of the quadratic characteristic of the MOS transistor is proposed in [1]. The non-linearity of the
circuit has been evaluated by using an expansion in Taylor series of the amplifier transfer function. This
technique reduces the distortion only up to 8dB. The harmonic distortion of the conventional NMOS source
follower and PMOS source follower are thoroughly analyzed using a simplified large-signal model in

Distortion Analysis Of Differential Amplifier
conjunction with Level49 BSIM3 model equations and assumptions in [2]. Based on this analysis, a new
linearization technique of the cascade-complementary source follower is proposed. Comparative study of three
different current mirror circuits has been done in [3]. Performance parameter including total harmonic distortion
was calculated. Results are validated in 90nm CMOS technology. In [4], a high frequency low voltage low
power tunable highly linear transconductor is presented. Shift level biasing is used at the inputs of both the
amplifiers of a cross coupled differential pair for tuning. Bias currents of cross coupled differential amplifiers
are adjusted to cancel third harmonic distortion. Author simulated the proposed circuit in Cadence VIRTUOSO
with 0.18-µm CMOS process technology.
III. Theory of Amplifiers
Conventionally passive loads such resistors are used in amplifier circuits, but it have some drawback.
The main drawback is to achieve large voltage gain, IDRD product must be made large, which in turn requires a
large power-supply voltage. Furthermore, large values of resistors are required when low current is used to limit
the power dissipation. As a result, the required die area for the resistors can be large, which is practically very
difficult to implement in nanometer technology range. To overcome this problem and provide large gain a
transistor is used as load element which is also called as active load.
There are mainly three types of active load configurations used in amplifiers:
1.Complementary load or current source/sink active load,
2. Depletion load,
3. Diode connected load.
CMOS current mirror circuits are as complementary load, n-channel or p-channel depletion type
transistors are used as depletion load and NMOS or PMOS transistors with gate is shorted to drain terminal is
used as diode connected load. Amplifiers with current source/sink active loads tend to achieve higher gain due
to the high output impedance, but at the expense of bandwidth. Amplifiers with gate-drain connected active
loads tend to achieve large frequency bandwidths but low gain due to their relatively low output impedance.
IV. Cmos Differential Amplifier With Current Mirror Load
An active load acts as a current source. Thus it must be biased such that their currents add up exactly to
Ibias
. In practice this is quite difficult. Thus a feedback circuit is required to ensure this equality. This is achieved
by using a current mirror circuit as load, as in Fig1.
Figure 1. Schematic of Differential Amplifier with current mirror load
The current mirror consists of transistor M3 and M4. One transistor (M3) is always connected as diode
and drives the other transistor (M4). Since VGS3
=VGS4
, if both transistors have the same β, then the current ID3
is
mirrored to ID4
, i.e., ID3
=ID4
. The advantage of this configuration is that the differential output signal is converted
to a single ended output signal with no extra components required. In this circuit, the output voltage or current is
taken from the drains of M2 and M4. The operation of this circuit is as follows:
Small Signal Analysis
The small signal analysis of differential amplifier can be accomplished with the assistance of the model
shown in Fig2, which is only appropriate for differential analysis when both sides of the amplifier are assumed
to be perfectly matched. If this condition is satisfied, then the point where the sources of M1 and M2 are
connected can be considered at AC ground. The body effect is neglected.

Output Resistance (rout)
The evaluation of the output resistance, rout, is determined by using the small-signal equivalent circuit
and applying a voltage to the output node, as seen in Fig. 2. Note that the T model was used for both M1 and
M2, whereas M3 was replaced by an equivalent resistance (since it is diode-connected), and the hybrid-𝜋 model
was used for M4.
Figure 2. Small-signal model for the calculation of output resistance
As usual, rout is defined as the ratio Vx/ix, where ix is given by the sum ix = ix1 + ix2+ ix3+ix4.
Clearly,
i 𝑥1 =
V 𝑥
r 𝑑𝑠4
(1)
Implying that the resistance seen in the path taken by ixl is equal to rds4. Now, assuming that the effect
of rdsl can be ignored (since it-is much larger than rs1), we see that the current ix2 is given by
i 𝑥2 ≅
V 𝑥
r 𝑑𝑠2+ r 𝑠1∥r 𝑠2
≅
V 𝑥
r 𝑑𝑠2
(2)
where the second approximation is valid, since rds2 is typically much greater than rs1║rs2. This ix2 current splits
equally between is1and is2 (assuming rs1= rs2 and once again ignoring rds1), resulting in
i 𝑠1 = i 𝑠2 =
−V 𝑥
2r 𝑑𝑠2
(3)
However, since the current mirror realized by M3 and M4 results in ix4 = ix5 (assuming gm4 = l/rs4 = 1/rs3
and rds3 is much larger than rs3), the current ix4 is given by
i 𝑥4 = −i 𝑠1 = −i 𝑠2 = −i 𝑥3 (4)
In other words, when the current splits equally between rs1 and rs2, the current mirror of M3 and M4
causes the two currents ix3 and ix4 to cancel each other. Finally, the output resistance, rout, is given by
r 𝑜𝑢𝑡 =
V𝑥
i 𝑥1 + i 𝑥2 + i 𝑥3 + i 𝑥4
=
V𝑥
V𝑥 r 𝑑𝑠4 + V𝑥 r 𝑑𝑠2
which results in the simple relationship
r 𝑜𝑢𝑡 = r 𝑑𝑠2 ∥ r 𝑑𝑠4 (5)
Low frequency voltage gain (Av)
Figure 3. Small signal model of differential pair with current mirror load
Since, 𝑣g𝑠3 = 𝑣g𝑠4
The voltage vgs4 can be calculated from above small signal model as
𝑣g𝑠4 = −g 𝑚1
𝑣𝑖𝑑
2
1
g 𝑚 3
r 𝑑𝑠1 r 𝑑𝑠3 (6)

Since, r 𝑑𝑠1 andr 𝑑𝑠3 ≫
1
g 𝑚3
Therefore the above equation reduces to
𝑣g𝑠4 = −
g 𝑚 1
g 𝑚 3
𝑣𝑖𝑑
2
(7)
This voltage controls the drain current of M4 resulting in a current of g 𝑚4 𝑣g𝑠4.
Thus the output current 𝑖 𝑜𝑢𝑡 will be
𝑖 𝑜𝑢𝑡 = −g 𝑚4 𝑣g𝑠4 + g 𝑚2
𝑣𝑖𝑑
2
(8)
Substituting for 𝑣g𝑠4 from equation (7) gives
𝑖 𝑜𝑢𝑡 = g 𝑚1
g 𝑚 4
g 𝑚 3
𝑣𝑖𝑑
2
+ g 𝑚2
𝑣𝑖𝑑
2
(9)
Now, since g 𝑚3 = g 𝑚4andg 𝑚1 = g 𝑚2 = g 𝑚 ,the current 𝑖 𝑜𝑢𝑡 becomes
𝑖 𝑜𝑢𝑡 = g 𝑚 𝑣𝑖𝑑(10)
Now the small signal output voltage is simply:
𝑣 𝑜𝑢𝑡 = 𝑖 𝑜𝑢𝑡 ∙ r 𝑜𝑢𝑡
𝑣 𝑜𝑢𝑡 = g 𝑚 𝑣𝑖𝑑 ∙ r 𝑑𝑠2 ∥ r 𝑑𝑠4 (11)
Therefore, the voltage gain will be
A 𝑣 =
𝑣 𝑜𝑢𝑡
𝑣𝑖𝑑
= g 𝑚 ∙ 𝑟𝑑𝑠2 ∥ 𝑟𝑑𝑠4 (12)
This result assumes that the output impedance is purely resistive. If there is also a capacitive load, CL, then the
gain is given by
A 𝑣 =
𝑣 𝑜𝑢𝑡
𝑣𝑖𝑑
= g 𝑚 ∙ 𝑧 𝑜𝑢𝑡 (13)
where 𝑧 𝑜𝑢𝑡 = r 𝑜𝑢𝑡 ∥ 1 sC 𝐿.
DC Analysis-Large signal model
The differential pair in Fig. 3 is biased with a current source so that
I 𝑏𝑖𝑎𝑠 = I 𝑑1 + I 𝑑2(14)
If we label the input voltages at the gates of Ml and M2 as V𝑖1and V𝑖2, we can write the input difference as
V𝑑𝑖 = V𝑖1 − V𝑖2 = Vg𝑠1 − Vg𝑠2
or in terms of the AC and DC components of the differential input voltage,V𝑑𝑖 ,
V𝑑𝑖 = V𝐺𝑆1 + 𝑣g𝑠1 − V𝐺𝑆2 − 𝑣g𝑠2 (15)
When the gate potentials of Ml and M2 are equal, then (assuming both are operating in the saturation region)
I 𝐷1 = I 𝐷2 = I 𝑏𝑖𝑎𝑠 2(16)
Maximum and Minimum Differential Input Voltage
Since we know that a saturated MOSFET follows the relation
I 𝑑 =
β 𝑛
2
(Vg𝑠 − V𝑡ℎ𝑛 )2
(17)
The difference in the input voltages may be written as
V𝑑𝑖 =
2
β 𝑛
I 𝑑1 − I 𝑑2 (18)
The maximum difference in the input voltages, V𝑑𝑖𝑚𝑎𝑥 (maximum differential input voltage), is found by setting
I 𝑑1to I 𝑏𝑖𝑎𝑠 (Ml conducting all of the tail bias current) and I 𝑑2to 0 (M2 off)
V𝑑𝑖𝑚𝑎𝑥 < V𝑖1 − V𝑖2 =
2∙L∙I 𝑏𝑖𝑎𝑠
k′∙W
(19)
The minimum differential input voltage, V𝑑𝑖𝑚𝑖𝑛 , is found by setting I 𝑑2to I 𝑏𝑖𝑎𝑠 and I 𝑑1to 0
V𝑑𝑖𝑚𝑖𝑛 = −V𝑑𝑖𝑚𝑎𝑥 = − V𝑖1 − V𝑖2 = −
2∙L∙I 𝑏𝑖𝑎𝑠
k′∙W
(20)
Maximum and Minimum Differential Output Voltage
The large signal swing limitations of the output are also of interest. In this case, the swing limitations
will be based on keeping both M2 and M4 in saturation.When VGS1 is taken above VGS2, the output voltage,
VOUT, increases. Therefore,
V𝑂𝑈𝑇 𝑚𝑎𝑥 = V𝐷𝐷 − V𝑆𝐷4,𝑠𝑎𝑡
= V𝐷𝐷 − V𝑆𝐺3 − V𝑡ℎ𝑝,4
= V𝐷𝐷 −
2I 𝐷1
k′ ∙ W
L
+ V𝑡ℎ𝑝,3 + V𝑡ℎ𝑝,4

V𝑂𝑈𝑇 𝑚𝑎𝑥 = V𝐷𝐷 −
I 𝑏𝑖𝑎𝑠
k′∙
W
L
(21)
The minimum output voltage is determined by the voltage on the gate of M2 (M2 must remain in saturation).
V𝑂𝑈𝑇 𝑚𝑖𝑛 = V𝐼2 − V𝑡ℎ𝑛,2 (22)
HarmonicDistortion in CMOS Differential Amplifier
Differential circuits exhibit an odd-symmetric input/output characteristics, i.e., f(-x) =-f(x). For the
Taylor expansion to be an odd function, all of the even-order terms must be zero:
𝑦 𝑡 = 𝛼1 𝑥 𝑡 + 𝛼3 𝑥3
𝑡 + ⋯ (23)
The above equation indicates that a differential circuit driven by a differential signal produces no even
harmonics. This is very important property of differential operation.
The most common approach of a differential amplifier in CMOS technology is based on strong-
inverted MOS transistors (usually working in the saturation region). As a result of the quadratic characteristic of
a MOS transistor operating in saturation, the transfer characteristic of the classical CMOS differential amplifier
will be strongly nonlinear, its linearity being in reasonable limits only for a very limited range of the
V. Result &Conclusion
The design parameters are given as follows:
Positive supply voltage = +1.2V,
Negative supply voltage = -1.2V
W/L ratio of driver transistors (M1 & M2) = 25,
W/L ratio of load transistors (M3 & M4) = 25,
Input bias voltage = 0.6V,
Input voltage signal level = 10mV,
Biasing current source = 100µA,
Load capacitance = 0.05pF,
Operating frequency = 10MHz.
1. Transient Analysis:
The transient analysis of CMOS differential amplifier with current mirror load shows that
output voltage signal is in same phase and amplified version of input voltage signal.
Figure 4. Transient response waveform of CMOS differential amplifier with current mirror load
2. FFT Analysis:
Figure 5. Output voltage (dB) vs. Frequency (MHz) curve of CMOS differential amplifier

This analysis shows the value of output voltage signal at fundamental frequency and its harmonics at
the multiple of fundamental frequency. The waveform of FFT analysis shows that the value of 3rd
harmonic is
greater than the 2nd
harmonic, which means 3rd
harmonic is dominated in CMOS differential amplifier. The 3rd
harmonic term is mainly responsible for distortion in CMOS differential amplifier.
3. AC Analysis:
Figure 6. Voltage gain vs. Frequency waveform of CMOS differential amplifier
Table 1. Summary of results obtained from AC analysis
S.No. Parameters Calculated Simulated
1. Small Signal Voltage Gain 14.73 or 23.36 dB 14.61 or 23.29 dB
2. 3-dB Cut-off Frequency 143.47 MHz 137 MHz
3. Unity Gain Frequency (GBW) 2.11 GHz 1.89 GHz
4. Harmonic Distortion Analysis:
Table 2. Total harmonic distortion vs. Peak to peak input voltage signal level
S.NO.
Peak to peak input voltage
signal level
(mV )
THD(dB)
Calculated
THD(dB)
Simulated
1. 10 -56.38 -45.31
2. 20 -44.34 -44.26
3. 30 -37.30 -43.87
4. 40 -32.30 -37.85
5. 50 -28.42 -33.15
6. 60 -25.25 -28.33
7. 70 -22.58 -24.66
8. 80 -20.26 -21.98
9. 90 -18.21 -19.95
10. 100 -16.38 -18.40
Figure 7.Total harmonic distortion vs. Peak to peak input voltage signal level
The allowable input voltage signal level for CMOS Differential Amplifier using above design
parameters is 20mV (Calculated) and 30mV (Simulated) for which THD is below the 1%.
Table 3. Simulated Results for Total harmonic distortion vs. Frequency
S.NO. FREQUENCY (MHz )
Total Harmonic
Distortion (dB)
1. 0.1 -51.9094
2. 0.5 -51.8886
3. 1 -51.806
4. 2 -51.4863
5. 3 -51.0261
6. 4 -50.4915
7. 5 -49.9296
8. 6 -49.3693
9. 7 -48.8277
10 20 30 40 50 60 70 80 90 100
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
Peak to peak input voltage signal level (mV)
TotalHarmonicDistortion(dB)
THD(Calculated)
THD(Simulated)

10. 8 -48.312
11. 9 -47.8264
12. 10 -47.3711
13. 20 -44.1371
14. 30 -42.2842
15. 40 -41.0659
16. 50 -40.1891
17. 60 -39.5234
18. 70 -38.9815
19. 80 -38.5403
20. 90 -38.1673
21. 100 -37.8456
Figure 8. Total harmonic distortion vs. Frequency graph of CMOS differential amplifier
The frequency range for which Total Harmonic Distortion is below the 1% is 50MHz for CMOS
Differential Amplifier designed using above parameters.
VI. Future Scope
This project is mainly concentrated on harmonic distortion analysis. So, future work should be put into
investigating the effect of inter-modulation and phase distortion.The downscaling of transistor sizes to
submicron regions continues and modifies the square-law I-V characteristic of MOS devices. Short channel
effects, such as body-effect, channel length modulation, velocitysaturation and mobility reduction, arise and
change the square-law relation to a morelinear characteristic.This will affect the nonlinear behavior of analog
integrated circuits. In this project, body-effect is considered on hand calculation of the measurement of
distortion. Thus it is recommended that another short channel effects should be include in measurement so that a
more clear picture of distortion analysis should be develop and the difference between calculated results and
simulated results will be minimized.The more complicated analog circuits such as operational amplifier, analog
to digital converter, mixers and low noise amplifier should be choose for distortion analysis. The presented
circuit topology was implemented in a 130nm CMOS process. It is also of great interest to investigate the
nonlinear behavior in different processtechnologies, such as 90nm, 45nm and even belowCMOS process,
silicon-germanium BiCMOS process,gallium-arsenide or a process using silicon-on-insulator technology.
References
[1] P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, Inc, 2001
[2] B. Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw-Hill, 2002.
[3] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Oxford Univ. Press, 2nd
edition2002.
[4] P.Wambacq and W.Sansen,Distortion Analysis of Analog Integrated Circuits. Norwel, MA:Kluwer,1998.
[5] C. Popa, “Linearity Evaluation Technique for CMOS Differential Amplifier”, 26th International Conference on Microelectronics
(MIEL 2008)NIS, Serbia , 11-14 May, 2008.
[6] Xianping Fan and P. K. Chan, “Analysis and Design of Low-Distortion CMOS Source Followers”, IEEE Transactions on Circuits
and Systems—I: Regular Papers, vol. 52, no. 8, August 2005.
[7] MelitaPennisi, Gaetano Palumbo and Ramon Gonzalez Carvajal, “Analysis and comparison of class AB current mirror OTAs”,
Springer Science Business Media, 24 October 2010.
[8] VijayaBhadauria, Krishna Kant, Swapna Banerjee, “A TunableTransconductor With High Linearity”, Circuits and Systems
(APCCAS), 2010 IEEE Asia Pacific Conference onKuala Lumpur, pp.5 – 8, 6-9 Dec. 2010.
[9] Mollaalipour, M., Naimi, H. M. “Volterra series analysis of down conversion CMOS mixer with high IIP2 and IIP3”, IEEE Trans.
on Cricuits and systems, pp. 201-204, Sept 2012
[10] Avant, Star-Hspice Manual, 1998.
[11] Synopsys, HSPICE User Guide Manual, Version A-2008.03, March 2008.
[12] Department of Electrical Engineering and Computer Sciences University of California, Berkeley, “BSIM3v3.3 Users' Manual,”
2005.
0 10 20 30 40 50 60 70 80 90 100
-54
-52
-50
-48
-46
-44
-42
-40
-38
-36
Frequency(MHz)
TotalHarmonicDistortion(dB)

Distortion Analysis of Differential Amplifier

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