1. Edge Detection using 4 Bit MAC on Basys3 FPGA
Subject: FPGA -21ES612
Gokul - CB.EN.P2EBS24009
Shravan Ramesh - CB.EN.P2EBS24020
Amrita School of Engineering, Coimbatore Amrita
Vishwa Vidyapeetham
February 14, 2025
2. Outline
1. Objectives
2. Literature Revie
w
3. Methodology
4. Partial Result
5. References
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3. Objectives
• To implement a 4-bit MAC (Multiply-Accumulate) unit using in-memory computing
for efficient edge detection in images on an FPGA.
• Compare performance of FPGA using in memory and using LUT based process.
• Perform MAC-based Sobel filtering inside memory (BRAM) instead of using
external processing logic
• Perform MAC-based Sobel filtering inside memory (LUT’S) instead of using
external processing logic
• Validate the system by displaying processed images on an FPGA-
connected monitor.
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4. Outline
1. Objectives
2. Literature Revie
w
3. Methodology
4. Partial Result
5. References
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5. Literature Review
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Title/Year Key Findings
Performance Analysis of Multiplier
with Different Bits Size for MAC unit-
2024
The analysis could help in selecting or designing a multiplier that is
specifically optimized for 4-bit precision, which is often sufficient for
low-resolution image processing tasks.
An Efficient Softcore Multiplier
Architecture for Xilinx FPGAs-2015
The architecture could be modified or scaled down to handle 4-bit data,
ensuring that the multiplier is both area-efficient and fast, which is
important for real-time image processing applications.
Image Display using FPGA with
BRAM and VGA Interface for
Multimedia Applications-2023
For 4-bit image processing, the paper could provide valuable
information on how to store and retrieve 4-bit image data efficiently
from BRAM, as well as how to interface with a VGA display
Implementation of Sobel Edge
Detection with Image Processing on
FPGA-2024
For 4-bit image processing, the paper could provide insights into how to
adapt the Sobel algorithm to work with 4-bit data, ensuring that the
edge detection is both accurate and efficient.
6. Outline
1. Objectives
2. Literature Revie
w
3. Methodology
4. Partial Result
5. References
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7. Methodology
Image Preprocessing and Memory Mapping
• A grayscale image is converted into a binary memory file (image.mem) using a
Python script.
Storing Image in Block RAM (BRAM):
• In the IMC-based approach, the image is loaded into BRAM where all operations
occur.
• In the LUT-based approach, image data is stored in registers and processed through
logic gates.
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8. Methodology
Implementing 4-Bit MAC Unit
• The MAC operation (Multiply and Accumulate) is used to perform convolution for edge
detection.
Implementing Edge Detection Using Sobel Filter
• IMC-Based: The Sobel kernel coefficients are stored in BRAM, and convolution is
performed inside memory.
• LUT-Based: The image pixels are fetched into LUTs, processed through
combinational logic, and stored back.
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9. Outline
1. Objectives
2. Literature Revie
w
3. Methodology
4. Partial Result
5. References
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11. Outline
1. Objectives
2. Literature Revie
w
3. Methodology
4. Partial Result
5. References
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12. References
• 1. Implementation of Sobel Edge Detection with Image Processing on FPGA
• Priyanka, V., Sri Rama, Y., Sravani, K., & Kavya, B. (2024). Implementation of Sobel edge detection with image processing on FPGA. In 2024
IEEE International Conference on Emerging Technologies and Applications (ICETA). IEEE. https://doi.org/10.1109/ICETA.2024.XXXXXXX
• 2. Image Display using FPGA with BRAM and VGA Interface for Multimedia Applications
• Navaneethan, S., Nath, S. S., Krishnan, U., Krishna, L., Sakthekannan, M. S., & Yogavignes, B. M. (2023). Image display using FPGA with
BRAM and VGA interface for multimedia applications. In 2023 8th International Conference on Communication and Electronics Systems (ICCES)
(pp. 77-83). IEEE. https://doi.org/10.1109/ICCES57224.2023.XXXXXXX
• 3. An Efficient Softcore Multiplier Architecture for Xilinx FPGAs
• Kumm, M., Abbas, S., & Zipf, P. (2015). An efficient softcore multiplier architecture for Xilinx FPGAs. In 2015 IEEE 22nd Symposium on
Computer Arithmetic (pp. 1-8). IEEE. https://doi.org/10.1109/ARITH.2015.22
• 4. Performance Analysis of Multiplier with Different Bits Size for MAC Unit
• Anuraj, V., & Vaithiyanathan, D. (2024). Performance analysis of multiplier with different bits size for MAC unit. In 2024 IEEE International
Conference on Emerging Technologies and Applications (ICETA). IEEE. https://doi.org/10.1109/ICETA.2024.XXXXXXX
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