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Introduction to
Electronics
An Online Text
Bob Zulinski
Associate Professor
of Electrical Engineering
Michigan Technological University
Version 2.0

Introduction to Electronics ii
Dedication
Human beings are a delightful and complex amalgam of
the spiritual, the emotional, the intellectual, and the physical.
This is dedicated to all of them; especially to those
who honor and nurture me with their friendship and love.

Introduction to Electronics iii
Table of Contents
Preface xvi
Philosophy of an Online Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi
Notes for Printing This Document . . . . . . . . . . . . . . . . . . . . . . . . xviii
Copyright Notice and Information . . . . . . . . . . . . . . . . . . . . . . . . xviii
Review of Linear Circuit Techniques 1
Resistors in Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Resistors in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Over Sum 1
Inverse of Inverses 1
Ideal Voltage Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ideal Current Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Real Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Voltage Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Current Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Superposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
A quick exercise 4
What’s missing from this review??? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
You’ll still need Ohm’s and Kirchoff’s Laws 5
Basic Amplifier Concepts 6
Signal Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ground Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
To work with (analyze and design) amplifiers . . . . . . . . . . . . . . . . . . . . . 7
Voltage Amplifier Model 8
Signal Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Amplifier Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Amplifier Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Open-Circuit Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Introduction to Electronics iv
Power Supplies, Power Conservation, and Efficiency 11
DC Input Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Conservation of Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Amplifier Cascades 13
Decibel Notation 14
Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Cascaded Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Current Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Using Decibels to Indicate Specific Magnitudes . . . . . . . . . . . . . . . . . . . 15
Voltage levels: 15
Power levels 16
Other Amplifier Models 17
Current Amplifier Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Transconductance Amplifier Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transresistance Amplifier Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Amplifier Resistances and Ideal Amplifiers 20
Ideal Voltage Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Ideal Current Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ideal Transconductance Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Ideal Transresistance Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Uniqueness of Ideal Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Frequency Response of Amplifiers 24
Terms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Magnitude Response 24
Phase Response 24
Frequency Response 24
Amplifier Gain 24
The Magnitude Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Causes of Reduced Gain at Higher Frequencies . . . . . . . . . . . . . . . . . . 26
Causes of Reduced Gain at Lower Frequencies . . . . . . . . . . . . . . . . . . 26

Introduction to Electronics v
Differential Amplifiers 27
Example: 27
Modeling Differential and Common-Mode Signals . . . . . . . . . . . . . . . . . 27
Amplifying Differential and Common-Mode Signals . . . . . . . . . . . . . . . . 28
Common-Mode Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ideal Operational Amplifiers 29
Ideal Operational Amplifier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Op Amp Operation with Negative Feedback . . . . . . . . . . . . . . . . . . . . . 30
Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Op Amp Circuits - The Inverting Amplifier 31
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Op Amp Circuits - The Noninverting Amplifier 33
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Input and Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Op Amp Circuits - The Voltage Follower 34
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Input and Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Op Amp Circuits - The Inverting Summer 35
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Op Amp Circuits - Another Inverting Amplifier 36
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Op Amp Circuits - Differential Amplifier 38
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Op Amp Circuits - Integrators and Differentiators 40
The Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
The Differentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Introduction to Electronics vi
Op Amp Circuits - Designing with Real Op Amps 42
Resistor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Source Resistance and Resistor Tolerances . . . . . . . . . . . . . . . . . . . . . 42
Graphical Solution of Simultaneous Equations 43
Diodes 46
Graphical Analysis of Diode Circuits 48
Examples of Load-Line Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Diode Models 50
The Shockley Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Forward Bias Approximation 51
Reverse Bias Approximation 51
At High Currents 51
The Ideal Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
An Ideal Diode Example 53
Piecewise-Linear Diode Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A Piecewise-Linear Diode Example 57
Other Piecewise-Linear Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Diode Applications - The Zener Diode Voltage Regulator 59
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Load-Line Analysis of Zener Regulators . . . . . . . . . . . . . . . . . . . . . . . . 59
Numerical Analysis of Zener Regulators . . . . . . . . . . . . . . . . . . . . . . . . 61
Circuit Analysis 62
Zener Regulators with Attached Load . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Example - Graphical Analysis of Loaded Regulator 64
Diode Applications - The Half-Wave Rectifier 66
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
A Typical Battery Charging Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
The Filtered Half-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Relating Capacitance to Ripple Voltage 70

Introduction to Electronics vii
Diode Applications - The Full-Wave Rectifier 72
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
1st
(Positive) Half-Cycle 72
2nd
(Negative) Half-Cycle 72
Diode Peak Inverse Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Diode Applications - The Bridge Rectifier 74
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
1st
(Positive) Half-Cycle 74
2nd
(Negative) Half-Cycle 74
Peak Inverse Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Diode Applications - Full-Wave/Bridge Rectifier Features 75
Bridge Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Full-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Filtered Full-Wave and Bridge Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . 75
Bipolar Junction Transistors (BJTs) 76
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Qualitative Description of BJT Active-Region Operation . . . . . . . . . . . . 77
Quantitative Description of BJT Active-Region Operation . . . . . . . . . . . 78
BJT Common-Emitter Characteristics 80
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Input Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Active Region 81
Cutoff 82
Saturation 82
The pnp BJT 83
BJT Characteristics - Secondary Effects 85

Introduction to Electronics viii
The n-Channel Junction FET (JFET) 86
Description of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Equations Governing n-Channel JFET Operation . . . . . . . . . . . . . . . . . 89
Cutoff Region 89
Triode Region 89
Pinch-Off Region 89
The Triode - Pinch-Off Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
The Transfer Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Metal-Oxide-Semiconductor FETs (MOSFETs) 92
The n-Channel Depletion MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
The n-Channel Enhancement MOSFET . . . . . . . . . . . . . . . . . . . . . . . . 93
Comparison of n-Channel FETs 94
p-Channel JFETs and MOSFETs 96
Cutoff Region 98
Triode Region 98
Pinch-Off Region 98
Other FET Considerations 99
FET Gate Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
The Body Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Basic BJT Amplifier Structure 100
Circuit Diagram and Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Load-Line Analysis - Input Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Load-Line Analysis - Output Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
A Numerical Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Basic FET Amplifier Structure 107
Amplifier Distortion 110
Biasing and Bias Stability 112

Introduction to Electronics ix
Biasing BJTs - The Fixed Bias Circuit 113
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
For b = 100 113
For b = 300 113
Biasing BJTs - The Constant Base Bias Circuit 114
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
For b = 100 114
For b = 300 114
Biasing BJTs - The Four-Resistor Bias Circuit 115
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Bias Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
To maximize bias stability 117
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
For b = 100 (and VBE = 0.7 V) 118
For b = 300 118
Biasing FETs - The Fixed Bias Circuit 119
Biasing FETs - The Self Bias Circuit 120
Biasing FETs - The Fixed + Self Bias Circuit 121
Design of Discrete BJT Bias Circuits 123
Concepts of Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Design of the Four-Resistor BJT Bias Circuit . . . . . . . . . . . . . . . . . . . . 124
Design Procedure 124
Design of the Dual-Supply BJT Bias Circuit . . . . . . . . . . . . . . . . . . . . . 125
Design of the Grounded-Emitter BJT Bias Circuit . . . . . . . . . . . . . . . . 126
Analysis of the Grounded-Emitter BJT Bias Circuit . . . . . . . . . . . . . . . 127

Introduction to Electronics x
Bipolar IC Bias Circuits 129
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
The Diode-Biased Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Current Ratio 130
Reference Current 131
Output Resistance 131
Compliance Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Using a Mirror to Bias an Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Wilson Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Current Ratio 133
Reference Current 134
Output Resistance 134
Widlar Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Current Relationship 135
Multiple Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
FET Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Linear Small-Signal Equivalent Circuits 138
Diode Small-Signal Equivalent Circuit 139
The Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
The Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Diode Small-Signal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Notation 142
BJT Small-Signal Equivalent Circuit 143
The Common-Emitter Amplifier 145
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Constructing the Small-Signal Equivalent Circuit . . . . . . . . . . . . . . . . . 146
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Introduction to Electronics xi
The Emitter Follower (Common Collector Amplifier) 149
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Review of Small Signal Analysis 153
FET Small-Signal Equivalent Circuit 154
The Small-Signal Equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
FET Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
The Common Source Amplifier 157
The Small-Signal Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
The Source Follower 159
Small-Signal Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Review of Bode Plots 164
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
The Bode Magnitude Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
The Bode Phase Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Single-Pole Low-Pass RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Gain Magnitude in dB 167
Bode Magnitude Plot 168
Bode Phase Plot 169
Single-Pole High-Pass RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Bode Magnitude Plot 170
Bode Phase Plot 171

Introduction to Electronics xii
Coupling Capacitors 172
Effect on Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Constructing the Bode Magnitude Plot for an Amplifier . . . . . . . . . . . . 174
Design Considerations for RC-Coupled Amplifiers 175
Low- & Mid-Frequency Performance of CE Amplifier 176
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Midband Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
The Effect of the Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . 179
The Effect of the Emitter Bypass Capacitor CE . . . . . . . . . . . . . . . . . . 180
The Miller Effect 183
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Deriving the Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
The Hybrid-p BJT Model 185
The Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Effect of Cp and Cm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
High-Frequency Performance of CE Amplifier 189
The Small-Signal Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
High-Frequency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
The CE Amplifier Magnitude Response . . . . . . . . . . . . . . . . . . . . . . . . 192
Nonideal Operational Amplifiers 193
Linear Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Input and Output Impedance 193
Gain and Bandwidth 193
Nonlinear Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Output Voltage Swing 194
Output Current Limits 194
Slew-Rate Limiting 194
Full-Power Bandwidth 195

Introduction to Electronics xiii
DC Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Input Offset Voltage, VIO 195
Input Currents 195
Modeling the DC Imperfections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Using the DC Error Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
DC Output Error Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Finding Worst-Case DC Output Error 201
Canceling the Effect of the Bias Currents . . . . . . . . . . . . . . . . . . . . . . 203
Instrumentation Amplifier 204
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Simplified Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Noise 206
Johnson Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Johnson Noise Model 207
Shot Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
1/f Noise (Flicker Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Other mechanisms producing 1/f noise 209
Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Amplifier Noise Performance 211
Terms, Definitions, Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Amplifier Noise Voltage 211
Amplifier Noise Current 212
Signal-to-Noise Ratio 212
Noise Figure 213
Noise Temperature 213
Converting NF to/from Tn 214
Adding and Subtracting Uncorrelated Quantities . . . . . . . . . . . . . . . . . 214
Amplifier Noise Calculations 215
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Calculating Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Typical Manufacturer’s Noise Data 217
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Example #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Example #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Introduction to Electronics xiv
Noise - References and Credits 220
Introduction to Logic Gates 221
The Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
The Ideal Case 221
The Actual Case 221
Manufacturer’s Voltage Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 222
Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Manufacturer’s Current Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 223
Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Static Power Consumption 224
Dynamic Power Consumption 224
Rise Time, Fall Time, and Propagation Delay . . . . . . . . . . . . . . . . . . . 226
Speed-Power Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
TTL Logic Families & Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 228
CMOS Logic Families & Characteristics . . . . . . . . . . . . . . . . . . . . . . . 229
MOSFET Logic Inverters 230
NMOS Inverter with Resistive Pull-Up . . . . . . . . . . . . . . . . . . . . . . . . . 230
Circuit Operation 230
Drawbacks 231
CMOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Circuit Operation 232
Differential Amplifier 239
Modeling Differential and Common-Mode Signals . . . . . . . . . . . . . . . . 239
Basic Differential Amplifier Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Case #1 - Common-Mode Input 240
Case #2A - Differential Input 241
Case #2B - Differential Input 241
Large-Signal Analysis of Differential Amplifier 242

Introduction to Electronics xv
Small-Signal Analysis of Differential Amplifier 246
Differential Input Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Analysis of Differential Half-Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Differential Input Resistance 250
Differential Output Resistance 250
Common-Mode Input Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Analysis of Common-Mode Half-Circuit . . . . . . . . . . . . . . . . . . . . . . . . 253
Common-mode input resistance 253
Common-mode output resistance 253
Common-Mode Rejection Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Introduction to Electronics xvi
1
I use the word “supposedly” because, in my view, the official rewards for textbook
authoring fall far short of what is appropriate and what is achievable through an equivalent
research effort, despite all the administrative lip service to the contrary. These arguments,
though, are more appropriately left to a different soapbox.
Preface
Philosophy of an Online Text
I think of myself as an educator rather than an engineer. And it has
long seemed to me that, as educators, we should endeavor to bring
to the student not only as much information as possible, but we
should strive to make that information as accessible as possible,
and as inexpensive as possible.
The technology of the Internet and the World Wide Web now allows
us to virtually give away knowledge! Yet, we don’t, choosing
instead to write another conventional text book, and print, sell, and
use it in the conventional manner. The “whys” are undoubtedly
intricate and many; I offer only a few observations:
G Any change is difficult and resisted. This is true in the habits
we form, the tasks we perform, the relationships we engage.
It is simply easier not to change than it is to change. Though
change is inevitable, it is not well-suited to the behavior of any
organism.
G The proper reward structure is not in place. Faculty are
supposedly rewarded for writing textbooks, thereby bringing
fame and immortality to the institution of their employ.1
The
recognition and reward structure are simply not there for a text
that is simply “posted on the web.”
G No economic incentive exists to create and maintain a

Introduction to Electronics xvii
structure that allows all authors to publish in this manner; that
allows students easy access to all such material, and that
rigorously ensures the material will exceed a minimum
acceptable quality.
If I were to do this the way I think it ought to be done, I would have
prepared the course material in two formats. The first would be a
text, identical to the textbooks with which you are familiar, but
available online, and intended to be used in printed form. The
second would be a slide presentation, à la Corel
Presentations
or Microsoft
PowerPoint
, intended for use in the classroom or in
an independent study.
But, alas, I am still on that journey, so what I offer you is a hybrid of
these two concepts: an online text somewhat less verbose than a
conventional text, but one that can also serve as classroom
overhead transparencies.
Other compromises have been made. It would be advantageous to
produce two online versions - one intended for use in printed form,
and a second optimized for viewing on a computer screen. The two
would carry identical information, but would be formatted with
different page and font sizes. Also, to minimize file size, and
therefore download times, font selection and variations are
somewhat limited when compared to those normally encountered
in a conventional textbook.
You may also note that exercise problems are not included with this
text. By their very nature problems quickly can become “worn out.”
I believe it is best to include problems in a separate document.
Until all of these enhancements exist, I hope you will find this a
suitable and worthwhile compromise.
Enough of this; let’s get on with it...

Introduction to Electronics xviii
Notes for Printing This Document
This document can be printed directly from the Acrobat
Reader -
see the Acrobat
Reader help files for details.
If you wish to print the entire document, do so in two sections, as
most printer drivers will only spool a maximum of 255 pages at one
time.
Copyright Notice and Information
This entire document is 1999 by Bob Zulinski. All rights reserved.
I copyrighted this online text because it required a lot of work, and
because I hold a faint hope that I may use it to acquire
immeasurable wealth, thereby supporting the insatiable, salacious
lifestyle that I’ve always dreamed of.
Thus, you will need my permission to print it. You may obtain that
permission simply by asking: tell me who you are and what you
want it for. Route your requests via email to rzulinsk@mtu.edu, or
by USPS mail to Bob Zulinski, Dept. of Electrical Engineering,
Michigan Technological University, Houghton MI 49931-1295.
Generous monetary donations included with your request will be
looked upon with great favor.

Introduction to Electronics 1Review of Linear Circuit Techniques
R1
R2
Fig. 1.
R’s in series.
R1 R2
Fig. 2.
R’s in parallel.
R R R Rtotal = + + +1 2 3 (1)
R
R R
R R
total =
+
1 2
1 2
(2)
R
R R R
total =
+ + +
1
1 1 1
1 2 3
(3)
Review of Linear Circuit Techniques
Resistors in Series
This is the simple one!!!
Resistors must carry the same current!!!
L’s is series and C’s in parallel have same form.
Resistors in Parallel
Resistors must have the same voltage!!!
Equation takes either of two forms:
Product Over Sum:
Only valid for two resistors. Not calculator-efficient!!!
Inverse of Inverses:
Always valid for multiple resistors. Very calculator-efficient!!!
L’s in parallel and C’s in series have same forms.

+
-
+
-
3 V 5 V
Fig. 3. Ideal voltage
sources in parallel???
Fig. 4. Ideal current
sources in series???
v
i
VOC
ISC
1/RTH
Fig. 5. Typical linear i - v
characteristic of a real source.
v V i R i I
v
R
OC TH SC
TH
= − = −or (4)
Ideal Voltage Sources
Cannot be connected in parallel!!!
Real voltage sources include a series
resistance (“Thevenin equivalent”), and can
be paralleled.
Ideal Current Sources
Cannot be connected in series!!!
Real current sources include a parallel
resistance (“Norton equivalent”), and can be
connected in series.
Real Sources
All sources we observe in nature exhibit a
decreasing voltage as they supply increasing
current.
We presume that i-v relationship to be linear,
so we can write the equations:

+
-
VOC = VTH
RTH +
-
v
i
Fig. 6. Thevenin
equivalent circuit.
ISC RTH
+
-
v
i
Fig. 7. Norton equivalent
circuit.
+
-
+
+
+
-
-
-
VX
VA
VB
VC
RA
RB
RC
Fig. 8. Example of a
voltage divider.
R
V
I
TH
OC
SC
= (5)
V
R
R R R
VB
B
A B C
X=
+ +
(6)
The linear equations help us visualize what might be inside of a real
source:
Note that:
We can generalize this any linear resistive circuit can be⇒
represented as in Figs. 6 and 7.
Voltage Dividers
Example - finding the voltage across RB :
Resistors must be in series, i.e., they must
carry the same current!!!
(Sometimes we cheat a little, and use the divider equation if the
currents through the resistors are almost the same - we’ll note this
in class if that is the case)

RA RB RCIX
IB
Fig. 9. Example of a current divider.
+
-
I
Fig. 10. The total
response current I . . .
IA
Fig. 11. . . . is the sum of
the response IA . . .
+
-
IB
Fig. 12. . . . and the
response IB . . .
I
R
R R R
IB
B
A B C
X=
+ +
1
1 1 1
(7)
10 kΩ 30 kΩ
4 V 12 V
VX
Fig. 13. A quick exercise . . .
Current Dividers
Resistors must be in parallel, i.e.,
have the same voltage!!!
Superposition
Superposition applies to any linear circuit - in fact, this is the
definition of a linear circuit!!!
An example of finding a response using superposition:
A quick exercise:
Use superposition and voltage division to show that VX = 6 V:

What’s missing from this review???
Node voltages / mesh currents . . .
For the kinds of problems you’ll encounter in this course, I think you
should forget about these analysis methods!!!
If there is any other way to solve a circuit problem, do it that other
way . . . you’ll arrive at the answer more efficiently, and with more
insight.
You’ll still need Ohm’s and Kirchoff’s Laws:
KVL: Sum of voltages around a closed loop is zero.
We’ll more often use a different form:
Sum of voltages from point A to point B is the same
regardless of the path taken.
KCL: Sum of currents into a node (or area) is zero.
I won’t insult you by repeating Ohm’s Law here . . .

Introduction to Electronics 6Basic Amplifier Concepts
Signal
Source
Amplifier Loadvi (t) vo (t)
+ +
- -
Ground
Fig. 14. Block diagram of basic amplifier.
vi
t
Fig. 15. Generic input
signal voltage.
vo
t
Fig. 16. Output voltage
of noninverting
amplifier.
vo
t
Fig. 17. Output voltage
of inverting amplifier.
Basic Amplifier Concepts
Signal Source
A signal source is anything that provides the signal, e.g., . . .
. . . the carbon microphone in a telephone handset . . .
. . . the fuel-level sensor in an automobile gas tank . . .
Amplifier
An amplifier is a system that provides gain . . .
. . . sometimes voltage gain (illustrated below), sometimes current
gain, always power gain.

Introduction to Electronics 7Basic Amplifier Concepts
Signal
Source
Amplifier Loadvi (t) vo (t)
+ +
- -
Ground
Fig. 18. Block diagram of basic amplifier (Fig. 14 repeated).
Load
The load is anything we deliver the amplified signal to, e.g., . . .
. . . loudspeaker . . .
. . . the leg of lamb in a microwave oven . . .
Ground Terminal
Usually there is a ground connection . . .
. . . usually common to input and output . . .
. . . maybe connected to a metal chassis . . .
. . . maybe connected to power-line ground . . .
. . . maybe connected to both . . .
. . . maybe connected to neither . . . use caution!!!
To work with (analyze and design) amplifiers
we need to visualize what might be inside all three blocks of Fig. 18,
i.e., we need models!!!

Introduction to Electronics 8Voltage Amplifier Model
+ +
- -
vs vi Avocvi vo
+ +
- -
RS
RLRi
Ro
ii io
Source Amplifier Load
Fig. 19. Modeling the source, amplifier, and load with the emphasis on
voltage.
Voltage Amplifier Model
This is usually the one we have the most intuition about . . .
Signal Source
Our emphasis is voltage . . . source voltage decreases as source
current increases, as with any real source . . .
. . . so we use a Thevenin equivalent.
Amplifier Input
When the source is connected to the amplifier, current flows . . .
. . . the amplifier must have an input resistance, Ri .
Amplifier Output
Output voltage decreases as load current increases . . .
. . . again we use a Thevenin equivalent.
Load
Load current flows . . . the load appears as a resistance, RL .

+ +
- -
vs vi Avocvi vo
+ +
- -
RS
RLRi
Ro
ii io
Fig. 20. Voltage amplifier model (Fig. 19 repeated).
+
-
vi Avocvi vo
+ +
- -
RLRi
Ro
ii io
Amplifier Load
+
-vi
Fig. 21. Av = vo /vi illustrated.
A
v
v
voc
o
i RL
=
= ∞
(8)
A
v
v
v
R
R R
A v A A
R
R R
V
o
i
o
L
o L
voc i v voc
L
o L
= ⇒ =
+
⇒ =
+
(9)
Open-Circuit Voltage Gain
If we remove RL (i.e., with RL = ) the voltage of the Thevenin∞
source in the amplifier output is the open-circuit output voltage of
the amplifier. Thus, Avoc is called the open-circuit voltage gain:
Voltage Gain
With a load in place our concept of voltage gain changes slightly:
We can think of this as the amplifier voltage gain if the source were
ideal:

+ +
- -
vs vi Avocvi vo
+ +
- -
RS
RLRi
Ro
ii io
Fig. 22. Voltage amplifier model (Fig. 19 repeated).
A
v
v
v
R
R R
v A A
R
R R
R
R R
vs
o
s
i
i
S i
s vs voc
i
S i
L
o L
= ⇒ =
+
⇒ =
+ +
(10)
A
i
i
v
R
v
R
v
v
R
R
A
R
R
i
o
i
o
L
i
i
o
i
i
L
v
i
L
= = = = (11)
G
P
P
V I
V I
A A A
R
R
A
R
R
o
i
o o
i i
v i v
i
L
i
L
i
= = = = =
2 2
(12)
With our “real” source model we define another useful voltage gain:
Notice that Av and Avs are both less than Avoc, due to loading effects.
Current Gain
We can also define the amplifier current gain:
Power Gain
Because the amplifier input and load are resistances, we have
Po = Vo Io , and Pi = Vi Ii (rms values). Thus:

Introduction to Electronics 11Power Supplies, Power Conservation, and Efficiency
+ +
- -
vs vi Avocvi vo
+ +
- -
RS
RLRi
Ro
ii io
VAA
-VBB
IA
IB
VAA
VBB
+
+
-
-
Fig. 23. Our voltage amplifier model showing power supply and ground connections.
P V I V IS AA A BB B= + (13)
P P P PS i o D+ = + (14)
Power Supplies, Power Conservation, and Efficiency
The signal power delivered to the load is converted from the dc
power provided by the power supplies.
DC Input Power
This is sometimes noted as PIN. Use care not to confuse this with
the signal input power Pi .
Conservation of Power
Signal power is delivered to the load Po⇒
Power is dissipated within the amplifier as heat PD⇒
The total input power must equal the total output power:
Virtually always Pi << PS and is neglected.

Introduction to Electronics 12Power Supplies, Power Conservation, and Efficiency
+ +
- -
vs vi Avocvi vo
+ +
- -
RS
RLRi
Ro
ii io
VAA
-VBB
IA
IB
VAA
VBB
+
+
-
-
Fig. 24. Our voltage amplifier model showing power supply and ground connections
(Fig. 23 repeated).
η = ×
P
P
o
S
100% (15)
Efficiency
Efficiency is a figure of merit describing amplifier performance:

Introduction to Electronics 13Amplifier Cascades
+
-
vi1
Avoc1vi1
+
-
Ri1
Ro1
ii1
+
-
vo1 = vi2
Avoc2vi2
+
-
Ri2
Ro2ii2 io2
vo2
+
-
Amplifier 1 Amplifier 2
Fig. 25. A two-amplifier cascade.
A
v
v
v
o
i
1
1
1
= (16)
+
-
vi1
Avocvi1
+
-
Ri1
Ro2ii1 io2
vo2
+
-
Fig. 26. Model of cascade.
A
v
v
v
v
v
o
i
o
o
2
2
2
2
1
= = (17)
A
v
v
v
v
A Avoc
o
i
o
o
v v= =1
1
2
1
1 2 (18)
Amplifier Cascades
Amplifier stages may be connected together (cascaded) :
Notice that stage 1 is loaded by the input resistance of stage 2.
Gain of stage 1:
Gain of stage 2:
Gain of cascade:
We can replace the two models by a single model (remember, the
model is just a visualization of what might be inside):

Introduction to Electronics 14Decibel Notation
10 10
10 10 10
20 10 10
2
2
log log
log log log
log log log
G A
R
R
A R R
A R R
v
i
L
v i L
v i L
=
= + −
= + −
(21)
G GdB =10log (19)
G GG G G G Gtotal dB dB dB, , ,log log log= = + = +10 10 101 2 1 2 1 2 (20)
Decibel Notation
Amplifier gains are often not expressed as simple ratios . . . rather
they are mapped into a logarithmic scale.
The fundamental definition begins with a power ratio.
Power Gain
Recall that G = Po /Pi , and define:
GdB is expressed in units of decibels, abbreviated dB.
Cascaded Amplifiers
We know that Gtotal = G1 G2 . Thus:
Thus, the product of gains becomes the sum of gains in decibels.
Voltage Gain
To derive the expression for voltage gain in decibels, we begin by
recalling from eq. (12) that G = Av
2
(Ri /RL ). Thus:

A Av dB v= 20log (22)
A Ai dB i= 20log (23)
316 20
316
1
10. log
.
V =
V
V
dBV= (24)
Even though Ri may not equal RL in most cases, we define:
Only when Ri does equal RL , will the numerical values of GdB and
Av dB be the same. In all other cases they will differ.
From eq. (22) we can see that in an amplifier cascade the product
of voltage gains becomes the sum of voltage gains in decibels.
Current Gain
In a manner similar to the preceding voltage-gain derivation, we can
arrive at a similar definition for current gain:
Using Decibels to Indicate Specific Magnitudes
Decibels are defined in terms of ratios, but are often used to
indicate a specific magnitude of voltage or power.
This is done by defining a reference and referring to it in the units
notation:
Voltage levels:
dBV, decibels with respect to 1 V . . . for example,

5 10
5
699mW =
mW
1 mW
dBmlog .= (25)
5 23 0mW = 10log
5 mW
1 W
dbW= − . (26)
Power levels:
dBm, decibels with respect to 1 mW . . . for example
dBW, decibels with respect to 1 W . . . for example
There is a 30 dB difference between the two previous examples
because 1 mW = - 30 dBW and 1 W = +30 dBm.

Introduction to Electronics 17Other Amplifier Models
+ +
- -
vs vi Avocvi vo
+ +
- -
RS
RLRi
Ro
ii io
voltage (Fig. 19 repeated).
is RS RLRo
ii io
Source Current Amplifier Load
vi
+
-
Ri
vo
+
-Aiscii
current.
A
i
i
isc
o
i RL
=
= 0
(27)
Other Amplifier Models
Recall, our voltage amplifier model arose from our visualization of
what might be inside a real amplifier:
Current Amplifier Model
Suppose we choose to emphasize current. In this case we use
Norton equivalents for the signal source and the amplifier:
The short-circuit current gain is given by:

RLRo
ii io
Source Transconductance Amplifier Load
vi
+
-
Ri
vo
+
-Gmscvi
+
-
vs
RS
Fig. 29. The transconductance amplifier model.
+
-
vi Rmocii vo
+ +
- -
RLRi
Ro
ii io
Source Transresistance Amplifier Load
is RS
Fig. 30. The transresistance amplifier model.
G
i
vmsc
o
i RL
=
= 0
(siemens, S) (28)
R
v
imoc
o
i RL
=
= ∞
(ohms, )Ω (29)
Transconductance Amplifier Model
Or, we could emphasize input voltage and output current:
The short-circuit transconductance gain is given by:
Transresistance Amplifier Model
Our last choice emphasizes input current and output voltage:
The open-circuit transresistance gain is given by:

Any of these four models can be used to represent what might be
inside of a real amplifier.
Any of the four can be used to model the same amplifier!!!
G Models obviously will be different inside the amplifier.
G If the model parameters are chosen properly, they will
behave identically at the amplifier terminals!!!
We can change from any kind of model to any other kind:
G Change Norton equivalent to Thevenin equivalent (if
necessary).
G Change the dependent source’s variable of dependency
with Ohm’s Law vi = ii Ri (if necessary).⇒
Try it!!! Pick some values and practice!!!

Introduction to Electronics 20Amplifier Resistances and Ideal Amplifiers
+ +
- -
vs vi Avocvi vo
+ +
- -
RS
RLRi
Ro
ii io
Source Voltage Amplifier Load
Fig. 31. Voltage amplifier model.
Amplifier Resistances and Ideal Amplifiers
Ideal Voltage Amplifier
Let’s re-visit our voltage amplifier model:
We’re thinking voltage, and we’re thinking amplifier . . . so how can
we maximize the voltage that gets delivered to the load ?
G We can get the most voltage out of the signal source if
Ri >> RS , i.e., if the amplifier can “measure” the signal voltage
with a high input resistance, like a voltmeter does.
In fact, if , we won’t have to worry about the value ofRi ⇒∞
RS at all!!!
G We can get the most voltage out of the amplifier if Ro << RL ,
i.e., if the amplifier can look as much like a voltage source as
possible.
In fact, if , we won’t have to worry about the value of RLRo ⇒0
at all!!!
So, in an ideal world, we could have an ideal amplifier!!!

+
-
Avocvivi
+
-
Fig. 32. Ideal voltage amplifier. Signal
source and load are omitted for clarity.
is RS RLRo
ii io
Source Current Amplifier Load
vi
+
-
Ri
vo
+
-Aiscii
Fig. 33. Current amplifier model (Fig. 28 repeated).
An ideal amplifier is only a concept; we cannot build one.
But an amplifier may approach the ideal, and we may use the
model, if only for its simplicity.
Ideal Current Amplifier
Now let’s revisit our current amplifier model:
How can we maximize the current that gets delivered to the load ?
G We can get the most current out of the signal source if
Ri << RS , i.e., if the amplifier can “measure” the signal current
with a low input resistance, like an ammeter does.
In fact, if , we won’t have to worry about the value of RSRi ⇒0
at all!!!

Aisciiii
Fig. 34. Ideal current amplifier.
Gmscvivi
+
-
Fig. 35. Ideal transconductance amplifier.
G We can get the most current out of the amplifier if Ro >> RL ,
i.e., if the amplifier can look as much like a current source as
possible.
In fact, if , we won’t have to worry about the value ofRo ⇒∞
RL at all!!!
This leads us to our conceptual ideal current amplifier:
Ideal Transconductance Amplifier
With a mixture of the previous concepts we can conceptualize an
ideal transconductance amplifier.
This amplifier ideally measures the input voltage and produces an
output current:

Rmociiii
+
-
Fig. 36. Ideal transresistance amplifier.
Ideal Transresistance Amplifier
Our final ideal amplifier concept measures input current and
produces an output voltage:
Uniqueness of Ideal Amplifiers
Unlike our models of “real” amplifiers, ideal amplifier models cannot
be converted from one type to another (try it . . .).

Introduction to Electronics 24Frequency Response of Amplifiers
A
V
V
V V
V V
A Av
o
i
o o
i i
v v= =
∠
∠
= ∠ (30)
A Av vdB
= 20log (31)
Frequency Response of Amplifiers
Terms and Definitions
In real amplifiers, gain changes with frequency . . .
“Frequency” implies sinusoidal excitation which, in turn, implies
phasors . . . using voltage gain to illustrate the general case:
Both |Av| and Av are functions of frequency and can be plotted.∠
Magnitude Response:
A plot of |Av| vs. f is called the magnitude response of the amplifier.
Phase Response:
A plot of Av vs. f is called the phase response of the amplifier.∠
Frequency Response:
Taken together the two responses are called the frequency
response . . . though often in common usage the term frequency
response is used to mean only the magnitude response.
Amplifier Gain:
The gain of an amplifier usually refers only to the magnitudes:

f (log scale)
|Av|dB
|Av mid|dB
3 dB
fH
Bandwidth, B
midband region
Fig. 37. Magnitude response of a dc-coupled, or direct-coupled amplifier.
f (log scale)
|Av|dB
|Av mid|dB
3 dB
fL fH
Bandwidth, B
midband region
Fig. 38. Magnitude response of an ac-coupled, or RC-coupled amplifier.
The Magnitude Response
Much terminology and measures of amplifier performance are
derived from the magnitude response . . .
|Av mid|dB is called the midband gain . . .
fL and fH are the 3-dB frequencies, the corner frequencies, or the
half-power frequencies (why this last one?) . . .
B is the 3-dB bandwidth, the half-power bandwidth, or simply the
bandwidth (of the midband region) . . .

+
-
+
-
Fig. 39. Two-stage amplifier model including stray
wiring inductance and stray capacitance between
stages. These effects are also found within each
amplifier stage.
+
-
+
-
Fig. 40. Two-stage amplifier model showing
capacitive coupling between stages.
Causes of Reduced Gain at Higher Frequencies
Stray wiring inductances . . .
Stray capacitances . . .
Capacitances in the amplifying devices (not yet included in our
amplifier models) . . .
The figure immediately below provides an example:
Causes of Reduced Gain at Lower Frequencies
This decrease is due to capacitors placed between amplifier stages
(in RC-coupled or capacitively-coupled amplifiers) . . .
This prevents dc voltages in one stage from affecting the next.
Signal source and load are often coupled in this manner also.

Introduction to Electronics 27Differential Amplifiers
+
-
+
-
+
-
+
-
vI1 vI2
vICM
vID /2
vID /2
1
1
2
2
+-
Fig. 41. Representing two sources by their differential and
common-mode components.
v v
v
v v
v
I ICM
ID
I ICM
ID
1 2
2 2
= + = −and (32)
Differential Amplifiers
Many desired signals are weak, differential signals in the presence
of much stronger, common-mode signals.
Example:
Telephone lines, which carry the desired voice signal between the
green and red (called tip and ring) wires.
The lines often run parallel to power lines for miles along highway
right-of-ways . . . resulting in an induced 60 Hz voltage (as much as
30 V or so) from each wire to ground.
We must extract and amplify the voltage difference between the
wires, while ignoring the large voltage common to the wires.
Modeling Differential and Common-Mode Signals
As shown above, any two signals can be modeled by a differential
component, vID , and a common-mode component, vICM , if:

Introduction to Electronics 28Differential Amplifiers
+
-
+
-
vo = Ad vid + Acm vicm
vid /2
vid /2
+-
Amplifier
+
-
vicm
Fig. 42. Amplifier with differential and common-mode input signals.
CMRR
A
A
dB
d
cm
= 20log (34)
v v v v
v v
ID I I ICM
I I
= − =
+
1 2
1 2
2
and (33)
Solving these simultaneous equations for vID and vICM :
Note that the differential voltage vID is the difference between the
signals vI1 and vI2 , while the common-mode voltage vICM is the
average of the two (a measure of how they are similar).
Amplifying Differential and Common-Mode Signals
We can use superposition to describe the performance of an
amplifier with these signals as inputs:
A differential amplifier is designed so that Ad is very large and Acm
is very small, preferably zero.
Differential amplifier circuits are quite clever - they are the basic
building block of all operational amplifiers
Common-Mode Rejection Ratio
A figure of merit for “diff amps,” CMRR is expressed in decibels:

Introduction to Electronics 29Ideal Operational Amplifiers
+
-
v+
v-
vO
vO = A0 (v+ -v- )
Fig. 43. The ideal operational amplifier:
schematic symbol, input and output voltages,
and input-output relationship.
Ideal Operational Amplifiers
The ideal operational amplifier is an
ideal differential amplifier:
A0 = Ad = Acm = 0∞
Ri = Ro = 0∞
B = ∞
The input marked “+” is called the noninverting input . . .
The input marked “-” is called the inverting input . . .
The model, just a voltage-dependent voltage source with the gain
A0 (v+ - v- ), is so simple that you should get used to analyzing
circuits with just the schematic symbol.
Ideal Operational Amplifier Operation
With A0 = , we can conceive of three rules of operation:∞
1. If v+ > v- then vo increases . . .
2. If v+ < v- then vo decreases . . .
3. If v+ = v- then vo does not change . . .
In a real op amp vo cannot exceed the dc power supply voltages,
which are not shown in Fig. 43.
In normal use as an amplifier, an operational amplifier circuit
employs negative feedback - a fraction of the output voltage is
applied to the inverting input.

Introduction to Electronics 30Ideal Operational Amplifiers
Op Amp Operation with Negative Feedback
Consider the effect of negative feedback:
G If v+ > v- then vo increases . . .
Because a fraction of vo is applied to the inverting input,
v- increases . . .
The “gap” between v+ and v- is reduced and will eventually
become zero . . .
Thus, vo takes on the value that causes v+ - v- = 0!!!
G If v+ < v- then vo decreases . . .
Because a fraction of vo is applied to the inverting input,
v- decreases . . .
The “gap” between v+ and v- is reduced and will eventually
become zero . . .
Thus, vo takes on the value that causes v+ - v- = 0!!!
In either case, the output voltage takes on whatever value that
causes v+ - v- = 0!!!
In analyzing circuits, then, we need only determine the value of vo
which will cause v+ - v- = 0.
Slew Rate
So far we have said nothing about the rate at which vo increases or
decreases . . . this is called the slew rate.
In our ideal op amp, we’ll presume the slew rate is as fast as we
need it to be (i.e., infinitely fast).

Introduction to Electronics 31Op Amp Circuits - The Inverting Amplifier
+
-
+
vO
vi
R1 R2
i1 i2
0
Fig. 44. Inverting amplifier circuit.
v
v R v R
R R
i o
− =
+
+
2 1
1 2
(35)
v R v R v
R
R
v A
R
R
i o o i v2 1
2
1
2
1
0+ = ⇒ = − ⇒ = − (36)
Op Amp Circuits - The Inverting Amplifier
Let’s put our ideal op amp concepts to work in this basic circuit:
Voltage Gain
Because the ideal op amp has Ri = , the current into the inputs∞
will be zero.
This means i1 = i2 , i.e., resistors R1 and R2 form a voltage dividerIII
Therefore, we can use superposition to find the voltage v- .
(Remember the quick exercise on p. 4 ??? This is the identical
problem!!!):
Now, because there is negative feedback, vo takes on whatever
value that causes v+ - v- = 0 , and v+ = 0 !!!
Thus, setting eq. (35) to zero, we can solve for vo :

Introduction to Electronics 32Op Amp Circuits - The Inverting Amplifier
+
-
+
vO
vi
R1 R2
i1 i2
0
Fig. 45. Inverting amplifier circuit
(Fig. 44 repeated).
i
v
R
R
v
i
v
Ri
in
i i
v
R
i
1
1 1
1
1
= ⇒ = = = (37)
RO = 0 (38)
Input Resistance
This means resistance “seen” by the signal source vi , not the input
resistance of the op amp, which is infinite.
Because v- = 0, the voltage across R1 is vi . Thus:
Output Resistance
This is the Thevenin resistance which would be “seen” by a load
looking back into the circuit (Fig. 45 does not show a load attached).
Our op amp is ideal; its Thevenin output resistance is zero:

Introduction to Electronics 33Op Amp Circuits - The Noninverting Amplifier
+
-
+
vOvi
R1 R2
i1 i2
0
Fig. 46. Noninverting amplifier circuit.
v v v
R
R R
vi o= = =
+
+ −
1
1 2
(39)
v
R R
R
v
R
R
v A
R
R
o i i v=
+
= +





 ⇒ = +1 2
1
2
1
2
1
1 1 (40)
R Rin i= = ∞ (41)
RO = 0 (42)
Op Amp Circuits - The Noninverting Amplifier
If we switch the vi and ground connections on the inverting
amplifier, we obtain the noninverting amplifier:
Voltage Gain
This time our rules of operation and a voltage divider equation lead
to:
from which:
Input and Output Resistance
The source is connected directly to the ideal op amp, so:
A load “sees” the same ideal Thevenin resistance as in the inverting
case:

Introduction to Electronics 34Op Amp Circuits - The Voltage Follower
+
-
+
vovi
Fig. 47. The voltage follower.
v v v v Ai o v= = = ⇒ =+ − 1 (43)
R Rin O= ∞ =and 0 (44)
Op Amp Circuits - The Voltage Follower
Voltage Gain
This one is easy:
i.e., the output voltage follows the input voltage.
Input and Output Resistance
By inspection, we should see that these values are the same as for
the noninverting amplifier . . .
In fact, the follower is just a special case of the noninverting
amplifier, with R1 = and R2 = 0!!!∞

Introduction to Electronics 35Op Amp Circuits - The Inverting Summer
+
-
+
vO
vB
RB RF
iA
iF
+
vA
RA iB
+ -
Fig. 48. The inverting summer.
i
v
R
i
v
R
A
A
A
B
B
B
= =and (45)
( )i i i v R i i R
v
R
v
RF A B R F A B F
A
A
B
B
F
= + = + = +





and (46)
v
R
R
v
R
R
vO
F
A
A
F
B
B= − +





 (47)
Op Amp Circuits - The Inverting Summer
This is a variation of the inverting amplifier:
Voltage Gain
We could use the superposition approach as we did for the
standard inverter, but with three sources the equations become
unnecessarily complicated . . . so let’s try this instead . . .
Recall . . . vO takes on the value that causes v- = v+ = 0 . . .
So the voltage across RA is vA and the voltage across RB is vB :
Because the current into the op amp is zero:
Finally, the voltage rise to vO equals the drop across RF :

Introduction to Electronics 36Op Amp Circuits - Another Inverting Amplifier
+
-
+
vO
vi
R1
R2
i1 R4
R3
i2
Fig. 49. An inverting amplifier with a resistive T-network
for the feedback element.
vO
R4
R3 vTH
RTH
+ +
Fig. 50. Replacing part of the original circuit with a
Thevenin equivalent
Op Amp Circuits - Another Inverting Amplifier
If we want very large gains with the standard inverting amplifier of
Fig. 44, one of the resistors will be unacceptably large or
unacceptably small . . .
We solve this problem with the following circuit:
Voltage Gain
One common approach to a solution begins with a KCL equation at
the R2 - R3 - R4 junction . . .
. . . we’ll use the superposition & voltage divider approach, after we
apply some network reduction techniques.
Notice that R3 , R4 and the op amp output voltage source can be
replaced with a Thevenin equivalent:

Introduction to Electronics 37Op Amp Circuits - Another Inverting Amplifier
v- = 0
vTH
REQ = R2 + RTHR1
vi
Fig. 51. Equivalent circuit to original amplifier.
v
R
R R
v R R RTH O TH=
+
=3
3 4
3 4and || (48)
v
R
R
vTH
EQ
i= −
1
(49)
( )R
R R
v
R R R
R
v
R
R
R R
R
vO i i
3
3 4
2 3 4
1
2
1
3 4
1+
= −
+
= − +






|| ||
(50)
A
v
v
R
R
R
R
R R
R
v
O
i
= = − +





 +





1 4
3
2
1
3 4
1
||
(51)
The values of the Thevenin elements in Fig. 50 are:
With the substitution of Fig. 50 we can simplify the original circuit:
Again, vO , and therefore vTH, takes on the value necessary to make
v+ - v- = 0 . . .
We’ve now solved this problem twice before (the “quick exercise” on
p. 4, and the standard inverting amplifier analysis of p. 31):
Substituting for vTH and REQ , and solving for vO and Av :

Introduction to Electronics 38Op Amp Circuits - The Differential Amplifier
+
-
+
vO
v1
R1 R2
i1 i2
+
R1
R2v2
+ -
Fig. 52. The differential amplifier.
v
R
R R
v v+ −=
+
=2
1 2
2 (52)
( )
i
v v
R
v
R
R
R R R
v i1
1
1
1
1
2
1 1 2
2 2=
−
= −
+
=−
(53)
( )
v i R
R
R
v
R R
R R R
vR2 2 2
2
1
1
2 2
1 1 2
2= = −
+
(54)
( )
v v v
R
R R
v
R
R
v
R R
R R R
vO R= − =
+
− +
++ 2
2
1 2
2
2
1
1
2 2
1 1 2
2 (55)
Op Amp Circuits - Differential Amplifier
The op amp is a differential amplifier to begin with, so of course we
can build one of these!!!
Voltage Gain
Again, vO takes on the value
required to make v+ = v- .
Thus:
We can now find the current
i1 , which must equal the
current i2 :
Knowing i2 , we can calculate the voltage across R2 . . .
Then we sum voltage rises to the output terminal:

Introduction to Electronics 39Op Amp Circuits - The Differential Amplifier
( ) ( ) ( )
R
R R
v
R R
R R R
v
R R
R R R
v
R R
R R R
v2
1 2
2
2 2
1 1 2
2
1 2
1 1 2
2
2 2
1 1 2
2
+
+
+
=
+
+
+
(56)
( )
( )
( )
=
+
+
=
+
+
=
R R R R
R R R
v
R R R
R R R
v
R
R
v1 2 2 2
1 1 2
2
2 1 2
1 1 2
2
2
1
2 (57)
( )v
R
R
v
R
R
v
R
R
v vO = − + = −2
1
1
2
1
2
2
1
2 1 (58)
Working with just the v2 terms from eq. (55) . . .
And, finally, returning the resulting term to eq. (55):
So, under the conditions that we can have identical resistors (and
an ideal op amp) we truly have a differential amplifier!!!

Introduction to Electronics 40Op Amp Circuits - Integrators and Differentiators
+
-
vO
vi
R C
iR iC
+
+ -
Fig. 53. Op amp integrator.
i
v
R
iR
i
C= = (59)
( )v
C
i dt
C
i dt vC C
t
C C
t
= = +
−∞
∫ ∫
1 1
0
0
(60)
( ) ( )v
C
v
R
dt v
RC
v dt vO
i
t
C i C
t
= − + = − +∫ ∫
1
0
1
0
0 0
(61)
Op Amp Circuits - Integrators and Differentiators
Op amp circuits are not limited to resistive elements!!!
The Integrator
From our rules and previous
experience we know that v- = 0
and iR = iC , so . . .
From the i-v relationship of a
capacitor:
Combining the two previous equations, and recognizing that
vO = - vC :
Normally vC (0) = 0 (but not always). Thus the output is the integral
of vi , inverted, and scaled by 1/RC.

Introduction to Electronics 41Op Amp Circuits - Integrators and Differentiators
+
-
vO
vi
RC
iRiC
+
+ -
Fig. 54. The op amp differentiator.
i C
dv
dt
C
dv
dt
iC
C i
R= = = (62)
v v i R RC
dv
dt
O R R
i
= − = − = − (63)
The Differentiator
This analysis proceeds in the
same fashion as the previous
analysis.
From our rules and previous
experience we know that v- = 0
and iC = iR . . .
From the i-v relationship of a capacitor:
Recognizing that vO = -vR :

Introduction to Electronics 42Op Amp Circuits - Designing with Real Op Amps
+
-
+
vO
vi
R1
RL
iLiF
+
-
R2
Fig. 55. Noninverting amplifier with load.
+
-
+
vO
vi
R1 R2
i1
i2
RS
Fig. 56. Inverting amplifier including source resistance.
Op Amp Circuits - Designing with Real Op Amps
Resistor Values
Our ideal op amp can supply unlimited current; real ones can’t . . .
To limit iF + iL to a reasonable
value, we adopt the “rule of
thumb” that resistances should
be greater than approx. 100 Ω.
Of course this is highly
dependent of the type of op amp
to be used in a design.
Larger resistances render circuits more susceptible to noise and
more susceptible to environmental factors.
To limit these problems we adopt the “rule of thumb” that
resistances should be less than approximately 1 MΩ.
Source Resistance and Resistor Tolerances
In some designs RS will
affect desired gain.
Resistor tolerances will
also affect gain.
If we wish to ignore source resistance effects, resistances must be
much larger than RS (if possible).
Resistor tolerances must also be selected carefully.

Introduction to Electronics 43Graphical Solution of Simultaneous Equations
y x y= =and 4 (64)
Fig. 57. Simple example of obtaining the solution to simultaneous
equations using a graphical method.
Graphical Solution of Simultaneous Equations
Let’s re-visit some 7th
-grade algebra . . .we can find the solution of
two simultaneous equations by plotting them on the same set of
axes.
Here’s a trivial example:
We plot both equations:
Obviously, the solution is where the two plots intersect, at x = 4,
y = 4 . . .

y
x
x
=
<
≥



0 0
0
, for
0.4x , for2
(65)
Fig. 58. Another example of graphically finding the solution to
simultaneous equations.
y
x
= −8
4
5
(66)
Let’s try another one:
and
Here we see that the solution is approximately at x = 3.6, y = 5.2.
Note that we lose some accuracy with a graphical method, but, we
gain the insight that comes with the “picture.”

Fig. 59. Graphically finding multiple solutions.
y x x= 0 4 2
. , for all (67)
y
x
= −8
4
5
(68)
If we change the previous example slightly, we’ll see that we can’t
arbitrarily neglect the other quadrants:
and
Now we have two solutions - the first one we found before, at
x = 3.6, y = 5.2 . . . the second solution is at x = -5.5, y = 12.5.
In the pages and weeks to come, we will often use a graphical
method to find current and voltage in a circuit.
This technique is especially well-suited to circuits with nonlinear
elements.

Introduction to Electronics 46Diodes
Anode Cathode
p-type n-type
+ -
iD
vD
+ +
+ ++
+ + - - -
- -
- -
free
electrons
free
”holes”
Fig. 60. Simplified physical construction and schematic symbol of
a diode.
Diodes
When we “place” p-type semiconductor adjacent to n-type
semiconductor, the result is an element that easily allows current to
flow in one direction, but restricts current flow in the opposite
direction . . . this is our first nonlinear element:
The free holes “wish” to combine with the free electrons . . .
When we apply an external voltage that facilitates this combination
(a forward voltage, vD > 0), current flows easily.
When we apply an external voltage that opposes this combination,
(a reverse voltage, vD < 0), current flow is essentially zero.
Of course, we can apply a large enough reverse voltage to force
current to flow . . .this is not necessarily destructive.

Introduction to Electronics 47Diodes
Fig. 61. PSpice-generated i-v characteristic for a 1N750 diode showing the various regions of
operation.
Thus, the typical diode i-v characteristic:
VF is called the forward knee voltage, or simply, the forward voltage.
G It is typically approximately 0.7 V, and has a temperature
coefficient of approximately -2 mV/K
VB is called the breakdown voltage.
G It ranges from 3.3 V to kV, and is usually given as a positive
value.
Diodes intended for use in the breakdown region are called zener
diodes (or, less often, avalanche diodes).
In the reverse bias region, |iD| 1 nA for low-power (“signal”)≈
diodes.

Introduction to Electronics 48Graphical Analysis of Diode Circuits
iD
+
-
vD
+
-
R
VS
Fig. 62. Example circuit to illustrate
graphical diode circuit analysis.
v
+
-
(=R)
VOC
i
+
-
(=VS)
RTH
Fig. 63. Thevenin eq. of
Fig. 62 identified.
VOC
ISC
1/RTH
v=vD
i=iD
Fig. 64. Graphical solution.
v V iR i I
v
R
OC TH SC
TH
= − = −or (69)
Graphical Analysis of Diode Circuits
We can analyze simple diode circuits using the graphical method
described previously:
We need two equations to find the
two unknowns iD and vD .
The first equation is “provided” by
the diode i-v characteristic.
The second equation comes from
the circuit to which the diode is
connected.
This is just a standard Thevenin
equivalent circuit . . .
. . . and we already know its i-v
characteristic . . . from Fig. 5 and eq.
(4) on p. 2:
. . . where VOC and ISC are the open-
circuit voltage and the short-circuit
current, respectively.
A plot of this line is called the load
line, and the graphical procedure is
called load-line analysis.

Introduction to Electronics 49Graphical Analysis of Diode Circuits
iD
+
-
vD
+
-
R
VS
Fig. 65. Example circuit
(Fig. 62 repeated).
Case 3: VOC = VS = 10 V
ISC = 10 V / 1 kΩ = 10 mA
VOC not on scale, use slope:
1
1
1 2 5
2 5k
mA
V
mA
VΩ = = .
.
The solution is at:
vD 0.68 V, iD 9.3 mA≈ ≈
Fig. 66. Example solutions.
Examples of Load-Line Analysis
Case 1: VS = 2.5 V and R = 125 Ω
Case 2: VS = 1 V and R = 25 Ω
Case 3: VS = 10 V and R = 1 kΩ
Case 1: VOC = VS = 2.5 V and ISC = 2.5 V / 125 Ω = 20 mA.
We locate the intercepts, and draw the line.
The solution is at vD 0.71 V, iD 14.3 mA≈ ≈
Case 2: VOC = VS = 1 V and ISC = 1 V / 25 Ω = 40 mA
ISC is not on scale, so we use the slope: 1
25
40 20
0 5Ω = =mA
V
mA
V.
The solution is at vD 0.70 V, iD 12.0 mA≈ ≈

Introduction to Electronics 50Diode Models
i I
v
nV
D S
D
T
=





 −





exp 1 (70)
v nV
i
I
D T
D
S
= +





ln 1 (71)
V
kT
q
T = (72)
Diode Models
Graphical solutions provide insight, but neither convenience nor
accuracy . . . for accuracy, we need an equation.
The Shockley Equation
or conversely
where,
IS is the saturation current, 10 fA for signal diodes≈
IS approx. doubles for every 5 K increase in temp.
n is the emission coefficient, 1 n 2≤ ≤
n = 1 is usually accurate for signal diodes (iD < 10 mA)
VT is the thermal voltage,
k, Boltzmann’s constant, k = 1.38 (10-23
) J/K
T. temperature in kelvins
q, charge of an electron, q = 1.6 (10-19
) C
Note: at T = 300 K, VT = 25.9 mV
we’ll use VT = 25 mV as a matter of convenience.

i I
v
nV
D S
D
T
≈





exp (75)
i ID S≈ − (76)
v nV
i
I
i RD T
D
S
D S= +





 +ln 1 (77)
i I
v
nV
D S
D
T
=





 −





exp 1 (73)
v nV
i
I
D T
D
S
= +





ln 1 (74)
Repeating the two forms of the Shockley equation:
Forward Bias Approximation:
For vD greater than a few tenths of a volt, exp(vD /nVT ) >> 1, and:
Reverse Bias Approximation:
For vD less than a few tenths (negative), exp(vD /nVT ) << 1, and:
At High Currents:
where RS is the resistance of the bulk semiconductor material,
usually between 10 Ω and 100 Ω.

+ -
iD
vD
fwd bias (ON)
rev bias (OFF)
Fig. 67. Ideal diode i-v characteristic.
Let’s stop and review . . .
G Graphical solutions provide insight, not accuracy.
G The Shockley equation provides accuracy, not convenience.
But we can approximate the diode i-v characteristic to provide
convenience, and reasonable accuracy in many cases . . .
The Ideal Diode
This is the diode we’d like to have.
We normally ignore the breakdown
region (although we could model this,
too).
Both segments are linear . . . if we
knew the correct segment we could
use linear analysis!!!
In general we don’t know which line segment is correct . . .so we
must guess , and then determine if our guess is correct.
If we guess “ON,” we know that vD = 0, and that iD must turn out to
be positive if our guess is correct.
If we guess “OFF,” we know that iD = 0, and that vD must turn out to
be negative if our guess is correct.

10 V 10 V
+
+ +
-
- -
4 kΩ
6 kΩ 3 kΩ
7 kΩvDiD
Fig. 68.Circuit for an ideal diode example.
10 V 10 V
+
+ +
- -
4 kΩ
6 kΩ 3 kΩ
7 kΩ
vD -
Fig. 69.Equivalent circuit if the diode is OFF.
10 V 10 V
+
+ +
- -
4 kΩ
6 kΩ 3 kΩ
7 kΩ
vD -
6 V 3 V
+ +
- -
Fig. 70.Calculating vD for the OFF diode.
10 V 10 V
+ +
- -
4 kΩ
6 kΩ 3 kΩ
7 kΩiD
Fig. 71.Equivalent circuit if the diode is ON.
6 V 3 V
+ +
- -
2.4 kΩ 2.1 kΩiD
667 µA
Fig. 72.Calculating iD for the ON diode.
An Ideal Diode Example:
We need first to
assume a diode state,
i.e., ON or OFF.
We’ll arbitrarily choose
OFF.
If OFF, iD = 0, i.e., the
diode is an open circuit.
We can easily find vD
using voltage division
and KVL vD = 3 V.⇒
vD is not negative, so
diode must be ON.
If ON, vD = 0, i.e., the
diode is a short circuit.
We can easily find iD
using Thevenin eqs.
iD = 667 µA.⇒
No contradictions !!!

+ -
iD
vD
fwd bias (ON)
rev bias (OFF)
(Fig. 67 repeated)
Let’s review the techniques, or rules, used in analyzing ideal diode
circuits. These rules apply even to circuits with multiple diodes:
1. Make assumptions about diode states.
2. Calculate vD for all OFF diodes, and iD for all ON diodes.
3. If all OFF diodes have vD < 0, and all ON diodes have iD > 0,
the initial assumption was correct. If not make new
assumption and repeat.

VX
-VX /RX
1/RX
i
v
Fig. 74. A piecewise-linear segment.
+
+-
-
VX RX
v
i
Fig. 75. Circuit producing eq. (?).
v V iRX X= + (78)
Piecewise-Linear Diode Models
This is a generalization of the ideal diode concept.
Piecewise-linear modeling uses straight line segments to
approximate various parts of a nonlinear i-v characteristic.
The line segment at left has the
equation:
The same equation is provided
by the following circuit:
Thus, we can use the line segments of Fig. 74 to approximate
portions of an element’s nonlinear i-v characteristic . . .
. . . and use the equivalent circuits of Fig. 75 to represent the
element with the approximated characteristic!!!

iD
vD
VF
1/RF
VZ
1/RZ
Fig. 76. A diode i-v characteristic (red) and
its piecewise-linear equivalent (blue).
A “complete” piecewise-linear diode model looks like this:
G In the forward bias region . . .
. . . the approximating segment is characterized by the forward
voltage, VF , and the forward resistance, RF .
G In the reverse bias region . . .
. . . the approximating segment is characterized by iD = 0, i.e.,
an open circuit.
G In the breakdown region . . .
. . . the approximating segment is characterized by the zener
voltage, VZ , (or breakdown voltage, VB ) and the zener
resistance, RZ .

5 V
500 Ω
+ +
- -
vD
iD
Fig. 77. Circuit for piecewise-
linear example.
5 V
500 Ω
+
+
-
-
vD
+
-
0.5 V
10 Ω
Fig. 78. Equivalent circuit in forward
bias region.
iD =
−
+
=
5 05
500 10
882
V V
mA
.
.
Ω Ω
(79)
( )( )vD = +
=
05 882 10
0588
. .
.
V mA
V
Ω
(80)
A Piecewise-Linear Diode Example:
We have modeled a diode using piecewise-linear segments with:
VF = 0.5 V, RF = 10 , and VZ = 7.5 V, RZ = 2.5Ω Ω
Let us find iD and vD in the following circuit:
We need to “guess” a line segment.
Because the 5 V source would tend to
force current to flow in a clockwise
direction, and that is the direction of
forward diode current, let us choose the
forward bias region first.
Our equivalent circuit for the forward bias
region is shown at left. We have
and
This solution does not contradict our forward bias assumption, so
it must be the correct one for our model.

+ -
iD
vD
fwd bias (ON)
rev bias (OFF)
(Fig. 67 repeated)
+ -
iD
vD
VF
fwd bias (ON)
rev bias (OFF)
Fig. 80. I-v characteristic of constant voltage
drop diode model.
Other Piecewise-Linear Models
Our ideal diode model is a
special case . . .
. . . it has VF = 0, RF = 0 in the
forward bias region . . .
. . . it doesn’t have a
breakdown region.
The constant voltage drop
diode model is also a special
case . . .
. . . it has RF = 0 in the forward
bias region . . .
. . . VF usually 0.6 to 0.7 V . . .
. . . it doesn’t have a
breakdown region

Introduction to Electronics 59The Zener Diode Voltage Regulator
+
+
+
-
-
-
VTH
RTH = 500 Ω
vD vOUT
iD
7.5 V to 10 V
Fig. 81. Thevenin equivalent source with
unpredictable voltage and zener diode.
Diode Applications - The Zener Diode Voltage Regulator
Introduction
This application uses diodes in the breakdown region . . .
For VZ < 6 V the physical breakdown phenomenon is called zener
breakdown (high electric field). It has a negative temperature
coefficient.
For VZ > 6 V the mechanism is called avalanche breakdown (high
kinetic energy). It has a positive temperature coefficient.
For VZ 6 V the breakdown voltage has nearly zero temperature≈
coefficient, and a nearly vertical i-v char. in breakdown region, i.e.,
a very small RZ .
These circuits can produce nearly constant voltages when used
with voltage supplies that have variable or unpredictable output
voltages. Hence, they are called voltage regulators.
Load-Line Analysis of Zener Regulators
Note: when intended for use
as a zener diode, the
schematic symbol changes
slightly . . .
With VTH positive, zener
current can flow only if the
zener is in the breakdown
region . . .
We can use load line analysis with the zener diode i-v characteristic
to examine the behavior of this circuit.

+
+
+
-
-
-
VTH
RTH = 500 Ω
vD vOUT
iD
7.5 V to 10 V
Fig. 82. Thevenin equivalent source with
unpredictable voltage and zener diode.
(Fig. 81 repeated)
Fig. 83. 1N750 zener (VZ = 4.7 V) i-v
characteristic in breakdown region, with load
lines from source voltage extremes.
Note that vOUT = -vD . Fig. 83
below shows the graphical
construction.
Because the zener is upside-down
the Thevenin equivalent load line
is in the 3rd
quadrant of the diode
characteristic.
As VTH varies from 7.5 V to 10 V, the load line moves from its blue
position, to its green position.
As long as the zener remains in breakdown, vOUT remains nearly
constant, at 4.7 V.≈
As long as the minimum VTH is somewhat greater than VZ (in this
case VZ = 4.7 V) the zener remains in the breakdown region.
If we’re willing to give up some output voltage magnitude, in return
we get a very constant output voltage.
This is an example of a zener diode voltage regulator providing line
voltage regulation . . . VTH is called the line voltage.

Fig. 84. Zener i-v characteristic of Fig. 83 with
piecewise-linear segment.
+
-
VTH
RTH = 500 Ω
vOUT
7.5 V to 10 V
8 Ω
4.6 V
+
-
+
-
Fig. 85. Regulator circuit of Fig. 81 with piecewise-
linear model replacing the diode.
Numerical Analysis of Zener Regulators
To describe line voltage regulation numerically we use linear circuit
analysis with a piecewise-linear model for the diode.
To obtain the model we draw a tangent to the curve in the vicinity
of the operating point:
From the intercept and slope of the piecewise-linear segment we
obtain VZ = 4.6 V and RZ = 8 Ω. Our circuit model then becomes:

+
-
VTH
RTH = 500 Ω
vOUT
7.5 V to 10 V
8 Ω
4.6 V
+
-
+
-
Fig. 86. Regulator with diode model
(Fig. 85 repeated).
( )V8
8
500 8
75 46 4567Ω
Ω
Ω Ω
=
+
− =. . .V V mV (81)
VO = + =46 45 67 464567. . .V mV V (82)
( )V8
8
500 8
10 46 8504Ω
Ω
Ω Ω
=
+
− =V V V. . (83)
VO = + =46 85 04 4 68504. . .V mV V (84)
Important: The model above is valid only if zener is in
breakdown region !!!
Circuit Analysis:
The 500 Ω and 8 Ω resistors are in series, forming a voltage divider.
For VTH = 7.5 V:
For VTH = 10 V:
Thus, for a 2.5 V change in the line voltage, the output voltage
change is only 39.4 mV !!!

+
+-
-
vD vOUT
iD
+
-
VSS
RS
RL
Fig. 87. Zener regulator with load.
+
+ -
-
vDvOUT
iD
+
-
VSS
RS
RL
Fig. 88. Regulator drawn with zener and
load in reversed positions.
+
+ -
-
vDvOUT
iD
+
-
VTH
RTH
Fig. 89. Regulator of Fig. 87 with VSS , RS ,
and RL replaced by Thevenin eq.
Zener Regulators with Attached Load
Now let’s add a load to our regulator circuit . . .
Only the zener is nonlinear, so we approach this problem by finding
the Thevenin equivalent seen by the diode:
The resulting circuit is topologically identical to the circuit we just
analyzed!!!
Different loads will result in different values for VTH and RTH , but the
analysis procedure remains the same!!!

+
+-
-
vD vOUT
iD
+
-
RS = 500 Ω
RL10 VVSS
Fig. 90. Example of loaded zener regulator for
graphical analysis.
V VOC TH= =
+
=
10
500
10 9 52
k
10 k
V V
Ω
Ω Ω
. (85)
I
V
R
SC
SS
S
= = =
10
20
V
500
mA
Ω
(86)
V VOC TH= =
1
10
k
1k + 500
V = 6.67 V
Ω
Ω Ω
(87)
I
V
R
SC
SS
S
= = =
10
20
V
500
mA
Ω
(88)
Example - Graphical Analysis of Loaded Regulator
Let’s examine graphically the behavior of a loaded zener regulator.
Let VSS = 10 V, RS = 500 Ω and,
(a) RL = 10 kΩ (b) RL = 1 kΩ (c) RL = 100 Ω
We find the load lines in each case by calculating the open-circuit
(Thevenin) voltage and the short-circuit current:
(a)
(b)

V VOC TH= =
+
=
100
100 500
10 167
Ω
Ω Ω
V V. (89)
Fig. 91. Load line analysis for the loaded zener regulator.
I
V
R
SC
SS
S
= = =
10
20
V
500
mA
Ω
(90)
(c)
The three load lines are plotted on the zener characteristic below:
As long as RL (and therefore VTH ) is large enough so that the zener
remains in breakdown, the output voltage is nearly constant !!!
This is an example of a zener diode voltage regulator providing load
voltage regulation (or simply, load regulation).

Introduction to Electronics 66The Half-Wave Rectifier
vO
vD
Vm sin ωtvS
++
+
--
-
RL
Fig. 92. The half-wave rectifier circuit.
t
vS
T
Vm
-Vm
Fig. 93. Waveform of voltage source.
t
vO
T
Vm
Fig. 94. Output voltage waveform.
t
vD
T
-Vm
Fig. 95. Diode voltage waveform.
Diode Applications - The Half-Wave Rectifier
Introduction
This diode application changes
ac into dc. The voltage source is
most often a sinusoid (but can be
anything).
We’ll assume the diode is ideal
for our analysis.
During positive half-cycle . . .
. . . diode conducts (“ON”)
. . . vD = 0
. . . vO = vS
During negative half-cycle . . .
. . . diode “OFF”
. . . iD = 0, vO = 0
. . . vD = vS
Peak Inverse Voltage, PIV:
Another term for breakdown
voltage rating . . .
. . . in this circuit, the diode
PIV rating must be > Vm .

Rtotal D
VBATTERY
+
-
A
110 Vrms Vm sin ωt
+
-
Fig. 96. A circuit typical of most battery chargers.
t
Vm
-Vm
T
VBATT
Charging
current
vS
Fig. 97. Battery charger waveforms.
Here vS represents the transformer secondary voltage, and VBATT
represents the battery voltage.
A Typical Battery Charging Circuit
In the figure above . . .
. . . VBATTERY represents the battery to be charged . . .
. . . Rtotal includes all resistance (wiring, diode, battery, etc.) reflected
to the transformer secondary winding.
Charging current flows only when Vm sin ωt > VBATTERY . . .
. . . inertia of meter movement allows indication of average current.

vS (t) C RL vL (t)
iD (t) iL (t)
++
--
Fig. 98. Filtered half-wave rectifier.
t
vL(t)
Vm
Ripple voltage, Vr
ondiode off
T T
onon diode off
Fig. 99. Load voltage waveform in the filtered half-wave rectifier.
The Filtered Half-Wave Rectifier
Also called a peak rectifier, a half-wave rectifier with a smoothing
capacitor, or a half-wave rectifier with a capacitor-input filter.
We create it by placing a capacitor in parallel with the rectifier load
(creating a low-pass filter):
Analysis of this circuit
with a nonlinear element
is very difficult . . .
. . . so we will use the
ideal diode model.
A lot happens in this circuit!!! Let’s look at the load voltage:

t
vL(t)
Vm
Ripple voltage, Vr
ondiode off
T T
onon diode off
Fig. 100. Load voltage waveform (Fig. 99 repeated).
We let vS (t) = Vm sin ωt . . . and assume steady-state . . .
1. When vS > vL (shown in blue), the diode is on, and the voltage
source charges the capacitor.
(Because the diode and source are ideal, vS can only be
infinitesimally greater than vL )
2. When vS < vL (shown in red), the diode is off, and C discharges
exponentially through RL .
3. We define peak-to-peak ripple voltage, Vr , as the total change
in vL over one cycle.
4. In practice, Vr is much smaller than shown here, typically being
1% to 0.01% of Vm (e.g., a few mV). This means that:
(a) the load voltage is essentially “pure” dc
(b) the diode is off for almost the entire period, T !!!

t
vL(t)
Vm
Ripple voltage, Vr
ondiode off
T T
onon diode off
Q I T
V
R
T
V
fR
L
m
L
m
L
≈ ≈ = (91)
Q V Cr= (92)
V C
V
fR
C
V
V fR
r
m
L
m
r L
= ⇒ = (93)
Relating Capacitance to Ripple Voltage
Because the diode is off for nearly the entire period, T, the capacitor
must supply the “dc” load current during this interval.
The charge taken from the capacitor in this interval is:
The capacitor voltage decreases by Vr in this interval, which
requires a decrease in the charge stored in the capacitor:
Equating these equations and solving for C gives us a design
equation that is valid only for small Vr :

t
vL(t)
Vm
Ripple voltage, Vr
ondiode off
T T
onon diode off
t
i(t)
T T
iD(t)
iL(t)
iD PEAK
on on ondiode off diode off
Fig. 103. Current waveforms in filtered half-wave rectifier.
Because all of the charge supplied to the load must come from the
source only when the diode is ON, iD PEAK can be very large, as
illustrated below..

Introduction to Electronics 72The Full-Wave Rectifier
vS (t)
vL (t)
iL (t)
+
-
vS (t)
vin (t)
+
+
-
-
vA (t)
vB (t)
DA
DB
RL
Fig. 104. The full-wave rectifier.
t
vS
Vm
-Vm
Fig. 105. Voltage across each half of the
transformer secondary.
t
vL
Vm
Fig. 106. Full-wave load voltage.
Diode Applications - The Full-Wave Rectifier
The full-wave rectifier makes use of a center-tapped transformer to
effectively create two equal input sources:
Operation
Note that the upper half of the transformer secondary voltage has
its negative reference at ground, while the lower half of the
secondary voltage has its positive reference at ground.
1st
(Positive) Half-Cycle:
Current flows from upper source, through DA and RL, returning to
upper source via ground. Any current through DB would be in
reverse direction, thus DB is off.
2nd
(Negative) Half-Cycle:
Current flows from lower source, through DB and RL, returning to
lower source via ground. Any current through DA would be in
reverse direction, thus DA is off.

Introduction to Electronics 73The Full-Wave Rectifier
vS (t)
vL (t)
iL (t)
+
-
vS (t)
vin (t)
+
+
-
-
vA (t)
vB (t)
DA
DB
RL
Fig. 107. The full-wave rectifier (Fig. 104 repeated).
t
vA
-2Vm
Fig. 108. Voltage across diode DA .
t
vB
-2Vm
Fig. 109. Voltage across diode DB .
Diode Peak Inverse Voltage
When DA is on, DB is off . . . a KVL path around the “outside” loop of
the transformer secondary shows that DB must withstand a voltage
of 2vS .
When DB is on, DA is off . . . now a KVL path shows that DB must
withstand 2vS .
Thus the diode PIV rating must be 2Vm . Diode voltage waveforms
are shown below . . .

Introduction to Electronics 74The Bridge Rectifier
vL (t)
iL (t)
+
-
vin (t) vS (t)
D1
+
-
D2D3
D4
Fig. 110. The bridge rectifier.
t
vS
Vm
-Vm
Fig. 111. Input voltage to diode bridge.
t
vL
Vm
Fig. 112. Full-wave load voltage.
t
v1, v3
-Vm
Fig. 113. Diode voltage for D1 and D3 .
t
v2, v4
-Vm
Fig. 114. Diode voltage for D2 and D4 .
Diode Applications - The Bridge Rectifier
The bridge rectifier is also a full-wave rectifier, but uses a diode
bridge rather than a center-tapped transformer:
Operation
1st
(Positive) Half-Cycle:
Current flows from top end of vS ,
through D1 and RL , then via
ground through D3 , and back to
vS .
2nd
(Negative) Half-Cycle:
Current flows from bottom end
of vS , through D2 and RL , then
via ground through D4, and back
to vS .
Peak Inverse Voltage:
In each half-cycle the OFF
diodes are directly across vS ,
thus the diode PIV is Vm .

Introduction to Electronics 75Full-Wave/Bridge Rectifier Features
V C
V
fR
C
V
V fR
r
m
L
m
r L
= ⇒ =
2 2
(94)
Diode Applications - Full-Wave/Bridge Rectifier Features
Bridge Rectifier
Much cheaper transformer more than offsets the negligible cost of
two more diodes.
Full-Wave Rectifier
Archaic since vacuum tube rectifiers have largely been replaced by
semiconductor rectifiers.
Preferable only at low voltages (one less diode forward-voltage
drop), if at all.
Filtered Full-Wave and Bridge Rectifiers
Because the rectifier output voltage is “full-wave,” C discharges for
approximately only half as long as in the half-wave case.
Thus, for a given ripple voltage, only half the capacitance is
required (all other parameters being equal).
That is, a factor of 2 appears in denominator of eq. (93):
Remember though, the design equation is valid only for small Vr .

Introduction to Electronics 76Bipolar Junction Transistors (BJTs)
collector
n-type
n-type
emitter
p-type base
C
B
E
vCE
vBE
+
+
-
-
iC
iE
iB
C
B
E
Fig. 115. The npn BJT representative physical
structure (left), and circuit symbol (right).
Bipolar Junction Transistors (BJTs)
Introduction
The BJT is a nonlinear, 3-terminal device based on the junction
diode. A representative structure sandwiches one semiconductor
type between layers of the opposite type. We first examine the npn
BJT:
Two junctions: collector-
base junction (CBJ);
emitter-base junction
(EBJ).
Current in one p-n
junction affects the
current in the other p-n
junction.
There are four regions of
operation:
Operating Region EBJ CBJ Feature
cutoff rev. rev. iC = iE = iB = 0
active fwd. rev. amplifier
saturation fwd. fwd. vCE nearly zero
inverse rev. fwd. limited use
We’re most interested in the active region, but will have to deal with
cutoff and saturation, as well.
Discussion of inverse region operation is left for another time.

C
B
E
n
p
n
Fig. 116. Active-region
BJT currents.
Qualitative Description of BJT Active-Region Operation
G Emitter region is heavily doped . . .lots of electrons available
to conduct current.
G Base region very lightly doped and very narrow . . .very few
holes available to conduct current.
G Rev-biased CBJ collector positive w.r.t base.⇒
G Fwd-biased EBJ base positive w.r.t emitter.⇒
G Emitter current, iE , consists mostly of electrons being injected
into base region; because the base is lightly doped, iB is small.
Some of the injected electrons combine with holes in base
region.
Most of the electrons travel across the narrow base and are
attracted to the positive collector voltage, creating a collector
current!!!
G The relative current magnitudes are
indicated by the arrow thicknesses in the
figure.
G Because iB is so small, a small change in
base current can cause a large change in
collector current - this is how we get this
device to amplify!!!

vCE
vBE
+
+
-
-
iC
iE
iB
C
B
E
Fig. 117. Npn BJT
schematic symbol.
i I
v
V
E ES
BE
T
=





 −





exp 1 (95)
i i iE B C= + (96)
α =
i
i
C
E
(97)
Quantitative Description of BJT Active-Region Operation
The emitter-base junction (EBJ) is a diode and
is governed by the Shockley eqn.:
where, IES ranges from pA to fA
and n is usually 1≈
Also, from KCL:
In the active region (only!!!) iC is a fixed % of iE, which is dependent
on the manufacturing process.
We assign the symbol α to that ratio, thus:
Ideally, we would like α = 1. Usually, α falls between 0.9 and 1.0,
with 0.99 being typical.
Remember!!! Eqs. (95) and (96) apply always.
Eq. (97) applies only in the active region.

i i I
v
V
C E ES
BE
T
= =





 −





α α exp 1 (98)
i I
v
V
C S
BE
T
≈





exp (99)
( )i i i i i i i iE C B E E B B E= + ⇒ = + ⇒ = −α α1 (100)
( )
i
i
i
i
C
B
E
E
=
−
=
−
=
α
α
α
α
β
1 1
(101)
α
β
β
=
+1
(102)
i iC B= β (103)
From eqs. (95) and (97) we have:
and for a forward-biased EBJ, we may approximate:
where the scale current, IS = αIES .
Also, from eqs. (96) and (97) we have:
thus
Solving the right-hand half of eq. (101) for α:
For α = 0.99, we have β = 100. Rearranging eq. (101) gives:
Thus, small changes in iB produce large changes in iC , so again we
see that the BJT can act as an amplifier!!!

Introduction to Electronics 80BJT Common-Emitter Characteristics
vBE
+
-
vCE
+
-
iB
iC
+
+ -
-
Fig. 118.Circuit for measuring
BJT characteristics.
Fig. 119. Typical input characteristic of an npn BJT.
BJT Common-Emitter Characteristics
Introduction
We use the term common-emitter
characteristics because the emitter is
common to both voltage sources.
The figure at left represents only how we
might envision measuring these
characteristics. In practice we would
never connect sources to any device
without current-limiting resistors in
series!!!
Input Characteristic
First, we measure the iB - vBE relationship (with vCE fixed). Not
surprisingly, we see a typical diode curve:
This is called the input characteristic because the base-emitter will
become the input terminals of our amplifier.

vBE
+
-
vCE
+
-
iB
iC
+
+ -
-
Fig. 120. Circuit for
measuring BJT characteristics
(Fig. 118 repeated).
Fig. 121. Typical output characteristics of an npn BJT.
Output Characteristics
Next, we measure a family of iC - vCE curves for various values of
base current:
Active Region:
Recall that the active region requires that the EBJ be forward-
biased, and that the CBJ be reverse-biased.
A forward-biased EBJ means that vBE 0.7 V. Thus, the CBJ will≈
be reverse-biased as long as vCE > 0.7 V.
Note that iC and iB are related by the ratio β, as long as the BJT is
in the active region.
We can also identify the cutoff and saturation regions . . .

Fig. 122. BJT output characteristics with cutoff and saturation
regions identified.
Cutoff:
The EBJ is not forward-biased (sufficiently) if iB = 0. Thus the cutoff
region is the particular curve for iB = 0 (i.e., the horizontal axis).
Saturation:
When the EBJ is forward-biased, vBE 0.7 V. Then, the CBJ is≈
reverse-biased for any vCE > 0.7 V. Thus, the saturation region lies
to the left of vCE = 0.7 V.
Note that the CBJ must become forward-biased by 0.4 V to 0.5 V
before the iC = βiB relationship disappears, just as a diode must be
forward-biased by 0.4 V to 0.5 V before appreciable forwardcurrent
flows.

Introduction to Electronics 83The pnp BJT
collector
p-type
p-type
emitter
n-type base
C
B
E
vEC
vEB +
+
-
-
iC
iE
iB
C
B
E
Fig. 123. A pnp BJT and its schematic symbol. Note
that the current and voltage references have been
reversed.
i i i i I
v
VE B C E ES
EB
T
= + =





 −





and exp 1 (104)
i i i i i I
v
V
C E C B C S
EB
T
= = ≈





α β, expand (105)
The pnp BJT
We get the same behavior with an n-type base sandwiched
between a p-type collector and a p-type emitter:
Now current in a fwd.
biased EBJ flows in the
opposite direction . . .
. . . iC and iE resulting
from active region
operation also flow in the
opposite direction.
Note that the voltage and
current references are
reversed.
But the equations have
the same appearance:
In general,
And for the active region in particular,
where, the latter equation is the approximation for a forward-biased
EBJ.

Introduction to Electronics 84The pnp BJT
Fig. 124. Input characteristic of a pnp BJT.
Fig. 125. Output characteristics of a pnp BJT.
Because the voltage and current references are reversed, the input
and output characteristics appear the same also:

Introduction to Electronics 85BJT Characteristics - Secondary Effects
Fig. 126. BJT output characteristics illustrating Early voltage.
BJT Characteristics - Secondary Effects
The characteristics of real BJTs are somewhat more complicated
than what has been presented here (of course!!!).
One secondary effect you need to be aware of . . .
G Output characteristics are not horizontal in the active region,
but have an upward slope . . .
G This is due to the Early effect, a change in base width as vCE
changes (also called base width modulation) . . .
G Extensions of the actual output characteristics intersect at the
Early voltage, VA . . .
G Typical value of VA is 50 V to 100 V.
Other secondary effects will be described as needed.

Introduction to Electronics 86The n-Channel Junction FET
n-type
Drain
Gate
Source
p vDS
vGS
+
+
-
-
iD
iD
iG = 0
D
G
S
channel
p
Fig. 127. The n-channel JFET
representative physical structure (left) and schematic
symbol (right).
n
Drain
Gate
Source
p p
Fig. 128. Depletion region
depicted for vGS = 0, vDS = 0.
The n-Channel Junction FET (JFET)
The field-effect transistor, or FET, is also a 3-terminal device, but
it is constructed, and functions, somewhat differently than the BJT.
There are several types. We begin with the junction FET (JFET),
specifically, the n-channel JFET.
Description of Operation
The p-n junction is a
typical diode . . .
Holes move from p-type
into n-type . . .
Electrons move from n-
type into p-type . . .
Region near the p-n
junction is left without
any available carriers -
depletion region
The depletion region is shown at left
for zero applied voltage (called zero
bias). . .
Carriers are still present in the n-type
channel . . .
Current could flow between drain and
source (if vDS 0) . . .≠
Channel has relatively low resistance.

n
Drain
Gate
Source
p p
vGS < 0
+
-
Fig. 129.
Depletion region for negative
vGS (reverse bias).
n
Drain
Gate
Source
p p
vGS = VP
+
-
Fig. 130. Depletion region at
pinch-off (vGS = VP).
Fig. 131. FET i-v curves for small
vDS .
As the reverse bias increases across
the p-n junction, the depletion region
width increases,
Because negative voltage at the Gate
pulls holes away from junction,
And positive voltage at the Source
pulls electrons away from junction.
Thus, the channel becomes narrower,
and the channel resistance increases.
With sufficient reverse bias the
depletion region pinches-off the entire
channel:
vGS = VP , pinch-off voltage
The channel resistance becomes
infinite; current flow impossible for
any vDS (less than breakdown).
Typical values: -5 < VP < -2
Thus, the FET looks like a voltage-
controlled resistance at small values
of vDS .
This region of FET operation is called
the voltage-controlled resistance, or
triode, region.

n
Drain
Gate
Source
p p 0 < vDS < |VP|
+
-
Fig. 132. Asymmetrical depletion
region as vDS increases.
n
Drain
Gate
Source
p p vDS |VP|
+
-
Fig. 133.Pinch-off at drain end for
vDS = VP .
Fig. 134. N-channel JFET output
characteristics (2N3819).
Now, as vDS increases, the depletion region becomes asymmetrical:
Reverse bias is greater at the drain
end, so the depletion region is greater
at the drain end.
Thus the channel becomes more
restricted and, for fixed vGS, i-v curves
become flatter (i.e., more horizontal).
For vDS = |VP | channel becomes
pinched-off only at drain end.
Carriers drift across pinched-off region
under influence of the E field.
The rate of drift, and therefore the
drain current flow, is dependent on
width of entire channel (i.e., on vGS),
but independent of vDS!!!
As vGS changes, the curves
become horizontal at different
values of drain current.
Thus, we have a device with
the output characteristics at
left.
Note that they are very similar
to BJT curves, though the
physical operation is very
different.

iD = 0 (106)
( )[ ]i K v V v vD GS P DS DS= − −2 2
(107)
( )i K v V v vD GS P DS DS= −2 , for small (108)
( )
R
v
i K v V
channel
DS
D GS P
≈ ≈
−
1
2
(109)
( )i K v VD GS P= −
2
(110)
Equations Governing n-Channel JFET Operation
Cutoff Region:
The FET is in cutoff for vGS VP , and for any vDS :≤
Triode Region:
The FET is in the triode region for 0 > vGS > VP , and vGD > VP :
where K has units of amperes per square volt, A/V2
For very small values of vDS , the vDS
2
term in the above eguation is
negligible:
and the channel resistance is approximately given by:
Pinch-Off Region:
The FET is in the pinch-off region for 0 > vGS > VP , and vGD < VP :
The pinch-off region (also called the saturation region) is most
useful for amplification.
Note that vGS is never allowed to forward bias the p-n junction !!!

v V v v V v V vGD P GS DS P GS P DS= ⇒ − = ⇒ − = (111)
Fig. 135. 2N3819 n-channel JFET output
characteristics showing the triode - pinch-off
boundary.
v V
i
K
GS P
D
− = (112)
v
i
K
i KvDS
D
D DS= ⇒ =
2
(113)
The Triode - Pinch-Off Boundary
We know pinch-off just occurs at the drain end when:
But from eq. (110)
Combining eqs. (111) and (112) gives the boundary:
The output characteristics exhibit a breakdown voltage for
sufficient magnitude of vDS .
“Real” output characteristics also have an upward slope and
can be characterized with an “Early” voltage, VA .

Fig. 136. 2N3819 n-channel JFET transfer
characteristic.
2
(114)
K
I
V
DSS
P
= 2 (115)
The Transfer Characteristic
Because the gate-channel p-n junction is reversed biased always,
the input i-v characteristic of a FET is trivial.
However, the pinch-off region equation (110), repeated below,
gives rise to a transfer characteristic:
IDSS is the zero-gate-voltage drain current. Substituting iD = IDSS and
vGS = 0 into eq. (114) gives a relationship between K and IDSS :

Introduction to Electronics 92Metal-Oxide-Semiconductor FETs (MOSFETs)
p-type substrate (body)
n n
metal SiO2
channel
S DG
B
S
D
G B
Fig. 137. The n-channel depletion MOSFET representative
physical structure (left) and schematic symbol (right).
Metal-Oxide-Semiconductor FETs (MOSFETs)
MOSFETs are constructed quite differently than JFETs, but their
electrical behavior is extremely similar . . .
The n-Channel Depletion MOSFET
The depletion MOSFET is built horizontally on a p-type substrate:
G n-type wells, used for the source and drain, are connected by
a very thin n-type channel . . .
G The gate is a metallized layer insulated from the channel by a
thin oxide layer . . .
G Negative gate voltages repel electrons from the channel,
causing the channel to narrow . . .
When vGS is sufficiently negative (vGS = VP ), the channel is
pinched-off . . .
G Positive gate voltages attract electrons from the substrate,
causing the channel to widen . . .

Introduction to Electronics 93Metal-Oxide-Semiconductor FETs (MOSFETs)
p-type substrate (body)
n n
metal SiO2
S DG
B
S
D
G B
Fig. 138. The n-channel enhancement MOSFET physical
structure (left) and schematic symbol (right).
The n-Channel Enhancement MOSFET
The MOSFET is built horizontally on a p-type substrate. . .
G n-type wells, used for the source and drain, are not connected
by a channel at all . . .
G The gate is a metallized layer insulated from the channel by a
thin oxide layer . . .
G Positive gate voltages attract electrons from the substrate . . .
When vGS is sufficiently positive, i.e., greater than the threshold
voltage, VTH , an n-type channel is formed (i.e., a channel is
enhanced) . . .
VTH functions exactly like a “positive-valued VP “

Introduction to Electronics 94Comparison of n-Channel FETs
iD
vGS
VP
IDSS
Fig. 139. Transfer char.,
n-channel JFET.
iD
vGS
VP
IDSS
Fig. 140. Transfer char., n-
channel depletion MOSFET.
iD
vGS
VTH
Fig. 141. Transfer char., n-
channel enhancement MOSFET.
2
(116)
2
(117)
( )i K v VD GS TH= −
2
(118)
Comparison of n-Channel FETs
G The n-channel JFET can only have
negative gate voltages . . .
p-n junction must remain reversed
biased . . .
Actual device can operate with vGS
slightly positive, approx. 0.5 V max.
G The n-channel depletion MOSFET
can have either negative or positive
gate voltages . . .
Gate current prevented by oxide
insulating layer in either case.
G The n-channel enhancement
MOSFET can have only positive
gate voltages . . .
Gate current prevented by oxide
insulating layer . . .
Only the notation changes in the
equation:

Introduction to Electronics 95Comparison of n-Channel FETs
Fig. 142. Typical output characteristics,
n-channel JFET.
n-channel depletion MOSFET.
n-channel enhancement MOSFET.
n-channel FET output characteristics differ only in vGS values:

Introduction to Electronics 96p-Channel JFETs and MOSFETs
vDS
vGS
+
+
-
-
iD
iD
iG =0
D
G
S S
D
G B
iD
iG =0
vGS
+
-
S
D
G B
iD
iG =0
vGS
+
-
Fig. 145.Schematic symbols for p-channel FETs.
From left to right: JFET, depletion MOSFET, enhancement MOSFET.
p-Channel JFETs and MOSFETs
By switching n-type semiconductor for p-type, and vice versa, we
create p-channel FETs . . .
The physical principles of operation are directly analogous . . .
Actual current directions and voltage polarities are reversed from
the corresponding n-channel devices . . .
Schematic symbols simply have the arrows reversed (because
arrow indicates direction of forward current in the corresponding p-n
junction):
Note the same reference directions and polarities for p-channel
devices as we used for n-channel devices . . .
i-v curves for p-channel FETs are identical to n-channel curves,
except algebraic signs are reversed.

VTHVP
n-ch. JFET
n-ch. depl. MOSFET
n-ch. enh. MOSFET
VPVTH
p-ch. JFET
p-ch. depl. MOSFET
p-ch. enh. MOSFET
Fig. 146. Comparison of p-channel and n-channel transfer
characteristics.
Fig. 147. Typical p-channel transfer
characteristic.
Fig. 148. Typical p-channel transfer
characteristic.
For comparing transfer characteristics on p-channel and n-channel
devices, the following approach is helpful:
But more often you’ll see negative signs used to labels axes, or
values along the axes, such as these examples:

Fig. 149. Typical p-channel output
characteristic.
Fig. 150. Typical p-channel output
characteristic.
iD = 0 (119)
( )[ ]i K v V v vD GS P DS DS= − −2 2
(120)
2
(121)
Output characteristics for p-channel devices are handled in much
the same way:
Equations governing p-channel operation are exactly the same as
those for n-channel operation. Replacing VP with VTH as necessary,
they are:
Cutoff Region:
(in cutoff for vGS VP , and for any vDS )≥
Triode Region:
(for vGS < VP , and vGD < VP )
where K is negative, and has units of -A/V2
Pinch-Off Region:
(for vGS < VP , and vGD > VP )

Introduction to Electronics 99Other FET Considerations
D
G B
S
Fig. 151. Zener-diode gate
protection of a MOSFET.
D
G
S
Fig. 152. Normal
MOSFET body-
source connection.
Other FET Considerations
FET Gate Protection
The gate-to-channel impedance (especially in MOSFETs) can
exceed 1 GΩ !!!
To protect the thin gate oxide layer, zeners are often used:
Zeners can be used externally, but are
usually incorporated right inside the FET
case.
Many FET device types available with or
without zener protection.
Zener protection adds capacitance, which
reduces FET performance at high
frequencies.
The Body Terminal
In some (rare) applications the body terminal
of MOSFETs is used to influence the drain
current.
Usually the body is connected to the source
terminal or a more negative voltage (to
prevent inadvertently forward-biasing the
channel-body parasitic diode).

Introduction to Electronics 100Basic BJT Amplifier Structure
++
+
+
-
-
RB
RC
VCC
VBB
vin
+
-
+
-+
-
vCE
vBE
iC
iB
Fig. 153. Basic BJT amplifier structure.
V v i R vBB in B B BE+ = + (122)
iB
vBE
VBB
VBB /RB
VBB +vin maxVBB -vin max
iB max
IBQ
iB min
Q
Fig. 154. Load-line analysis around base-emitter loop.
V i R vCC C C CE= + (123)
Basic BJT Amplifier Structure
Circuit Diagram and Equations
The basic BJT amplifier takes the form
shown:
KVL equation around B-E loop:
KVL equation around C-E loop:
Load-Line Analysis - Input Side
Remember that the base-emitter is a diode.
The Thevenin resistance is constant, voltage varies with time, but
the Thevenin. Thus, the load line has constant slope (-1/RB ), and
moves with time.

iB
vBE
VBB
VBB /RB
VBB +vin maxVBB -vin max
iB max
IBQ
iB min
Q
Fig. 155. Load-line analysis around base-emitter loop
G The load line shown in red for vin = 0.
When vin = 0, only dc remains in the circuit.
This iB , vBE operating pt. is called the quiescent pt.
The Q-point is given special notation: IBQ , VBEQ
G Maximum excursion of load line with vin is shown in blue.
G Minimum excursion of load line with vin is shown in green.
G Thus, as vin varies through its cycle, base current varies from
iB max to iB min .
The base-emitter voltage varies also, from vBE max to vBE min ,
though we are less interested in vBE at the moment.

++
+
+
-
-
RB
RC
VCC
VBB
vin
+
-
+
-+
-
vCE
vBE
iC
iB
Fig. 156. Basic BJT amplifier structure
Fig. 157. Amplifier load line on BJT output characteristics.
Load-Line Analysis - Output Side
Returning to the circuit, observe
that VCC and RC form a Thevenin
equivalent, with output variables
iC and vCE .
Thus we can plot this load line on
t h e t r a n s i s t o r o u t p u t
characteristics!!!
Because neither VCC nor RC are
time-varying, this load line is
fixed!!!

Fig. 158. Amplifier load line on BJT output characteristics
G The collector-emitter operating point is given by the
intersection of the load line and the appropriate base current
curve . . .
when vin = 0, iB = IBQ , and the quiescent pt. is ICQ , VCEQ
at vin max , iB = iB max , and the operating pt. is iC max , vCE min
at vin min , iB = iB min , and the operating pt. is iC min , vCE max
G If the total change in vCE is greater than total change in vin , we
have an amplifier !!!

++
+
+
-
-
RB = 10 kΩ
VCC = 10 V
VBB = 1 V
vin = 0.1 sin ωt V
+
-
+
-+
-
vCE
vBE
iC
iB
RC = 1 kΩ
Q1
2N2222
Fig. 159. Example circuit illustrating basic amplifier
structure.
Fig. 160. PSpice-simulated 2N2222 input characteristic.
A Numerical Example
Let’s look at a PSpice simulation of realistic circuit:
First we generate the input characteristic and draw the appropriate
base-emitter circuit load lines:

Fig. 161. 2N2222 output characteristics, with curves for base currents of (from
bottom to top) 4 µA, 13 µA, 22 µA, 31 µA, 40 µA, and 49 µA.
A
v
v
!!!v
CE
in
= = = −
∆
∆
2.95V - 6.11V
V0 2
15 8
.
. (124)
Using the cursor tool in the PSpice software plotting package, we
determine:
iB min = 22 µA IBQ = 31 µA iB max = 40 µA
Next we generate the output characteristics and superimpose the
collector-emitter circuit load line:
The resulting collector-emitter voltages are:
vCE min = 2.95 V VCEQ = 4.50 V vCE max = 6.11 V
Finally, using peak-to-peak values we have a voltage gain of:

Fig. 162. Input waveform for the circuit of Fig. 159.
Fig. 163. Output (collector) waveform for the circuit of Fig. 159.
Of course, PSpice can give us the waveforms directly (and can
even give us gain, if we desire):

Introduction to Electronics 107Basic FET Amplifier Structure
+
+
-
VDD = 15 V
VBB = -1 V
vin = 0.5 sin ωt V
+
-
+
-+
-
vDS
vGS
iD
RD = 1 kΩ
J1
2N3819
Fig. 164. Basic FET amplifier structure.
V v vGG in GS+ = (125)
V i R vDD D D DS= + (126)
Basic FET Amplifier Structure
The basic FET amplifier takes the same form as the BJT amplifier.
Let’s go right to a PSpice simulation example using a 2N3819 n-
channel JFET:
Now, KVL around the gate-source loop gives:
while KVL around the drain-source loop gives the familiar result:
Because iG = 0, the FET has no input characteristic, but we can plot
the transfer characteristic, and use eq. (125) to add the appropriate
load lines.
In this case, the load line locating the Q point, i.e., the line for
vin = 0, is called the bias line:

Fig. 165. PSpice-generated 2N3819 transfer characteristic showing the bias line,
and lines for vGS min and vGS max .
v iGS Dmin min
. .= − ⇒ =15 3 00V mA (127)
V IGSQ DQ= − ⇒ =10 530. .V mA (128)
v iGS Dmax max
. .= − ⇒ =05 8 22V mA (129)
From the transfer characteristic, the indicated gate-source voltages
correspond to the following drain current values:
Note, however, that we could have gone directly to the output
characteristics, as the parameter for the family of output curves is
vGS :

Fig. 166. 2N3819 output characteristics, with curves for gate-source voltages of
(from bottom to top) -3 V, -2.5 V, -2 V, -1.5 V, -1 V, -0.5 V, and 0 V.
v vGS DSmin max
. .= − ⇒ =15 120V V (130)
V VGSQ DSQ= − ⇒ =10 9 70. .V V (131)
v vGS DSmax min
. .= − ⇒ =05 678V V (132)
A
v
v
!!!v
DS
GS
= = = −
∆
∆
6.78V -12.0V
1V
5 22. (133)
From the output characteristics and the drain-source load line, the
indicated gate-source voltages correspond to the following drain-source
voltage values:
Thus, using peak-to-peak values, we have a voltage gain of:

Introduction to Electronics 110Amplifier Distortion
Fig. 167. Output (drain) waveform for the FET amplifier example.
Amplifier Distortion
Let’s look at the output waveform (vDS ) of the previous example:
Can you discern that the output sinusoid is distorted ?
The positive half-cycle has an amplitude of
12.0 V - 9.70 V = 2.30 V
while the negative half cycle has an amplitude of
9.70 V - 6.78 V = 2.92 V
This distortion results from the nonlinear (2nd
-order) transfer
characteristic, the effects of which also can be seen in the
nonuniform spacing of the family of output characteristics . . .
BJT’s are also nonlinear, though less prominently so . . .

Introduction to Electronics 111Amplifier Distortion
+
+
-
VDD = 15 V
VBB = -1.5 V
vin = 1.5 sin ωt V
+
-
+
-+
-
vDS
vGS
iD
RD = 1.3 kΩ
J1
2N3819
Fig. 168. Slight changes to the FET amplifier example to
illustrate nonlinear distortion.
Fig. 169. Severely distorted output waveform resulting from operation in the
cutoff region (top) and the triode region (bottom).
Distortion also results if the instantaneous operating point along the
output-side load line ventures too close to the saturation or cutoff
regions for the BJT (the triode or cutoff regions for the FET), as the
following example illustrates:

Introduction to Electronics 112Biasing and Bias Stability
Biasing and Bias Stability
Notice from the previous load line examples:
G The instantaneous operating point moves with instantaneous
signal voltage.
Linearity is best when operating point stays within the active
(BJTs) or pinch-off (FETs) regions.
G The quiescent point is the dc (zero signal) operating point.
It lies near the “middle” of the range of instantaneous
operating points.
This dc operating point is required if linear amplification is to
be achieved !!!
G The dc operating point (the quiescent point, the Q point, the
bias point) obviously requires that dc sources be in the circuit.
G The process of establishing an appropriate bias point is called
biasing the transistor.
G Given a specific type of transistor, biasing should result in the
same or nearly the same bias point in every transistor of that
type . . . this is called bias stability.
Bias stability can also mean stability with temperature, with
aging, etc.
We study BJT and FET bias circuits in the following pages . . .

Introduction to Electronics 113Biasing BJTs - The Fixed Bias Circuit
RB RC
VCC
iC
+
-
vCE
Fig. 170. BJT fixed bias circuit.
I
V V
R
B
CC BE
B
=
−
= =
15
200
715
V - 0.7V
k
A
Ω
. µ (134)
I I V V I RC B CE CC C C= = ⇒ = − =β 715 785. .mA V (135)
I
V V
R
B
CC BE
B
=
−
= =
15
200
715
V - 0.7V
k
A
Ω
. µ (136)
I I V V I RC B CE CC C C= = ⇒ = − = −β 215 6 45. .mA V (137)
Biasing BJTs - The Fixed Bias Circuit
Example
We let VCC = 15 V,
RB = 200 kΩ, and RC = 1 kΩ
β varies from 100 to 300
To perform the analysis, we
assume that operation is in the
active region, and that VBE = 0.7 V.
For β = 100:
Q. Active region??? A. VCE > 0.7 V and IB > 0 Yes!!!⇒
For β = 300:
Q. Active region? A. VCE < 0.7 V No!!! Saturation!!!⇒
Thus our calculations for β = 300 are incorrect, but more importantly
we conclude that fixed bias provides extremely poor bias stability!!!

Introduction to Electronics 114Biasing BJTs - The Constant Base Bias Circuit
RE
RC
VCC
iC
+
-
vCE
+
VBB
-
Fig. 171. BJT constant base bias
circuit.
I
V V
R
I IE
BB BE
E
C E=
−
= ⇒ =
+
=215
1
213. .mA mA
β
β
(138)
V V I R I RCE CC C C E E= − − = 6 44. V (139)
I
V V
R
I IE
BB BE
E
C E=
−
= ⇒ =
+
=215
1
214. .mA mA
β
β
(140)
V V I R I RCE CC C C E E= − − = 6 41. V (141)
Biasing BJTs - The Constant Base Bias Circuit
Example
Now we let VCC = 15 V and VBB = 5 V
RC = 2 kΩ and RE = 2 kΩ
β varies from 100 to 300
And we assume operation in active
region and VBE = 0.7 V, as before.
Though not explicitly shown here, the
active-region assumption must always
be verified.
For β = 100:
For β = 300:
Thus we conclude that constant base bias provides excellent bias
stability!!! Unfortunately, we can’t easily couple a signal into this
circuit, so it is not as useful as it may first appear.

Introduction to Electronics 115Biasing BJTs - The Four-Resistor Bias Circuit
R1
R2
RC
RE
VCC
Fig. 172. The four-resistor bias
circuit.
R1
R2
RC
RE
VCCVCC
+ +
- -
Fig. 173. Equivalent after “trick” with supply voltage.
RB
RC
RE
VCC
VBB
+
+
-
-
Fig. 174. Final equivalent after using Thevenin’s
Theorem on base divider.
Biasing BJTs - The Four-Resistor Bias Circuit
Introduction
This combines features of fixed bias and constant base bias, but it
takes a circuit-analysis “trick” to see that:

RB
RC
RE
VCC
VBB
+
+
-
-
Fig. 175. Four-resistor bias circuit equivalent
V I R V I RBB B B BE E E= + + (142)
( )V I R V I RBB B B BE B E= + + +β 1 (143)
( )
I
V V
R R
B
BB BE
B E
=
−
+ +β 1
(144)
( )
( )
β
β
β
I I
V V
R R
B C
BB BE
B E
= =
−
+ +1
(145)
V V I R I RCE CC C C E E= − − (146)
Circuit Analysis
Analysis begins with KVL around b-e loop:
But in the active region IE = (β + 1)IB :
Now we solve for IB :
And multiply both sides by β :
We complete the analysis with KVL around c-e loop:

( )
( )
β
β
β
I I
V V
R R
B C
BB BE
B E
= =
−
+ +1
(147)
Bias Stability
Bias stability can be illustrated with eq. (145), repeated below:
Notice that if RE = 0 we have fixed bias, while if RB = 0 we have
constant base bias.
To maximize bias stability:
G We minimize variations in IC with changes in β . . .
By letting (β + 1)RE >> RB ,
Because then β and (β + 1) nearly cancel in eq. (147).
Rule of Thumb: let (β + 1)RE 10 RB≈ 




=β 100
Equivalent Rule: let I IR B2
10≈ max
G We also minimize variations in IC with changes in VBE . . .
By letting VBB >> VBE .
Rule of Thumb: let V V V VR CE R CCC E
≈ ≈ ≈
1
3
Because if VBE and IB are small.V VR BBE
≈

RC
R2 5 kΩ
15 V
1 kΩ
R1
RE
10 kΩ 1 kΩ
Fig. 176. Example circuit.
RB = 3.3 kΩ
RC
RE
+
+
-
-
1 kΩ
1 kΩ
5 V
15 V
Fig. 177. Equivalent circuit.
( )
I
V V
R R
I IB
BB BE
B E
C B=
−
+ +
= ⇒ = =
β
µ β
1
412 412. .A mA (148)
⇒ = = ⇒ = − − =I
I
V V I R I RE
C
CE CC C C E E
α
416 6 72. .mA V (149)
( )
I
V V
R R
I IB
BB BE
B E
C B=
−
+ +
= ⇒ = =
β
µ β
1
141 4 24. .A mA (150)
⇒ = = ⇒ = − − =I
I
V V I R I RE
C
CE CC C C E E
α
4 25 6 50. .mA V (151)
Example
For β = 100 (and VBE = 0.7 V):
For β = 300:
Thus we have achieved a reasonable degree of bias stability.

Introduction to Electronics 119Biasing FETs - The Fixed Bias Circuit
VDD
VGG
RD
RG
iD
vDS
vGS
+
+
- -
+
-
Fig. 178. FET fixed bias circuit.
.iD
vGS
VGSQ
IDQ
IDQ
High-current device
Low-current device
Fig. 179. Graphical illustration of fixed bias using an
n-channel JFET.
Biasing FETs - The Fixed Bias Circuit
Just as the BJT parameters b and
VBE vary from device to device, so
do the FET parameters K and VP (or
VTH).
Thus, bias circuits must provide bias
stability, i.e., a reasonably constant
IDQ .
We look first at the fixed bias circuit
shown at left, and note that
VGG = vGSQ .
For an n-channel JFET, note
that VGG must be < 0, which
requires a second power
supply.
For an n-ch. depl. MOSFET,
VGG can be either positive or
negative.
For an n-ch. enh. MOSFET,
VGG must be > 0
Finally, note the complete lack of bias stability. Fixed bias is not
practical!!!

Introduction to Electronics 120Biasing FETs - The Self Bias Circuit
VDD
RD
RG
vDS
vGS
+
+
- -
RS
iD
RS iD
+
-
Fig. 180. FET self-bias circuit.
iD
vGS
IDQ
IDQ
High-current device
Low-current device
Bias line
vGS = -RS iD
Fig. 181. Graphical solution to self-bias circuit,
showing improved stability.
v i RGS D S= − (152)
2
(153)
Biasing FETs - The Self Bias Circuit
From a KVL equation around the
gate-source loop we obtain the bias
line:
And, assuming operation in the
pinch-off region:
Solving simultaneously provides the
Q point. A graphical solution is
shown, below left.
Note the improvement in bias
stability over a fixed bias approach.
Note also that VGSQ can only be
negative. Thus, self-bias is not
suitable for enhancement
MOSFETs!
An analytical solution requires the quadratic formula (though a good
guess often works) - the higher current solution is invalid (why?).

Introduction to Electronics 121Biasing FETs - The Fixed + Self Bias Circuit
VDD
R2 RS
RDR1
Fig. 182. Fixed + self-bias
circuit for FETs.
VDD
RD
RG
vDS
+
-
RS
iD
VG
+
-
Fig. 183. Equivalent circuit after using
Thevenin’s Theorem on gate divider.
v V i RGS G D S= − (154)
2
(155)
Biasing FETs - The Fixed + Self Bias Circuit
This is just the four-resistor bias circuit with a different name!!!
A KVL equation around gate-source loop provides the bias line:
And, as usual, assuming operation in the pinch-off region:
Simultaneous solution provides Q-point - see next page.

Introduction to Electronics 122Biasing FETs - The Fixed + Self Bias Circuit
iD
vGS
VG
IDQ
IDQ
High-current device
Low-current device
Bias line
vGS = VG - RS iD
Intercept at
VG / RS
Fig. 184. Graphical solution to fixed + self bias circuit.
G Note that bias stability can be much improved over that
obtained with self-bias.
The degree of stability increases as VG or RS increases.
Rule of thumb: let V V V VR DS R DDD S
= = =
1
3
G Other considerations:
Because IG = 0, R1 and R2 can be very large (e.g., MΩ).
Because VG can be > 0, this circuit can be used with any FET,
including enhancement MOSFETs.

Introduction to Electronics 123Design of Discrete BJT Bias Circuits
iC
vCE
VCC
RC + RE
VCC
PMAX = iC vCE
Q-point area
Fig. 185. Typical BJT output characteristics.
Design of Discrete BJT Bias Circuits
In the next few sections we shall look at biasing circuits in
somewhat greater detail.
Concepts of Biasing
We want bias stability because we generally desire to keep the Q-
point within some region:
In addition to voltage gain, we must consider and compromise
among the following:
G Signal Swing: If VCEQ is too small the device will saturate. If
ICQ is too small the device will cut off.
G Power Dissipation: VCEQ and ICQ must be below certain limits.
G Input Impedance: We can increase Zin with high R values.
G Output Impedance: We can decrease Zout with low R values.
G Bias Stability: We can increase stability with low R values.
G Frequency Response: A higher VCEQ lowers junction C and
improves response. A specific ICQ maximizes ft .

RE
RC
VCC
R1
R2
iB
i2
i1
iC
iE
-
vE
+
-
vB
+
Fig. 186. Four-resistor bias
circuit, revisited.
( )
( )
I
V V
R RCQ
BB BEQ
B E
=
−
+ +
β
β 1
(156)
R
V
I
R
V
I
V
I
C
R
CQ
E
E
EQ
E
CQ
C
= = ≈and (157)
( )R
V V
I
R
V V V
I I
E BEQ CC E BEQ
BQ
2
2
1
2
=
+
=
− +
+
and (158)
Design of the Four-Resistor BJT Bias Circuit
We begin where we are most familiar, by
revisiting the four-resistor bias circuit.
Assume that ICQ , VBEQ , VCC , βmin and βmax
are known. This amounts to little more
than having chosen the device and the
Q-point.
Now, recall this result from a KVL
equation around the base-emitter loop:
Design Procedure
G First, we decide how VCC divides among , VCE , VE . ForVRC
temperature stability we want VE >> temperature variation in
VBE . Recall the “one-third” rule of thumb. Then:
G Then we choose I2 (larger I2 lower RB better bias⇒ ⇒
stability lower Zin).⇒
Recall the rule of thumb: I2 = 10 IBQ max . Then:

RE
RC
+VCC
RB
iB
iC
iE
-
vB
+
-VEE
Fig. 187. Dual-supply bias ckt.
( )
( )
I
V V
R R
CQ
EE BEQ
B E
=
−
+ +
β
β 1
(159)
R
V
I
V
I
R
V V V
I
B
B
BQ
B
CQ
E
EE B BEQ
CQ
= = ≈
− −; β
and (160)
( )[ ]R
V V V V
I
V V V V
IC
CC CEQ B BEQ
CQ
CC CEQ B BEQ
CQ
=
− − − +
=
− + + (161)
Design of the Dual-Supply BJT Bias Circuit
This is essentially the same as the four-
resistor bias circuit. Only the reference
point (ground) has changed.
We begin with the same assumptions as
for the previous circuit.
Because its important that you
understand the principles used to obtain
these equations, verify that the following
results from a KVL equation around the
base-emitter loop:
Design Procedure
G Allocate a fraction of VEE for VB . For bias stability we would
like the voltage across RE to be << |VB| (i.e., RB << βRE).
A starting point, i.e., a rule of thumb is |VB| = VEE / 20. Then:
G Choose VCEQ . Here a rule of thumb is: VCEQ VCC /2. Then:≈
Note: Smaller VCEQ larger RC larger Av larger Zout⇒ ⇒ ⇒

RC
+VCC
R2
iB
iC
i2
-VEE
R1
i1
Fig. 188. Grounded-emitter
bias circuit.
( )
I
V
R
R
V V
R RCQ
CC EE BEQ
C
≈
− +






+
β
β
1
2
1
(162)
R
V V
I
R
V V
I I
R
V V
I I
EE BEQ CEQ BEQ
BQ
C
CC VEQ
CQ
2
2
1
2 1
=
+
=
−
+
=
−
+
(165)
/ 2CEQ CCV V≈ (163)
2 max10 BQI I≈ (164)
Design of the Grounded-Emitter BJT Bias Circuit
Grounding the emitter directly lowers
inductance in the emitter lead, which
increases high-frequency gain.
Bias stability is obtained by connecting
base to collector through R1 .
Verifying this approximate equation is
difficult; a derivation is provided on the
following pages:
Design Procedure
G Allocate VCC between VRc and VCEQ . With supply voltage split
between only two elements the rule of thumb becomes:
G Choose I2 . To have R1 << βRC , we want I2 >> IB . The rule of
thumb is:
G Then:

RC
+VCC
R2
iB
iC
i2
-VEE
R1
i1
Fig. 189. Grounded-emitter
bias circuit (Fig. 188 repeated).
( )
I
V
R
R
V V
R RCQ
CC EE BEQ
C
≈
− +






+
β
β
1
2
1
(166)
I I IB1 2= + (167)
( )I I I I IR C BC
= + = + +1 2 1β (168)
I
V V
R
EE BEQ
2
2
=
+
(169)
( ) ( )[ ]V V I I R I I RCC BEQ B B C= + + + + +2 1 2 1β (170)
( ) ( ) ( )V V
R
R
V V I R
R
R
V V I RCC BEQ EE BEQ B
C
EE BEQ B C= + + + + + + +1
2
1
2
1β (171)
Analysis of the Grounded-Emitter BJT Bias Circuit
Q. How do we obtain this equation?
A. We begin by noting that :
and
Then we find I2 with a KVL equation around the base-emitter loop:
Now we sum voltage rises from ground to VCC :
Substituting (169) into (170):

( ) ( ) ( )V V
R
R
V V I R
R
R
V V I RCC BEQ EE BEQ B
C
EE BEQ B C= + + + + + + +1
2
1
2
1β (172)
( ) ( ) ( )[ ]V V
R
R
V V
R
R
V V I R RCC BEQ EE BEQ
C
EE BEQ B C− − + − + = + +1
2 2
1 1β (173)
( )
I
V
R
R
V V
R RCQ
CC EE BEQ
C
=
− +






+
β
β
1
2
1
(174)
Repeating eq. (171) from the bottom of the previous page:
The next step is to collect terms:
Finally, if we apply the following approximations:
VCC - VBEQ VCC RC /R2 0 β + 1 β≈ ≈ ≈
we obtain our objective, the original approximation:

Introduction to Electronics 129Bipolar IC Bias Circuits
Bipolar IC Bias Circuits
Introduction
Integrated circuits present special problems that must be
considered before circuit designs are undertaken.
For our purposes here, the most important consideration is real
estate. Space on an IC wafer is at a premium. Anything that takes
up too much space is a liability. Consider the following:
G Resistors are very inefficient when it comes to real estate.
The area required is directly proportional to the value of
resistance (remember R = ρL / A ?).
As a result, use of resistances in ICs is avoided, if possible.
And resistances greater than 100 kΩ are extremely rare.
When used, it is quite difficult to control resistance values with
accuracy unless each resistor is laser-trimmed. Tolerances
are as large as 50% are not unusual.
Because all resistors are fabricated at the same time, all
resistors are “off” by the same amount. This means that
resistors that are intended to be equal will essentially be equal.
G Capacitors are also liabilities. Capacitance values greater
than 100 pF are virtually unheard of.
G Inductors only recently became integrable. Their use is quite
limited.
G BJTs are very efficient. And while β values suffer the same
3:1 to 5:1 variation found in discrete transistors, all BJTs on an
IC wafer are essentially identical (if intended to be).
This latter point is most important, and drives all IC circuit design.
We begin to examine this on the following pages.

IREF
IO = IC2
Q1 Q2
RREF
VCC VCC
Load
IC1
IB1 IB2
Fig. 190. Diode-biased current mirror.
I I I I IO C C C B= = = =2 1 β (175)
( )I I I I I I IREF C B B B B B= + + = + = +1 1 2 2 2β β (176)
( )
I
I
I
I
O
REF
B
B
=
+
=
+
=
+
β
β
β
β
β
2 2
1
1
2 (177)
The Diode-Biased Current Mirror
Current Ratio:
This is the most simple of all IC bias
circuit techniques.
The key here is that the BJTs are
identical !!! Because VBE1 = VBE2 , this
means that IB1 = IB2 = IB .
Note that VCB1 = 0, thus Q1 is active
(at the edge of saturation).
If we assume Q2 is also active, we
have IC1 = IC2 = IC .
From this point the analysis proceeds
straightforwardly . . .
And from a KCL equation at the collector of Q1 :
Dividing (175) by (176):
Thus, as long as Q2 remains active, for large β, IO IREF , i.e., IO≈
reflects the current IREF (hence “mirror”), regardless of the load!!!

IREF
IO = IC2
Q1 Q2
RREF
VCC VCC
Load
IC1
IB1 IB2
Fig. 191. Diode-biased current mirror
(Fig. 190 repeated.
I
V V
R
V
R
REF
CC BE
REF
CC
REF
=
−
≈
−07. V
(178)
r
i
v
o
C
CE
=






−
∂
∂
2
2
1
(179)
Reference Current:
IREF is set easily, by choosing RREF :
Output Resistance:
Finally, the output resistance seen by
the load is just the output resistance
of Q2 :

IC2
VCE2
Compliance Range
ro = 1/slope
0.5 V BV
Fig. 193. Example of the compliance range of a
current mirror. The diode-biased mirror is
represented in this figure.
VCC
-VEE
Amplifier
Current
Mirror
Fig. 194. Follower
biased with a current
nirror.
VCC
-VEE
IDC
Fig. 195. Representation
of the mirror circuit of
Fig. 194.
Fig. 192.
Compliance Range
This is defined as the range of
voltages over which the mirror
circuit functions as intended.
For the diode-biased mirror, this
is the range where Q2 remains
active.
Using a Mirror to Bias an Amplifier
Changing transistor areas gives mirror ratios other than
unity, which is useful to obtain small currents without
using large R values. The schematic technique used to
show integer ratios other than unity is shown.

IREF
RREF
Q1 Q3
Q2
IO = IC2
VCC
Load
VCC
Fig. 196. Wilson current mirror.
( )I I I IE C B B2 3 2 2= + = +β (180)
( )I I I IO C E B= =
+
=
+
+
2 2
1
2
1
β
β
β β
β
(181)
I I IB E B2 2
1
1
2
1
=
+
=
+
+β
β
β
(182)
I I I I IREF C B B B= + = +
+
+
1 2
2
1
β
β
β
(183)
Wilson Current Mirror
Current Ratio:
The addition of another transistor
creates a mirror with an output
resistance of βro2 (very large!!!)≈
Because VBE1 = VBE3 we know that
IB1 = IB3 = IB .
Because VCB3 = 0, Q3 is active.
Because VCB1 = VBE2 , Q1 is active.
Thus we know that IC1 = IC3 = βIB .
We assume also that Q2 is active.
We proceed with the mathematical derivation without further
comment.

( ) ( )
( )
( )
( ) ( )
I
I
I
I I
O
REF
B
B B
=
+
+
+
+
+
=
+
+
+
+
+
+
+
=
+
+ + +
β β
β
β
β
β
β β
β
β β
β
β
β
β β
β β β
2
1
2
1
2
1
1
1
2
1
2
1 2
(184)
I
I
O
REF
=
+
+ +
=
+
+
≈
+
≈
β β
β β
β β β
2
2
2 2
2
2 2
1
1
2
2
1
1
2
1
(185)
I
V V V
R
V
R
REF
CC BE BE
REF
CC
REF
=
− −
≈
−2 3 14. V
(186)
Thus the Wilson mirror ratio is much closer to unity than the ratio of
the simple diode-biased mirror.
Reference Current:
The reference current can be found by summing voltages rises from
ground to VCC :
Output Resistance:
The output resistance of the Wilson can be shown to be βro2 .
However, the derivation of the output resistance is a sizable
endeavor and will not be undertaken here.

VBE1
IO = IC2
Q1 Q2
R1
VCC VCC
Load
IC1
R2
VBE2
++
- -
Fig. 197. Widlar mirror.
i I
v
V
v V
i
I
C S
BE
T
BE T
C
S
=





 =





exp lnand (187)
V V
i
I
V V
i
I
BE T
C
S
BE T
C
S
1
1
2
2
=





 =





ln lnand (188)
Widlar Current Mirror
If very small currents are required, the
resistances in the previous mirror
circuits become prohibitively large.
The Widlar mirror solves that problem
Though it uses two resistors, the total
resistance required by this circuit is
reduced substantially.
The circuit’s namesake is Bob Widlar
(wide’ lar) of Fairchild Semiconductor
and National Semiconductor.
The analysis is somewhat different than
our previous two examples.
Current Relationship:
Recall the Shockley transistor equations for forward bias:
Thus we may write:
Note that VT and IS are the same for both transistors because they
are identical (and assumed to be at the same temperature).

VBE1
IO = IC2
Q1 Q2
R1
VCC VCC
Load
IC1
R2
VBE2
++
- -
Fig. 198. Widlar mirror (Fig. 197
repeated).
V V R I V R IBE BE E BE C1 2 2 2 2 2 2= + ≈ + (189)
V V V R IBE BE BE C1 2 2 2− = ≈∆ (190)
Analysis: Design:
V
R
I
I
I R
V
I
I
I
T C
C
C
T
C
C
C2
1
2
2 2
2
1
2
ln ln





 = =





 (192)
V
I
I
V
I
I
R I V
I
I
R IT
C
S
T
C
S
C T
C
C
Cln ln ln1 2
2 2
1
2
2 2





 −





 ≈ ⇒





 ≈ (191)
I I
V V
R
C REF
CC BE
1
1
1
≈ =
−
(193)
Continuing with the derivation from the
previous page . . .
From a KVL equation around the base-
emitter loop:
Rearranging:
Substituting the base-emitter voltages from eq. (188) into eq. (190):
Where the last step results from a law of logarithms.
This is a transcendental equation. It must be solved iteratively, or
with a spreadsheet, etc. The form of the equation to use depends
on whether we’re interested in analysis or design:
where:

IREF
VCC
VCC VCC
-VEE -VEE
-VEE
Load 1 Load 2
Load 3 Load 4
Fig. 199. Multiple current mirrors.
Multiple Current Mirrors
In typical integrated circuits multiple current mirrors are used to
provide various bias currents. Usually, though, there is only one
reference current, so that the total resistance on the chip may be
minimized.
The figure below illustrates the technique of multiple current mirrors,
as well as mirrors constructed with pnp devices:
FET Current Mirrors
The same techniques are used in CMOS ICs (except, of course, the
devices are MOSFETs). The details of these circuits are not
discussed here.

Introduction to Electronics 138Linear Small-Signal Equivalent Circuits
Linear Small-Signal Equivalent Circuits
G In most amplifiers (and many other circuits):
We use dc to bias a nonlinear device . . .
At an operating point (Q-point) where the nonlinear device
characteristic is relatively straight, i.e., almost linear . . .
And then inject the signal to be amplified (the small signal) into
the circuit.
G The circuit analysis is split into two parts:
DC analysis, which must consider the nonlinear device
characteristics to determine the operating point.
Alternatively, we can substitute an accurate model, such as a
piecewise-linear model, for the nonlinear device.
AC analysis, but because injected signal is small, only a small
region of the nonlinear device characteristic need be
considered.
This small region is almost linear, so we assume it is linear,
and construct a linear small-signal equivalent circuit.
G After analysis, the resulting dc and ac values may be
recombined, if necessary or desired.

Introduction to Electronics 139Diode Small-Signal Equivalent Circuit
VDC
vs
+
vD
iD
+
-
Fig. 200. Generalized diode circuit.
iD
vD
IDQ
VDQ
Q
Fig. 201. Diode characteristic.
∆ ∆i K vD D= (194)
Diode Small-Signal Equivalent Circuit
The Concept
First, we allow vs to be zero. The circuit is now dc only, and has a
specific Q-point shown.
We can find the Q-point analytically with the Shockley equation, or
with a diode model such as the ideal, constant-voltage-drop, or
piecewise-linear model.
Now, we allow vs to be nonzero, but small.
The instantaneous operating point moves slightly above and below
the Q-point. If signal is small enough, we can approximate the
diode curve with a straight line.
The Equations
This straight-line approximation allows us to write a linear equation
relating the changes in diode current (around the Q-pt.) to the
changes in diode voltage:

∆ ∆i K vD D= (195)
iD
vD
IDQ
VDQ
Q
Fig. 202. Diode curve with tangent at
Q-point.
i
r
vd
d
d=
1
(196)
Repeating the linear equation from the previous page:
The coefficient K is the slope of the straight-line approximation, and
must have units of Ω-1
.
We can choose any straight line we want. The best choice (in a
least-squared error sense) is a line tangent at pt. Q !!!
We rewrite eq. (195) with changes in notation.
K becomes 1/rd , ∆iD becomes id , and ∆vD becomes vd :
This is merely Ohm’s Law!!!
rd is the dynamic resistance or small-signal resistance of the diode.
id and vd are the signal current and the signal voltage, respectively.

1
r
i
vd
D
D Q po
=
−
∂
∂ int
(197)
i I
v
nV
I
v
nV
D S
D
T
S
D
T
=





 −





 ≈





exp exp1 (198)
∂
∂v
I
v
nV
I
nV
V
nVD
S
D
T Q po
S
T
DQ
T
exp exp
int











 =






−
(199)
I I
V
nV
DQ S
DQ
T
≈





exp (200)
∂
∂
i
v
I
nV
r
nV
I
D
D Q po
DQ
T
d
T
DQ−
≈ ⇒ ≈
int
(201)
Diode Small-Signal Resistance
We need only to calculate the value of rd , where 1/rd is the slope of
a line tangent at pt. Q, i.e.,
We use the diode forward-bias approximation:
Thus:
But, notice from (198):
So:
Notes:
1. The calculation of rd is easy, once we know IDQ !!!
2. IDQ can be estimated with simple diode models !!!
3. Diode small-signal resistance rd varies with Q-point.
4. The diode small-signal model is simply a resistor !!!

Introduction to Electronics 142Notation
iD
t
IDQ
iD
id
Fig. 203. Illustration of various currents.
Notation
The following notation is standard:
vD , iD This is the total instantaneous quantity.
(dc + ac, or bias + signal)
VD , ID This is the dc quantity.
(i.e., the average value)
vd , id This is the ac quantity.
(This is the total instantaneous quantity with the
average removed)
Vd , Id If a vector, this is a phasor quantity. If a scalar it is
an rms or effective value.

Introduction to Electronics 143BJT Small-Signal Equivalent Circuit
VDC
vs
+
iC
iE
iB
Fig. 204. Generalized BJT circuit.
iB
t
IBQ
iB
ib
Fig. 205. Generalized base current waveform.
iB
vBE
IBQ
Q
~0.7 V
Fig. 206. BJT input characteristic.
i
i
v
v
r
vb
B
BE Q po
be be=








=
−
∂
∂ πint
1
(202)
where r
V
I
T
BQ
π ≈ (203)
BJT Small-Signal Equivalent Circuit
First, note the total base current (bias + signal): iB = IBQ + ib
This produces a total base-emitter voltage: vBE = VBEQ + vbe
Now, let the signal component be small: |ib| << IBQ
With the signal sufficiently small, vbe and ib will be approximately
related by the slope of the BJT input characteristic, at the Q-point.
This is identical to the diode small-signal development !!! Thus, the
equations will have the same form:

Introduction to Electronics 144BJT Small-Signal Equivalent Circuit
ic
ie
ib
B C
E
rπ βibvbe
+
-
Fig. 207. BJT small-signal equivalent circuit.
i i i iC B c b= ⇒ =β β (204)
With rπ determined, we can turn our attention to the output
(collector) side.
If the BJT is in its active region, we have a simple current
relationship:
Combining eqs. (202) through (204) we can construct the BJT
small-signal equivalent circuit:
Because the bias point is “accounted for” in the calculation of rπ ,
this model applies identically to npn and to pnp devices.

Introduction to Electronics 145The Common-Emitter Amplifier
RS
R1
R2
RC
RE
RL
Cin
Cout
vs
vo
+
+
-
-
VCC
Q1
vin
+
-
CE
Fig. 208. Standard common emitter amplifier circuit.
The Common-Emitter Amplifier
Introduction
The typical four-resistor bias circuit is shown in black. . .capacitors
are open circuits at dc, so only signal currents can flow in the blue
branches.
Capacitors are chosen to appear as short circuits at frequencies
contained in the signal (called midband frequencies).
Cin and Cout couple the signal into, and out of, the amplifier. CE
provides a short circuit around RE for signal currents only (dc
currents cannot flow through CE .
A standard dc analysis of the four-resistor bias circuit provides the
Q-point, and from that we obtain the value of rπ .

RS
R1
R2
RC
RE
RL
Cin
Cout
vs
vo
+
+
-
-
VCC
Q1
vin
+
-
CE
Fig. 209. Standard common emitter. (Fig. 208 repeated)
vs
RS
R2 R1 rπ RLRCβib
vo
+
+
- -
B
E
Cib
vin
+
-
Fig. 210. Small signal equivalent circuit of common emitter amplifier.
Constructing the Small-Signal Equivalent Circuit
To construct small-signal equivalent circuit for entire amplifier, we:
1. Replace the BJT by its small-signal model.
2. Replace all capacitors with short circuits.
3. Set all dc sources to zero, because they have zero signal
component!!!
The result is the small-signal equivalent circuit of the amplifier:

vs
RS
RB rπ RL’βib
vo
+
+
- -
B
E
Cib
vin
+
-
Fig. 211. Simplified small signal equivalent of common emitter amplifier.
v i Ro b L= −
′
β (206)
v v i rin be b= = π (205)
A
v
v
i R
i r
R
r
v
o
in
b L
b
L
= =
−
′
=
−
′
β β
π π
(207)
A
v
v
R
r
vo
o
in
C
= =
−β
π
(208)
For convenience we let R1 || R2 = RB , and RC || RL = RL’:
Voltage Gain
Our usual focus is Av = vo /vin , or Avs = vo /vs . We concentrate on the
former. Because ib is the only parameter common to both sides of
the circuit, we can design an approach:
1. We write an equation on the input side to relate vin to ib .
2. We write an equation on output side to relate vo to ib .
3. We combine equations to eliminate ib .
Thus:
And:
With RL removed (an open-circuit load), we define the open-circuit
voltage gain, Avo :

vs
RS
RB rπ RLβib
vo
+
+
- -
B
E
Cib
vin
+
-
iin
Rin
Fig. 212. Input resistance of common emitter amplifier.
RS
RB rπ RCβib
B
E
Cib
Ro
Fig. 213. Output resistance of common emitter amplifier.
R R rin B= || π (209)
R Ro C= (210)
Input Resistance
By definition, Rin = vin /iin . We can find this simply by inspection:
Output Resistance
Recall that to find Ro , we must remove the load, and set all
independent sources to zero, but only independent sources. We do
not set dependent sources to zero!!!
Thus:
Now, because ib = 0, the dependent source βib = 0 also,and:

Introduction to Electronics 149The Emitter Follower (Common Collector Amplifier)
RS
R1
R2 RE
RL
Cin
Cout
vs
vo
+
+
-
-
VCC
Q1
vin
+
-
Fig. 214. Standard emitter follower circuit.
vs
RS
R2 R1 rπ
RLRE
βib
vo
+
+
-
-
B
E
Cib
vin
+
-
(β+1)ibR1 || R2 = RB
RE || RL = RL’
Fig. 215. Emitter follower small-signal equivalent circuit. The
collector terminal is grounded, or common, hence the alternate name
Common Collector Amplifier.
The Emitter Follower (Common Collector Amplifier)
Introduction
We have a four-resistor bias network, with RC = 0.
Unlike the common-emitter amplifier, vo is taken from the emitter.
The small-signal equivalent is derived as before:

vs
RS
R2 R1 rπ
RLRE
βib
vo
+
+
-
-
B
E
Cib
vin
+
-
(β+1)ibR1 || R2 = RB
RE || RL = RL’
Fig. 216. Emitter follower small-signal equivalent (Fig. 215 repeated).
( )v i r i Rin b b L= + +
′
π β 1 (211)
( )v i Ro b L= +
′
β 1 (212)
( )
( )
A
v
v
R
r R
v
o
in
L
L
= =
+
′
+ +
′
β
βπ
1
1
(213)
Voltage Gain
Gain, Av = vo /vin , is found using the same approach described for
the common-emitter amplifier. We write two equations of ib - one on
the input side, one on the output side - and solve:
Typical values for Av range from 0.8 to unity. The emitter (output)
voltage follows the input voltage, hence the name emitter follower.
The feature of the follower is not voltage gain, but power gain, high
input resistance and low output resistance, as we see next . . .

vs
RS
R2 R1 rπ
RLRE
βib
vo
+
+
-
-
B
E
Cib
vin
+
-
(β+1)ibR1 || R2 = RB
RE || RL = RL
Rin Rit
Fig. 217. Calculating the input resistance of the emitter follower.
R
v
i
R R R
v
i
in
in
in
B it it
in
b
= = =|| , where (214)
( )R r Rit L= + +
′
π β 1 (215)
( )[ ]R R r Rin B L= + + ′|| π β 1 (216)
Input Resistance
Note that :
We’ve already written the equation we need to find Rit. It’s equation
(211), from which:
Thus
Compare this to the common emitter input resistance, which is
generally much lower, at .R R rin B= || π

RS R2 R1
rπ
RE
βib
vtest
+
-
B
E
C
iy
(β+1)ibR1||R2||RS = RS’ itest
ib
RoRot
Fig. 218. Circuit for calculating follower output resistance.
( )
R
v
i
R R R
v
i
v
i
o
test
test
E ot ot
test
y
test
b
= = = =
− +
|| , where
β 1
(217)
( )v i R r R
R r
test b S ot
S
= − ′ + ∴ =
′ +
+π
π
β 1
(218)
Output Resistance
Notice that we have set the independent source to zero, and
replaced RL by a test source. From the definition of output
resistance:
But
Compare this to the common emitter input resistance, which is
much higher, at RC .

Introduction to Electronics 153Review of Small-Signal Analysis
Review of Small Signal Analysis
It’s presumed that a dc analysis has been completed, and rπ is
known.
1. Draw the small-signal equivalent circuit.
A. Begin with the transistor small signal model.
B. For midband analysis, coupling and bypass
capacitors replaced by short circuits.
C. Set independent dc sources to zero.
2. Identify variables of interest.
3. Write appropriate independent circuit equations.
(This usually requires an equation on the “input” side and an
equation on the “output” side of the small-signal equivalent
circuit.)
4. Solve.
5. Check units!!!

Introduction to Electronics 154FET Small-Signal Equivalent Circuit
VDC
vs
+
iD
iS
Fig. 219. Generalized FET circuit.
iD
vGS
VP
IDSS
IDQ
VGSQ
Q
Fig. 220. FET transfer characteristic.
v V v i I iGS GSQ gs D DQ d= + = +and (219)
id
is
vgs
+
-
G D
S
gm vgs
Fig. 221. FET sm. sig. model.
i g vd m gs= (220)
FET Small-Signal Equivalent Circuit
The Small-Signal Equivalent
We restrict operation to the pinch-off region and note that the dc
source and the circuit determine the Q-point.
For small vs, the instantaneous operating pt. stays very near Q, and
the transfer curve can be approximated with a line tangent at Q.
Both vGS and iD have dc and ac components:
VGSQ and IDQ are related by the second-
order FET characteristic, but if |vs| is
small enough, vgs and id are related
(almost) linearly:
gm , is called the transconductance.
This leads immediately to the model at
left.

iD
vGS
VP
IDSS
IDQ
VGSQ
Q
Fig. 222.FET transfer characteristic.
g
i
v
m
D
GS Q
=
∂
∂
(221)
2
(222)
( )[ ] ( )g
v
K v V K V Vm
GS
GS P
Q
GSQ P= − = −
∂
∂
2
2 (223)
V V
I
K
GSQ P
DQ
− = (224)
g KIm DQ= 2 (225)
g
I I
V
m
DSS DQ
P
= 2 (226)
Transconductance
The coefficient gm is the slope
of the tangent :
From the pinch-off region
equation:
We obtain:
But also from eq. (222) we have
Substituting this into eq. (223), we see that the transconductance
can also be written as:
Or, finally, because K = IDSS /VP
2
we can write:

Fig. 223. FET output characteristics.
i
i
v
v
i
v
v g v
v
r
d
D
GS Q
gs
D
DS Q
ds m gs
ds
d
=








+








= +
∂
∂
∂
∂
(227)
id
is
vgs
+
-
G D
S
gm vgs rd
Fig. 224. FET small-signal model including
FET output resistance.
∂
∂
i
v r
QD
DS Q d
= =
1
slope of output char. at (228)
FET Output Resistance
Recall that FET output
characteristics have upward
slope. This means that id is
not dependent only on vgs ,
but also on vds.
We can account for both
dependencies by writing:
where
A single addition to the small-signal model accounts for rd :
Output resistance is more
noticeable in FETs than in
BJTs.
But it is also observed in BJTs
and can be included in the
BJT small-signal model,
where the notation ro is used
for output resistance.

Introduction to Electronics 157The Common-Source Amplifier
Rsig
RG
RD
RS
RL
Cin
Cout
vsig
vo
+
+
-
-
VDD
vin
+
-
CS
Fig. 225. Standard common source amplifier circuit.
vsig
Rsig
rd
RG RLRDgmvgs
vo
+
+
- -
G
S
D
vin
+
-
iin
vgs
+
-
rd ||RD ||RL = RL’
Fig. 226. Small-signal equivalent circuit for the common source amplifier.
The Common Source Amplifier
The Small-Signal Equivalent Circuit
The self-bias circuit is shown in black.
Capacitors are open circuits at dc, so only signal currents flow in the
blue branches.
A standard dc analysis provides the value of gm .
The small-signal equivalent is constructed in the standard manner:

Introduction to Electronics 158The Common-Source Amplifier
vsig
Rsig
rd
RG RLRDgmvgs
vo
+
+
- -
G
S
D
vin
+
-
iin
vgs
+
-
rd ||RD ||RL = RL’
Fig. 227. Common source small signal equivalent (Fig. 226 repeated).
v v v g v Rin gs o m gs L= = −
′
and (229)
A
v
v
g Rv
o
in
m L= = −
′
(230)
R
v
i
Rin
in
in
G= = (231)
R r Ro d D= || (232)
Voltage Gain
Thus:
Input Resistance
Because no dc current flows through RG it can be extremely large.
Output Resistance
Remember, we must remove RL , and set all independent sources
to zero. For this circuit we can determine Ro by inspection:

Introduction to Electronics 159The Source Follower
Rsig
RG
RS
RL
Cin
Cout
vsig
vo
+
+
-
-
VDD
vin
+
-
Fig. 228. Source follower circuit.
vsig
Rsig
rd
RG
RLRS
gmvgs
vo
+
+
-
-
G
S
D
vin
+
-
iin
vgs
+
-
rd ||RS ||RL = RL’
Fig. 229. Source follower small-signal equivalent circuit.
The Source Follower
Small-Signal Equivalent Circuit
This follower uses fixed bias: IG = 0 VGSQ = 0 ID = IDSS⇒ ⇒
Tremendously large Rin is obtained by sacrificing bias stability,
which isn’t very important in this circuit anyway, as we shall see.
The small-signal equivalent is constructed in the usual manner:

vsig
Rsig
rd
RG
RLRS
gmvgs
vo
+
+
-
-
G
S
D
vin
+
-
iin
vgs
+
-
Fig. 230. Source follower small-signal equivalent circuit (Fig. 229
repeated).
v v v v v vin gs o gs in o= + ⇒ = − (233)
( )v g v i R g v
v
R
R v g
R
Ro m gs in L m gs
gs
G
L gs m
G
L= + ′ = +






′ = +






′1
(234)
( )v v v g
R
Ro in o m
G
L= − +






′1
(235)
1
1 1
+ +






′




 = +






′g
R
R v v g
R
Rm
G
L o in m
G
L
(236)
A
v
v
g
R
R
g
R
R
v
o
in
m
G
L
m
G
L
= =
+






′
+ +






′
=
1
1
1
0 5. to 0.8 typically (237)
Voltage Gain
This one requires a little more algebra. Beginning with:
and
We replace vgs in eq. (234) with eq. (233), and solve for vo /vin :

vsig
Rsig
rd
RG
RLRS
gmvgs
vo
+
+
-
-
G
S
D
vin
+
-
iin
vgs
+
-
Fig. 231. Source follower small-signal equivalent circuit (Fig. 229
repeated).
v v v v v g
R
Rin gs o gs gs m
G
L= + = + +






′1
(238)
v i R i R g
R
Rin in G in G m
G
L= + +






′1
(239)
( )R
v
i
R g R Rin
in
in
G m G L= = + +
′
1 (240)
Input Resistance
Replacing vo in eq. (233) with eq. (234):
But vgs = iin RG :
Solving for vin /iin :
Because IG = 0, RG can be several MΩ. With the additional
multiplying factor of RL’, Rin can become extremely large!!!

vtest
Rsig
rd
RG
RS
gmvgs
+
-
G
S
D
itest
vgs
+
-
Fig. 232. Determining output resistance of the source follower.
i
v
R
v
r
v
R R
g vtest
test
S
test
d
test
G sig
m gs= + +
+
− (241)
v
R
R R
vgs
G
G sig
test= −
+
(242)
i v
R r R R
g R
R R
test test
S d G sig
m G
G sig
= + +
+
+
+






1 1 1
(243)
Output Resistance
This calculation is a little more involved, so we shall be more formal
in our approach.
We remove RL , apply a test source, vtest , and set the independent
source to zero.
From a KCL equation at the source node:
But RG and Rsig form a voltage divider:
Substituting eq. (242) into eq. (241):

vtest
Rsig
rd
RG
RS
gmvgs
+
-
G
S
D
itest
vgs
+
-
Fig. 233. Determining output resistance of the source follower (Fig.
232 repeated).
R
v
i
R r R R
g R
R R
o
test
test
S d G sig
m G
G sig
= =
+ +
+
+
+
1
1 1 1 (244)
( )R R r R R
R R
g R
o S d G sig
G sig
m G
= +
+




|| || || (245)
Thus:
Finally, we recognize this form as that of resistances in parallel:

Introduction to Electronics 164Review of Bode Plots
A f
j
f
f
j
f
f
j
f
f
v
Z Z
P
( ) =





 +






+






1 2
1
1
1
(246)
Review of Bode Plots
Introduction
The emphasis here is review. Please refer to an appropriate text if
you need a more detailed treatment of this subject.
Let us begin with a generalized transfer function:
We presume the function is limited to certain features:
G Numerator and denominator can be factored.
G Numerator factors have only one of the two forms shown.
G Denominator factors have only the form shown.
Remember:
G Bode plots are not the actual curves, but only asymptotes to
the actual curves.
G Bode magnitude plots are not based on the transfer function
itself, but on the logarithm of the transfer function - actually, on
20 log Av .
G The total Bode response for Av(f) consists of the magnitude
response and the phase response. Both of these consist of
the sum of the responses to each numerator and denominator
factor.

0 dB
fz1
20 dB/decade
Fig. 234. Bode magnitude
response for jf/fZ1 .
0 dB
fz2
20 dB/decade
response for 1 + jf/fZ2 .
The Bode Magnitude Response
Now, let’s review the Bode magnitude response of each term:
The numerator term :j
f
fZ1
The magnitude response increases 20
dB per decade for all f.
For f = fZ1 the term has a magnitude of 1.
Thus the magnitude response has an
amplitude of 0 dB at fZ1 .
The numerator term :1
2
+ j
f
fZ
For f << fZ2 the imaginary term is
negligible; the magnitude is just 0 dB.
For f >> fZ2 the imaginary term
dominates, thus the magnitude increases
20 db per decade.
The denominator term :1
1
+ j
f
fP
For f << fP1 the imaginary term is
negligible; the magnitude is just 0 dB.
For f >> fP1 the imaginary term
dominates, thus the magnitude
decreases 20 db per decade (because
the term is in the denominator).
0 dB
fp
-20 dB/decade
response for 1 + jf/fP1 .

+90O
Fig. 237. Bode phase response
for jf/fZ1 .
0O
fz2 /10
10fz2
+90O
45O
/decade
for 1 + jf/fZ2 .
The Bode Phase Response
Now, let’s review the Bode phases response of each term:
The numerator term :j
f
fZ1
The phase response is simply 90o
for all
f.
The numerator term :1
2
+ j
f
fZ
negligible; the phase is just 0o
.
dominates, thus the phase is 90o
.
At f = fZ2 , the term is 1 + j1; its phase is
45O
.
The denominator term :1
1
+ j
f
fP
negligible; the phase is just 0o
.
dominates, thus the phase is -90o
.
At f = fZ2 , the term is 1 + j1; its phase is
-45O
.
0O
fp /10
10fp
-45O
/decade
-90O
for 1 + jf/fP1 .

Vo(s)
R
+
1/sCVin(s)
+
-
Fig. 240. Single-pole low-pass RC circuit,
A
V
V
sC
R
sC
sRC
v
o
in
= =
+
=
+
1
1
1
1
(247)
( )
A
j RC f j
f
f
f
RC
v
b
b=
+
=
+
=
1
1 2
1
1
1
2π π
where
(248)
A
f
f
v
b
=
+






1
12
2
(249)
Single-Pole Low-Pass RC
The review of the details of the
Bode response of a single-pole
low-pass RC circuit begins with
the s-domain transfer function:
Note that there is a pole at s = -1/RC and zero at s = .∞
For the sinusoidal steady state response we substitute j2πf for s:
This fits the generalized single-pole form from the previous page,
except we’re using “fb” instead of “fP.” The term fb is called the half-
power frequency, the corner frequency, the break frequency, or the
3-dB frequency.
Gain Magnitude in dB:
From:

( )A
f
f
f
f
f
f
f
f
v dB
b
b
b b
=
+






= − +






= − +





 = − +














20
1
1
20 1 20 1
20 1 10 1
2
2
2
2
2
2 2
log log log
log log
(250)
( )Av dB
= − =10 1 0log dB (251)
A
f
f
f
f
v dB
b b
= −





 = −





10 20
2
log log (252)
fb /10 fb 10fb 100fb
-3 dB
-40 dB
-20 dB
Av , dB
f
Fig. 241. Bode magnitude plot for single-pole low-
pass, in red. The actual curve is shown in blue.
We obtain:
Bode Magnitude Plot:
From eq. (250), at low frequencies (f /fb << 1):
And, at high frequencies (f /fb >> 1):
Note that the latter
equation decreases 20
dB for each factor of 10
increase in frequency
(i.e., -20 db per decade).

f/fb
1
θθθθ Re
Im
Fig. 242. Trigonometric representation
of transfer function phase angle.
A
j
f
f
v
b
=
+
1
1
(253)
θA
b
v
f
f
= −arctan (254)
θ, deg
f0O
-45O
-90O
Fig. 243. Bode phase plot for single-pole low-pass,
shown in red. The actual curve is shown in blue.
Bode Phase Plot:
From the transfer function:
The transfer function phase angle
is:
The Bode phase plot shows the characteristic shape of this inverse
tangent function:

Vo(s)R
+
1/sC
Vin(s)
+
-
Fig. 244. Single-pole high-pass RC
circuit.
A
R
sC
R
sRC
sRC
v =
+
=
+1 1 (255)
( )
( )
A
j RC f
j RC f
j
f
f
j
f
f
f
RC
v
b
b
b=
+
=
+
=
2
1 2 1
1
2
π
π π
where (256)
A
f
f
f
f
v dB
b b
=





 − +





20 20 1
2
log log (257)
Single-Pole High-Pass RC
The s-domain transfer function:
Note there is a pole at s = -1/RC,
and a zero at s = 0.
For the sinusoidal steady state response we substitute j2πf for s:
Bode Magnitude Plot:
Because this is a review, we go directly to the resulting gain
equation:
Recall from Fig. (234) that the first term is a straight line, with +20
dB/dec slope, passing through 0 dB at fb .
The last term is the same term from the low pass example, which
has the form of Fig. (236).
The total Bode magnitude response is merely the sum of these two
responses.

-3 dB
-40 dB
-20 dB
Av , dB
f
Fig. 245. Bode magnitude plot for single-pole high
pass, in red. The actual curve is shown in blue.
θ, deg
f
90O
45O
0O
Fig. 246. Bode phase plot for single-pole high-pass,
in red. The actual curve is shown in blue.
θA
b
v
f
f
= °−90 arctan (258)
Adding the two individual responses gives:
Bode Phase Plot:
The transfer function leads to the following phase equation:
This is just the low-pass phase plot shifted upward by 90o
:

Introduction to Electronics 172Coupling Capacitors
RS
RB RC
RL
Cin
Cout
vs
vo
+
+
-
-
VCC
Q1
vin
+
-
Fig. 247. Representative amplifier circuit, split into sections.
RB r RCβib
ib
Fig. 248. Amplifier sm. sig. eq. ckt.
Rin
Ro
+
-
+
-
vx Avo vx
Fig. 249. Model equivalent to
amplifier section.
Coupling Capacitors
Effect on Frequency Response
In our midband amplifier analysis, we assumed the capacitors were
short circuits, drew the small-signal equivalent, and analyzed it for
overall gain (or other parameters). This time, though:
(1) we can draw the sm. sig. eq.
ckt. of the amplifier section only,
(2) analyze it, determine the its
model parameters, and . . .

Rin
Ro
+
-
+
-
vx Avo vx
RL
Cout
vo
+
-
RS
Cin
vs
+
-
Fig. 250. Complete circuit redrawn with amplifier section replaced by its model.
( )
f
C R Rin S in
1
1
2
=
+π
(259)
( )
f
C R Rout o L
2
1
2
=
+π
(260)
. . . (3) redraw the entire circuit (Fig. 247) as shown:
Note that both sides are identical topologically, and are single-pole,
high-pass circuits:
On the left: On the right:
At frequencies above f1 and f2 , the Bode magnitude plots from
these high-pass circuits are simply horizontal lines at 0 dB, which
add to become a single horizontal line at 0 dB. Of course, the
amplifier (and resistive dividers) will shift this horizontal line
(hopefully upward, because we probably want Av > 1). .
Suppose we begin somewhere above f1 and f2 - at midband . . . we
already know how to find the midband gain, which will become
on the Bode magnitude plot.20logAvmid
Now let’s work our way lower in frequency. . . when we get to the
first of the two pole frequencies, our Bode magnitude plot begins to
drop at 20 dB/decade. . . when we get to the second pole, the plot
drops at 40 dB/decade. . . see the illustration on the next page.

20 log Av mid
f1
f2
20 dB/dec
40 dB/dec
Fig. 251. Generalized Bode magnitude plot of an amplifier with
coupling capacitors. Here f1 is assumed to be lower than f2 .
Note that the presence of f1 moves the overall half-power frequency
above f2 .
Constructing the Bode Magnitude Plot for an Amplifier
1. Analyze the circuit with the coupling capacitors replaced by
short circuits to find the midband gain.
2. Find the break frequency due to each coupling capacitor.
3. Sketch the Bode magnitude plot by beginning in the midband
range and moving toward lower frequencies.

Introduction to Electronics 175Design Considerations for RC-Coupled Amplifiers
Design Considerations for RC-Coupled Amplifiers
1. RC-Coupled amplifiers:
Coupling capacitors - capacitors cost $
Direct-Coupled amplifiers:
No capacitors - bias circuits interact - more difficult design, but
preferable.
2. Determine Thevenin resistance “seen” by each coupling
capacitor.
Larger resistances mean smaller and cheaper capacitors.
3. Choose fb for each RC circuit to meet overall -3 dB
requirement.
Judicious choice can reduce overall cost of capacitors.
4. Calculate required capacitance values.
5. Choose C values somewhat larger than calculated
(approximately 1.5 times larger).
Some C tolerances are as much as -20%, +80 %. Vales can
change with time and temperature.±10 %

Introduction to Electronics 176Low- & Mid-Frequency Performance of CE Amplifiers
RS
R1
R2
RC
REB
RL
Cin
Cout
vs
vo
+
+
-
-
VCC
Q1
vin
+
- CE
REF
Fig. 252. Generic single-supply common emitter ckt.
(Let RB = R1 || R2 , RL’ = RL || RC , RE = REF + REB )
RS
RB
RC
REB
RL
Cin
Cout
vs
vo
+
+
-
-
VCC
Q1
vin
+
- CE
REF
-VEE
Fig. 253. Generic dual-supply common emitter ckt.
(Let RL’ = RL || RC , RE = REF + REB )
Low- & Mid-Frequency Performance of CE Amplifier
Introduction
We begin with two of the most common topologies of common-
emitter amplifier:

vs
RS
RB r
RL’
βib
vo
+
+
- -
B
E
Cib
vin
+
-
iin io
REF
RC RL
Rin
Fig. 254. Generic small-signal equivalent of common emitter amplifier.
( )
A
v
v
R
r R
R
Rv
o
in
L
EF
L
EF
= =
− ′
+ +
≈
− ′
>>
β
β
β
π 1
1, if (261)
A
v
v
A
R
R R
v
o
s
v
in
S in
s
= =
+
(262)
( )[ ]R
v
i
R r Rin
in
in
B EF= = + +|| π β 1 (263)
A
i
i
A
R
R
R
R R
R
R R
i
o
in
v
R
v
R
v
in
L
C
C L
B
B X
o
L
in
in
= = = = −
+ +
β (264)
Both common-emitter topologies have the same small-signal
equivalent circuit:
Midband Performance
For the equivalent circuit shown, Ro = RC , but if we include the BJT
output resistance ro in the equivalent circuit, the calculation of Ro
becomes much more involved. We’ll leave this topic with the
assumption that Ro RC .≈
The focus has been Av , but we can determine Ai also:
where RX = rπ + (β + 1)REF .

Design Considerations
G In choosing a device we should consider:
Frequency performance
Noise figure
Power Dissipation
Device choice may not be critical. . .
G Design Tradeoffs:
1. RB large for high Rin and high Ai
RB small for bias (Q-pt.) stability
2. RC large for high Av and Ai
RC small for low Ro , low signal swing, high frequency
response
3. REF small (or zero) for maximum Av and Ai
REF > 0 for larger Rin , gain stability, improved high and
low frequency response, reduced distortion
G Gain Stability:
Note from eq. (261), as REF increases, Av -RL’/REF , i.e., gain≈
becomes independent of β !!!

vs
RS
RB rπ RLβib
vo
+
+
- -
B
E
Cib
vin
+
-
iin io
REF
CoutCin
RC
Fig. 255.Approximate sm. sig. equivalent of the CE amplifier at low
frequencies. The effect of CE is ignored by replacing it with a short circuit.
Cin and Cout remain so that their effect can be determined.
f
R C
b
Thevenin
=
1
2π
(265)
( )
f
R R C
out
C L out
=
+
1
2π
(266)
for A
v
v
f
R C
v
o
in
in
in in
= =
1
2π
(267)
( )
for A
v
v
f
R R C
v
o
s
in
S in in
= =
+
1
2π
(268)
The Effect of the Coupling Capacitors
To determine the effect of the coupling capacitors, we approximate
the small-signal equivalent as shown. Cin and Cout are then a part
of independent single-pole high-pass circuits, with break
frequencies of:
Thus the effect of Cout is:
And the effect of Cin is:
Equations for fin are approximate, because the effects of Cin and CE
interact slightly. The interaction is almost always negligible.

vs
RS
RB rπ RL’βib
vo
+
+
- -
B
E
Cib
vin
+
-
io
REF
CEREB
Fig. 256. Approximate common emitter sm. sig. equivalent at low frequencies.
Only the effect of CE is accounted for in this circuit.
Av , dB
f1
CE = short ckt.
CE = open ckt.
f
f2
Fig. 257. Bode magnitude plot showing the effect
of CE only.
The Effect of the Emitter Bypass Capacitor CE
Consider the following:
At sufficiently high frequencies, CE appears as a short circuit. Thus
the total emitter resistance is at its lowest, and Av is at its highest.
This appears like, and is, the standard single-pole high-pass effect.
At sufficiently low frequencies CE appears as an open circuit. The
total emitter resistance is at its highest, and Av is at its lowest, but
Av is not zero!!! Thus, there is not just a single-pole high-pass
effect. There must also be a zero at a frequency other than f = 0,
as shown below:

RB rπ RL’βib
vo
+
-
B
E
Cib
vin
+
-
iin io
REF
REB Rthevenin
RX
RY
Fig. 258. Finding Thevenin R “seen” by CE , assuming we are interested
in vo /vin , i.e., assuming RS = 0.
ic
itest
ib
r βibvbe
+
-
vtest
+
Fig. 259. Finding RY .
( )R R R R R RThevenin EB X EB EF Y= = +|| || (269)
i
v
r
v
r
b
be test
= = −
π π
(270)
( )i itest b= − +β 1 (271)
R
v
i
r
Y
test
test
= =
+
π
β 1
(272)
( )R
R R r
Y
B S
=
+
+
|| π
β 1
(273)
To find the pole frequency f1 we need the Thevenin resistance
“seen” by CE :
From inspection we should see that:
The difficulty is finding RY , which is undertaken below:
If RS 0, then RY becomes:≠

f
C R R
r
E EB EF
1
1
2
1
=
+
+











π
β
π
||
(274)
20 log Av mid
fout
20 dB/dec
f2
f1
fin
40 dB/dec
40 dB/dec
60 dB/dec
Fig. 260. One example of the
Bode plot of a CE amplifier.
f
C R R
r R R
E EB EF
B S
1
1
2
1
=
+
+
+











π
β
π
||
( || (275)
f
C RE EB
2
1
2
=
π
(276)
Thus, for Av = vo /vin :
Or, for Av = vo /vs :
The zero f2 is the frequency where :Z jf R
jf C
E E
E
( ) ||2
2
1
= = ∞
The mathematical derivation of eq. (276) is not a focus of this
course; it is left for your own endeavor.
The Bode magnitude plot of a common
emitter amplifier is the summation of the
effects of poles fin , fout , f1 , and the zero f2 .
One of many possible examples is shown
at left.

Introduction to Electronics 183The Miller Effect
Z
Vin Vout = AvVin
++
--
Iz
“Black Box”
Fig. 261. Circuit with feedback impedance Z. The
black box is usually an amplifier, but can be any
network with a common node.
Vin Vout = AvVin
++
--
Iz
“Black Box”
Zin, Miller Zout, Miller
Fig. 262. Circuit to be made equivalent to the previous
figure.
The Miller Effect
Introduction
Before we can examine the high frequency response of amplifiers,
we need some additional tools. The Miller Effect is one of them.
Consider:
It is difficult to analyze a circuit with a feedback impedance, so we
wish to find a circuit that is equivalent at the input & output ports:
If we can choose Zin. Miller so that Iz is the same in both circuits, the
input port won’t “know” the difference - the circuits will be equivalent
at the input port.

Introduction to Electronics 184The Miller Effect
( )I
V V
Z
V A V
Z
V A
Z
Z
in o in v in in v
=
−
=
−
=
−1
(277)
I
V
Z
Z
in
in Miller
=
,
(278)
Z
Z
A
in Miller
v
, =
−1
(279)
Z Z
A
A
Z
A
out Miller
v
v
v
, =
−
=
−1
1
1
1 (280)
Deriving the Equations
From Fig. 261:
And from Fig. 262:
Setting eqs. (277) and (278) equal, and solving:
Using a similar approach, the circuits can be made equivalent at the
output ports, also, if:
Notes:
1. Though not explicitly shown in the derivation, Av and all
the impedances can be complex (i.e., phasors).
2. If |Av | is, say, 10 or larger, then Zout, Miller Z.≈
3. If Av > 1 and real, then Zin, Miller is negative!!! This latter
phenomenon is used, among other things, to construct
oscillators.

Introduction to Electronics 185The Hybrid-π BJT Model
rπ
+
-
vπ gmvπ ro
Cµ
Cπ
rµrxB C
EE
B’
Fig. 263. Hybrid-π model of BJT.
The Hybrid-ππππ BJT Model
The Model
This is another tool we need before we examine the high frequency
response of amplifiers.
The hybrid-π BJT model includes elements that are negligible at low
frequencies and midband, but cannot be ignored at higher
frequencies of operation:
rx = ohmic resistance of base region, a few tens of ohms≈
rπ = dynamic resistance of base region, as described previously
ro = collector resistance of BJT, as described previously
rµ , Cµ represent the characteristics of the reverse-biased collector-
base junction:
rµ several Megohms Cµ 1 pF to 10 pF≈ ≈
Cπ = diffusion capacitance of b-e junction, 100 pF to 1000 pF≈
gm = BJT transconductance; we can show that gm = β/rπ = ICQ /VT

rπ
+
-
vπ gmvπ ro
Cµ
Cπ
rµrxB C
EE
B’
Fig. 264. Hybrid-π model of BJT (Fig. 263 repeated).
rπ
+
-
vπ gmvπ roCπ
B C
EE
B’
C2C1
Fig. 265. Simplified hybrid-π BJT model using the Miller Effect and the other
assumptions described in the text..
Effect of Cπ and Cµ
Notice the small values of Cπ and Cµ , especially when compared to
typical values of Cin , Cout , and CE .
At low and midband frequencies, Cπ and Cµ appear as open circuits.
At high frequencies, where Cπ and Cµ have an effect, Cin , Cout , and
CE appear as short circuits.
To focus our attention, we’ll assume rx 0 and rµ , and we’ll≈ ≈ ∞
use the Miller Effect to replace Cµ :

rπ
+
-
vπ gmvπ roCπ
B C
EE
B’
C2C1
Fig. 266. Miller Effect applied to hybrid-π model (Fig. 265 repeated).
fh1
fh2
Fig. 267. Typical amplifier response in the
midband and high-frequency regions. fh1 is
normally due to C1 + Cπ , and fh2 is normally
due to C2 .
( )C C A A Cv v1 1= − ≈µ µ
(281)
C C
A
C
v
2 1
1
= −





 ≈µ µ (282)
f
C R
b
eq Thevenin
=
1
2π
(283)
From the Miller Effect equations, (279) and (280):
Individually, all Cs in Fig. 266 have a single-pole low-pass effect.
As frequency increases they become short circuits, and vo
approaches zero .
Thus there are two low-pass poles with the mathematical form:
Because C1 + Cπ >> C2 , the pole
due to C1 + Cπ will dominate.
The pole due to C2 is usually
negligible, especially when RL’ is
included in the circuit.

rπ
+
-
vπ gmvπ roCπ
B C
EE
B’
C2C1
Fig. 268. Miller Effect applied to hybrid-π model (Fig. 265 repeated).
( )
f f
C C R
H h
Thevenin
≈ =
+
1
1
1
2π π
(284)
f
C R A C R
H
Thevenin v Thevenin
≈ ≈
1
2
1
21π π µ
(285)
The overall half-power frequency, then, is usually due to C1 + Cπ :
For typical transistors, C1 > Cπ . For a moment, let us be very
approximate and presume that Cπ is negligibly small. Then:
i.e., fH is approximately inversely proportional to |Av | !!!
Amplifiers are sometimes rated by their Gain-Bandwidth Product,
which is approximately constant. This is especially true for high
gains where C1 dominates.

Introduction to Electronics 189High-Frequency Performance of the CE Amplifier
RS
R1
R2
RC
RE
RL
Cin
Cout
vs
vo
+
+
-
-
VCC
Q1
vin
+
-
CE
Fig. 269. Standard common emitter amplifier (Fig.
208 repeated).
rπ
+
-
vπ gmvπ ro
Cµ
Cπ
rµrxB C
EE
B’
vs
RS
+
-
vin
+
-
RB = R1||R2
RL’ = ro||RL||RC
RL||RC
Fig. 270. Amplifier small-signal equivalent circuit using hybrid-π BJT model.
High-Frequency Performance of CE Amplifier
The Small-Signal Equivalent Circuit
We now have the tools we need to analyze (actually, estimate) the
high-frequency performance of an amplifier circuit. We choose the
common-emitter amplifier to illustrate the techniques:
Now we use the hybrid-π equivalent for the BJT and construct the
small-signal equivalent circuit for the amplifier:

+
-
vπ gmvπ
Cµ
Cπ
CB’
vs’
RS’
+
-
RL’
+
-
vo
Fig. 271. Modified small-signal equivalent, using a Thevenin
equivalent on the input side, and assuming rµ is infinite.
+
-
vπ gmvπCπ
CB’
vs’
RS’
+
-
RL’
+
-
voCµ (1+gmRL’)
Fig. 272. Final (approximate) equivalent after applying the Miller Effect.
A
v
v
g Rv
o
m L= ≈ −
′
π
(286)
High-Frequency Performance
We can simplify the circuit further by using a Thevenin equivalent
on the input side, and by assuming the effect of rµ to be negligible:
Note that the Thevenin resistance Rs’ = rπ || [rx + (RB||RS)]
Recognizing that the dominant high-frequency pole occurs on the
input side, we endeavor only to calculate fh1 . Thus we ignore the
effect of Cµ on the output side, calculate the voltage gain, and apply
the Miller Effect on the input side only.

+
-
vπ gmvπCπ
CB’
vs’
RS’
+
-
RL’
+
-
voCµ (1+gmRL’)
Fig. 273. Final (approximate) equivalent after applying the Miller Effect (Fig. 272
repeated).
f
R C
h
S total
1
1
2
=
′
π
(287)
C C C g Rtotal m L= + +
′

 

π µ 1 (288)
( )[ ]R r r R RS x B S
′ = +π || || (289)
So we have
where
and

20 logAv mid
fout
f2
fh1
fin
f1
-20 dB/dec
20 dB/dec
40 dB/dec
40 dB/dec
60 dB/dec
Fig. 274. One example of the entire Bode magnitude response of a common
emitter amplifier.
BW f f f fH L h= − ≈ −1 1 (290)
The CE Amplifier Magnitude Response
Finally, we can estimate the entire Bode magnitude response of an
amplifier. . . an example:
Of this plot, the lower and upper 3-dB frequencies are the most
important, as they determine the bandwidth of the amplifier:
where the latter approximation assumes that adjacent poles are far
away.
We’ve estimated the frequency response of only one amplifier
configuration, the common-emitter. The techniques, though, can be
applied to any amplifier circuit.

Introduction to Electronics 193Nonideal Operational Amplifiers
Av , dB
f, Hz
100
80
60
40
20
0
101 102
103
104
105
106
20 log A0
ft = A0fb
fb
20 dB/decade
Fig. 275. Typical op amp Bode magnitude
response.
A s
A
s
fb
( ) =
+
0
2
1
π
(291)
f A f A ft b of bf= =0 (292)
Nonideal Operational Amplifiers
In addition to operational voltage amplifiers, there are operational
current amplifiers and operational transconductance amplifiers
(OTAs). This discussion is limited to voltage amplifiers.
Linear Imperfections
Input and Output Impedance:
Ideally, Rin = and Rout = 0.∞
Realistically, Rin ranges from 1 MΩ in BJT op amps to 1 TΩ in≈ ≈
FET op amps.
Rout ranges from less than 100 Ω in general purpose op amps, to
several kΩ in low power op amps.
Gain and Bandwidth:
Ideally, Av = and BW = .∞ ∞
Realistically, Av ranges from 80 dB (104
) to 140 dB (107
).
Many internally-compensated op amps have their BW restricted to
prevent oscillation, producing the Bode magnitude plot shown:
The transfer function, then, has a
single-pole, low-pass form:
And gain-bandwidth product is
constant:

t
vo
Expected output
Actual output
Fig. 276. Illustration of op amp slew-rate limiting.
Nonlinear Imperfections
Output Voltage Swing:
BJT op amp outputs can swing to within 2VBE of VSUPPLY .±
FET op amp outputs an swing to within a few mV of VSUPPLY .±
Output Current Limits:
Of course, currents must be limited to a “safe” value. Some op
amps have internal current limit protection.
General purpose op amps have output currents in the range of tens
of mA. For examples, the LM741 has an output current rating of
25 mA, while the LM324 can source 30 mA and sink 20 mA.±
Slew-Rate Limiting:
This is the maximum rate at which vO can change, . It
dv
dt
SRo
≤
is caused by a current source driving the compensation capacitor.
As an example, the LM741 has a SR of 0.5 V/µs.≈

v t V t
dv
dt
SR V fVo OM
o
OM OM( ) sin
max
= ⇒ = = =ω ω π2 (293)
f
SR
V
FP
OM
=
2π
(294)
Full-Power Bandwidth:
This is defined as the highest frequency for which an undistorted
sinusoidal output is obtainable at maximum output voltage:
Solving for f and giving it a special notation:
DC Imperfections:
Many of the concepts in this section are rightly credited to Prof. D.B.
Brumm.
Input Offset Voltage, VIO :
vO is not exactly zero when vI = 0. The input offset voltage VIO is
defined as the value of an externally-applied differential input
voltage such that vO = 0. It has a polarity as well as a magnitude.
Input Currents:
Currents into noninverting and inverting inputs are not exactly zero,
but consist of base bias currents (BJT input stage) or gate leakage
currents (FET input stage):
II
+
, current into noninverting input
II
-
, current into inverting input
These also have a polarity as well as a magnitude.

+
-v-
v+
+-
VIO
ideal
op amp
IB - IIO/2 IB + IIO/2
i=0
i=0
II
-
II
+
vO
Fig. 277. DC error model of operational amplifier.
I
I I
I I IB
I I
IO I I=
+
= −
+ −
+ −
2
and (295)
In general, II
+
II
-
, so we define the input bias current as the≠
average of these, and the input offset current as the difference:
Data sheets give maximum magnitudes of these parameters.
Modeling the DC Imperfections
The definitions of
G input offset voltage, VIO
G input bias current, IB
G and, input offset current, IIO
lead to the following dc error model of the operational amplifier:

+
+
-
-
RN RF
R+
vIN
Fig. 278. Noninverting op amp
configuration.
+
+
-
-
RN RF
R+
vIN
Fig. 279. Inverting op amp
configuration.
+
-
RN
RF
R+
Fig. 280. Identical circuits result when the
sources of Figs. 278 and 279 are set to
zero.
Using the DC Error Model
Recall the standard noninverting and inverting operational amplifier
configurations. Note the presence of the resistor R+
. It is often
equal to zero, especially if dc error does not matter.
Notice that these circuits become identical when we set the
independent sources to zero:

+
-
VOE
RF
R+
+
-VIO
I+
I-
RN
Fig. 282. Op amp noninverting and
inverting amplifiers, external source set to
zero, using dc error model.
+
-v-
v+
+-
VIO
ideal
op amp
IB - IIO/2 IB + IIO/2
i=0
i=0
II
-
II
+
vO
Fig. 281. DC error op amp model (Fig. 277
repeated).
Now, recall the dc error op amp model:
And replace the ideal op amp of Fig. 280 with this model:
With the help of Thevenin equivalents, virtually all op amp circuits
reduce to Fig. 282 when the external sources are set to zero !!!

+
-
VOE
RF
R+
+
-VIO
I+
I-
RN
Fig. 283. Op amp configurations, with external
source set to zero, using dc error model. (Fig.
282 repeated)
v V R IIO
+ + +
= − − (296)
( )V
R
R
V R IOE
F
N
IO, Part A = − +





 + + +
1 (297)
Note that the source VIO can
be “slid” in series anywhere in
the input loop.
Also note carefully the polarity
of VIO .
And, finally, note that the dc
error current sources have
been omitted for clarity.
Currents resulting from these
sources are shown in red.
We can now determine the dc output error for virtually any op amp
configuration. We have already noted the dc output error as VOE .
Using superposition, we’ll first set I-
to zero. The voltage at the
noninverting input is
This voltage is simply the input to a noninverting amplifier, so the dc
output error, from these two error components alone, is:

+
-
VOE
RF
R+
+
-VIO
I+
I-
RN
Fig. 284. Op amp configurations, with external
source set to zero, using dc error model. (Fig.
282 repeated)
V R IOE F, Part B = −
(298)
V
R R
R
R
R R
R I
R
R
R IOE
N F
N
N
N F
F
F
N
, Part B =
+
+
= +






− − −
1 (299)
R
R
R R
R R RN
N F
F F N
−
=
+
= || (300)
( )V
R
R
V R I R IOE
F
N
IO= − +





 + −+ + − −
1 (301)
Next, we consider just I-
, i.e.,
we let VIO = 0 and I+
= 0.
Now v+
= v-
= 0, so there is no
current through RN .
The current I-
must flow
through RF , creating the dc
output error component:
Now we make use of a mathematical “trick.” To permit factoring, we
write (298) as:
where
And, finally, we combine (297) and (299) to obtain the totally
general result:

+
+
-
-vIN
vO
10 kΩ 100 kΩ
Fig. 285. DC output error example.
[ ]IB ∈ 0 100, nA (302)
[ ]IIO ∈ −40 40, nA (303)
[ ]VIO ∈ −2 2, mV (304)
( )V
R
R
V R IOE
F
N
IO= − +





 − − −
1 (305)
DC Output Error Example
The maximum bias current is
100 nA, i.e.,
A positive value for IB means
into the chip.
The maximum offset current magnitude is 40 nA, i.e.,
Note that the polarity of IIO is unknown.
The maximum offset voltage magnitude is 2 mV, i.e.,
Note also that the polarity of VIO is unknown.
Finding Worst-Case DC Output Error:
G Setting vIN to 0, and comparing to Fig. 282 and eq. (301):
where (1 + RF /RN ) = 11, and R-
= 9.09 kΩ.
Note the missing term because R+
= 0.

( )( )VOE = − = −11 2 22mV - 0 mV (306)
( ) ( )( )[ ]VOE = − − = +11 2 120 34mV - 9.09 k nA mVΩ (307)
G The term (VIO - R-
I-
) takes its largest positive value for
VIO = +2 mV and I-
= 0 (we cannot reverse the op amp input
current so the lowest possible value is zero):
Thus, from eq. (305):
G The term (VIO - R-
I-
) takes its largest negative value for
VIO = -2 mV and I-
= 100 nA + 40 nA/2 = 120 nA.
Thus from eq. (305):
G Thus we know VOE will lie between -22 mV and +34 mV.
Without additional knowledge, e.g., measurements on a particular
chip, we can not determine error with any higher accuracy.

( )V
R
R
V R I R IOE
F
N
IO= − +





 + −+ + − −
1 (308)
( ) ( )
V
R
R
V R I
I
R I
I
R
R
V R R I R R
I
OE
F
N
IO B
IO
B
IO
F
N
IO B
IO
= − +





 + +





 − −












= − +





 + − + +




+ −
+ − + −
1
2 2
1
2
(309)
R R R RF N
+ −
= = || (310)
Canceling the Effect of the Bias Currents:
Consider the complete dc error equation (301), repeated below:
If we knew the exact values of I+
and I-
we could choose the
resistances R+
and R-
so that these terms canceled. However, we
can’t know these values in general.
We do however know the value of input bias current, IB .
Rewriting (308) to show the effect of the bias currents:
Thus, we can eliminate the effect of IB if we select
This makes the average error due to currents be zero.

Introduction to Electronics 204Instrumentation Amplifier
R2
R3
R1
R4
v2
v1
vO
+
-
vID
+
-
Fig. 286. Difference amplifier.
( )v
R
R
v vO = −2
1
1 2 (311)
R
R
R
R
v2
v1
vO
+
-
R2
R2
R1
R1
+
+
-
-
+
-
vID
+
-
vY
+
-
vID
Fig. 287. Instrumentation amplifier.
Instrumentation Amplifier
Introduction
Recall the basic op amp
difference amplifier:
only if:
R
R
R
R
4
3
2
1
=
To obtain high CMRR, R4 /R3 and R2 /R1 must be very closely
matched. But this is impossible, in general, as we usually don’t
know the internal resistances of v1 and v2 with certainty or
predictability.
The solution is an instrumentation-quality differential amplifier!!!

Introduction to Electronics 205Instrumentation Amplifier
R
R
R
R
v2
v1
vO
+
-
R2
R2
R1
R1
+
+
-
-
+
-
vID
+
-
+
-
vID
Fig. 288. Instrumentation amplifier (Fig. 287
repeated).
i
v
R
R
ID
1
2 1
= (312)
( )v v
R
R
v vO Y= = +





 −1 2
1
1 2 (313)
Simplified Analysis
The input op amps present infinite input impedance to the
sources, thus the internal resistances of v1 and v2 are now
negligible.
Because the op amps are ideal vID appears across the series
R1 resistances. Current through these resistances is:
This current also flows through R2 . The voltage vY is the sum
of voltages across the R1 and R2 resistances, and the 2nd
stage
is a difference amplifier with unity gain. Thus:
Instrumentation amplifiers are available in integrated form,
both with and without the R1 resistances built-in.

Introduction to Electronics 206Noise
p kTBn = 4 (314)
e kTRBr = 4 (315)
4 0127kTR R= .
nV
Hz
(316)
Noise
We can define “noise” in two different ways:
1. Any undesired component in the signal (e.g., radio-frequency
interference, crosstalk, etc.)
2. Random inherent mechanisms.
Johnson Noise
This is noise generated across a resistor’s terminals due to random
thermal motion of electrons.
Johnson noise is white noise, meaning it has a flat frequency
spectrum - the same noise power in each Hz of bandwidth:
where, k = Boltzmann’s constant = 1.38 x 10-23
J/K,
T = resistor temperature in kelvins
B = measurement bandwidth in Hz.
The open-circuit rms noise voltage across a resistor R is:
From eq. (315), at Troom = 293 K:
This means that, if we have a perfect, noiseless BPF with
BW = 10 kHz, and Vin is the noise voltage of a 10 kΩ resistance at
Troom , we would measure an output voltage VOUT of 1.27 µV with an
ideal (noiseless) true-rms voltmeter.

I qI Br DC= 2 (317)
Johnson noise is random. The instantaneous amplitude is
unpredictable and must be described probabilistically.
It follows a Gaussian distribution with a mean value of zero. This
amplitude distribution has a flat spectrum with very “sharp”
fluctuations.
Johnson Noise Model:
A voltage source er in series with a resistance R.
The significance of Johnson noise is that it sets a lower bound on
the noise voltage present in any amplifier, signal source, etc.
Shot Noise
Shot noise arises because electric current flows in discrete charges,
which results in statistical fluctuations in the current.
The rms fluctuation is a dc current IDC is given by:
where, q = electron charge = 1.60 x 10-19
C
B = measurement bandwidth in Hz.

Shot Noise, 10 kHz measurement bandwidth, from eq. (317)
IDC Ir % fluctuation
1 A 57 nA 0.0000057%
1 µA 57 pA 0.0057% (-85 dB)
1 pA 57 fA 5.6%
Eq. (317) assumes that the charge carriers act independently.
This is true for charge carriers crossing a barrier (e.g., a junction
diode).
This is false for current in metallic conductor (e.g. a simple resistive
circuit). For this latter case, actual noise is less than that given in
eq. (317), i.e., the model gives a pessimistic estimate for design
purposes.
1/f Noise (Flicker Noise)
This is additional, or excess, noise found in real devices, caused by
various sources.
1/f noise is pink noise - it has a 1/f spectrum, which means equal
power per decade of bandwidth, rather than equal power per Hz.

As an example, let’s look at 1/f noise in resistors:
Fluctuations in resistance result in an additional noise voltage which
is proportional to the current flowing in the resistance.
The amount of additional noise depends on resistor construction.
The table below lists the excess noise for various resistor types.
The entries are given in rms voltage, per volt applied across the
resistor, and measured over one decade of bandwidth:
Carbon-composition 0.10 µV/V to 3 µV/V
Carbon-film 0.05 µV/V to 0.3 µV/V
Metal-film 0.02 µV/V to 0.2 µV/V
Wire-wound 0.01 µV/V to 0.2 µV/V
Other mechanisms producing 1/f noise:
G Base current noise in transistors.
G Cathode current noise in vacuum tubes.
G Speed of ocean currents.
G Flow of sand in an hourglass.
G Yearly flow of the Nile (measured over past 2000 years).
G Loudness of a piece of classical music vs. time.

Interference
In this case any interfering signal or unwanted “stray” pickup
constitutes a form of noise.
The frequency spectrum and amplitude characteristics depend on
type of interference:
Sharp spectrum, relatively constant amplitude:
60 Hz interference.
Radio and television stations.
Broad spectrum, probabilistic amplitude:
Automobile ignition noise.
Lightning.
Motors, switches, switching regulators, etc.
Some circuits, detectors, cables, etc., are microphonic:
Noise voltage or current is generated as a result of vibration.

Introduction to Electronics 211Amplifier Noise Performance
Noiseless
en
invsig
Rsig
+
Noisy amplifier
Fig. 289. Noise model of an amplifier.
Amplifier Noise Performance
Terms, Definitions, Conventions
Any noisy amplifier can be completely specified for noise in terms
of two noise generators, en and in :
Amplifier Noise Voltage:
Amplifier noise voltage is more properly called the equivalent short-
circuit input rms noise voltage.
en is the noise voltage that appears to be present at an amplifier
input if the input terminals are shorted. It is equivalent to a noisy
offset voltage, and is expressed in nV / at a specific frequency.Hz
It is measured by:
G shorting the amplifier input,
G measuring the rms noise output,
G dividing by amplifier gain (and further dividing by ).B
en increases at lower frequencies, so it appears as 1/f noise.

SNR
P
P
sig
n
=





10log dB (318)
SNR
v
e
sig
n
=





20log dB (319)
Amplifier Noise Current:
Amplifier noise current is more properly called the equivalent open-
circuit input rms noise current.
in is the apparent noise current at an amplifier input. It is equivalent
to a noisy bias current, and is expressed in pA / at a specificHz
frequency.
It is measured by:
G shunting the amplifier input with a resistor,
G measuring the rms noise output,
G dividing by amplifier gain (and further dividing by ),B
G “subtracting” noise due to en and the resistor (we discuss
adding and subtracting noise voltages later).
in increases at lower frequencies for op amps and BJTs - it
increases at higher frequencies for FETs.
Signal-to-Noise Ratio:
Expressed in decibels, the default definition is a ratio of signal
power to noise power (delivered to the same resistance, and
measured with the same bandwidth and center frequency):
It can also be expressed as the ratio of rms voltages:

Av Vn
RS (T = 0) Real (noisy)
Amplifier
Fig. 290. Noisy amplifier with ideal
input.
Av Vn
RS (T = Tn) Noiseless
Amplifier
Fig. 291. Ideal amplifier with noisy
input.
( )
( )
NF
P P
P P
sig n input
sig n output
=








10log
/
/
dB (320)
NF SNR SNRinput output= − (321)
Noise Figure:
This is a figure of merit for comparing amplifiers. It indicates how
much noise an amplifier adds.
Defined simply:
It can be written even more simply:
Note that NF will always be greater than 0 dB for a real amplifier.
Noise Temperature:
An alternative figure of merit to noise figure, it gives the same
information about an amplifier. The definition is illustrated below:
A real amplifier (Fig. 290) that produces vn at its output with a
noiseless input, has the noise temperature Tn.
An ideal, noiseless amplifier (Fig. 291) with a source resistance at
T = Tn produces the same noise voltage at its output.

( )T T NF
T
T
n
NF n
= − ⇔ = +




10 1 10 110/
log (322)
v v etotal sig n
2 2 2
= + (323)
Converting NF to/from Tn :
where, NF is expressed in dB
T is the ambient (room) temperature, usually 290 K
For good, low-noise amplifier performance:
NF << 3 dB and/or Tn << 290 K
Adding and Subtracting Uncorrelated Quantities
This applies to operations such as noise noise, or noise signal.± ±
Because noise is probabilistic, we don’t know instantaneous
amplitudes. As a result we can only add and subtract powers.
This means squared amplitudes add (rms amplitudes do not), e.g.:

Introduction to Electronics 215Amplifier Noise Calculations
Noiseless
en
invsig
Rsig
+
Noisy amplifier
Fig. 292. Noise model of an amplifier (Fig. 289 repeated).
e e e i Rt r n n sig
2 2 2 2 2
= + + (324)
e e i Req n n sig
2 2 2 2
= + (325)
Amplifier Noise Calculations
Introduction
Repeating our amplifier noise model:
We presume the input resistance of the noiseless amplifier is much
larger than Rsig , and describe the following amplifier noise sources:
er , the Johnson noise of Rsig ,
en ,the amplifier noise source (amplifier noise referred to the input),
in Rsig , the noise voltage resulting from in flowing through Rsig
The total input noise is (assuming they are uncorrelated):
For convenience, we define the last two terms of eq. (324) as the
equivalent amplifier input noise, i.e., the amplifier noise contribution
with a noise-free Rsig :

Introduction to Electronics 216Amplifier Noise Calculations
( )
( )
( )
( )
NF
P P
P P
P P
P P
P G e
e P G
e
e
e e i R
e
e i R
e
sig n input
sig n output
sig input n output
n input sig output
sig input p t
r sig input p
t
r
r n n sig
r
n n sig
r
=








=
×
×






=








=





 =
+ +





= +
+




 =
10 10
10 10 10
10 1 10
2
2
2
2
2 2 2 2
2
2 2 2
2
log
/
/
log
log log log
log log 1
2
2+






e
e
eq
r
(326)
Calculating Noise Figure
The noise figure of this amplifier may now be calculated. We use
the definition of NF as the ratio of powers, and let Gp represent the
amplifier power gain:
Observe that for small Rsig, amplifier noise voltage dominates, while
for large Rsig , the amplifier noise current dominates.
FET amplifiers have nearly zero noise current, so they have a clear
advantage !!!
Remember, NF data must include values of Rsig and frequency to
have significance.

Introduction to Electronics 217Typical Manufacturer’s Noise Data
Fig. 293. 2N5210 noise voltage vs.
frequency, for various quiescent collector
currents.
Fig. 294. 2N5210 noise current vs. frequency,
for variousquiescent collector currents.
Fig. 295. 2N5210 total noise voltage at 100 Hz
vs. source resistance, for various quiescent
collector currents
Typical Manufacturer’s Noise Data
Introduction
Manufacturers present noise data in various ways. Here is some
typical data for Motorola’s 2N5210 npn BJT:

e e e i Rt r n n sig
2 2 2 2 2
= + + (327)
et = 6 97. nV / Hz (328)
The en , in data of Figs. 293 and 294 can be used to construct
Fig. 295, a plot of total noise voltage, et , for various values of Rsig .
We simply follow eq. (324), repeated here:
Example #1
Calculate the total equivalent input noise per unit bandwidth, for a
2N5210 operating at 100 Hz with a source resistance of 1 kΩ, and
a collector bias current of 1 mA:
1. er 4.02 nV / from eq. (316).≈ Hz
2. en 4.5 nV / (f = 100 Hz, IC = 1 mA) from Fig. 293.≈ Hz
3. in 3.5 pA / (f = 100 Hz, IC = 1 mA) from Fig. 294.≈ Hz
Evaluating eq. (327) - remembering to square the terms on the
right-hand side, and take the square root of the resulting sum -
gives :
This compares favorably (within graphical error) with a value slightly
greater than 7 nV / obtained from Fig. 295.Hz
Of course, it would take many calculations of this type to produce
the curves of Fig. 295.

NF
e i R
e
n n sig
r
= +
+




10 1
2 2 2
2
log (329)
Fig. 296. 2N5210 100-Hz noise figure vs.
source resistance, at various quiescent
collector currents.
( )
( )
( )NF = +







 = =10 1
570
4 02
10 3 01 4 79
2
2
log
.
.
log . . dB (330)
Example #2
Determine the narrow bandwidth noise figure for the amplifier of
example #1 (f = 100 Hz, ICQ = 1 mA, Rsig = 1 kΩ).
1. From eq. (326), repeated here
with the values of en , in , and er from example #1, we calculate:
which compares favorably to the value of approx. 5 dB obtained
from the manufacturer’s data shown below:

Introduction to Electronics 220Noise - References and Credits
Noise - References and Credits
References for this section on noise are:
1. Noise Specs Confusing?, Application Note 104, National
Semiconductor Corp., May 1974.
This is an excellent introduction to noise. I highly recommend
that you get a copy. It is available on National’s website at
http://www.national.com
2. The Art of Electronics, 2nd
ed., Paul Horowitz and Winfield Hill,
Cambridge University Press, New York, 1989.
This text has a good treatment of noise, and makes a good
general electronics reference. Check it out at
http://www.artofelectronics.com
3. The 2N5210 data sheets, of which Figs. 293 - 296 are a part,
are available from Motorola, Inc., at http://www.motorola.com

Introduction to Electronics 221Introduction to Logic Gates
VDC
VOVI
Fig. 297. Logic inverter. DC supply
connections are not normally shown.
VO
VI
VDC
VDCVDC /2
ideal
actual
Fig. 298. Ideal and actual inverter transfer
functions.
Introduction to Logic Gates
The Inverter
We will limit our exploration to the logic inverter, the simplest of
logic gates. A logic inverter is essentially just an inverting amplifier,
operated at its saturation levels:
The Ideal Case
VI is either VDC (logic 1) or zero (logic 0).
VO is either zero (logic 0) or VDC (logic 1).
The Actual Case
We don’t know the exact transfer function of any individual logic
inverter.
Manufacturer’s specifications give us a clue about the “range” of
permitted input and output levels.

VO
VI
VDC
VDC
VOH
VOL
VIHVIL
tr. fn. forbidden regions
Fig. 300. Mfr’s voltage specs illustrated with
example transfer functions.
VDC
VOH
VIH
VIL
VOL
0
Output:
Logic 1
Output: Logic 0
Input sees
Logic 1
Input sees
Logic 0
NMH
NML
Fig. 299. Mfr’s voltage specs illustrated
on a number line.
NM V V NM V VH OH IH L IL OL= − = −and (331)
Manufacturer’s Voltage Specifications
G VIH = lowest VI guaranteed to be “seen” as “high” (logic 1).
G VIL = highest VI guaranteed to be “seen” as “low” (logic 0).
And with VI meeting the above specifications:
G VOH = lowest “high” (logic 1) output voltage.
G VOL = highest “low” (logic 0) output voltage.
Noise Margin
Noise margin is the maximum noise amplitude that can be added
to the input voltage, without causing an error in the output logic
level. It is the smaller of:

Fig. 301. Reference directions for mfr’s current
specifications.
Fig. 302. Fan-out illustrated.
FO
I
I
H
OH
IH
=





int (332)
FO
I
I
L
OL
IL
=





int (333)
Manufacturer’s Current Specifications
Note that the reference
direction for both input and
output currents is into the chip.
G IOH = highest current that output can source with VO VOH .≥
G IOL = highest current that output can sink with VO VOL .≤
G IIH = highest possible input current with VI VIH .≥
G IIL = highest possible input current with VI VIL .≤
Fan-Out
Fan-out is defined as the maximum number of gates that can be
driven without violating the voltage specifications. It must be an
integer, of course; it is the smaller of:
and

VDC
VO
RHIGH
RLOW
CLOAD
S
Fig. 303. Simple model of logic
gate output.
Q C VLOAD DC= (334)
E QV C VDC LOAD DC= =
2
(335)
Power Consumption
Static Power Consumption:
The static power is the power required to run the chip when the
output isn’t changing.
It may be different when the output is high may be different than
when the output is low. Thus, we normally assume that it is merely
the average of the two.
Dynamic Power Consumption:
Because load capacitance is always present, additional power is
required when the output is changing states.
To understand this, consider the following logic gate model, and
presume the switch begins in the low position.
When the switch goes high, CLOAD charges from VOL ( 0) to≈
VOH ( VDC ).≈
At the end of this charging cycle, the
charge stored in CLOAD is:
And the energy required of VDC to deliver
this charge is:

VDC
VO
RHIGH
RLOW
CLOAD
S
Fig. 304. Logic gate model (Fig.
303 repeated).
E C VC LOAD DC=
1
2
2
(336)
C V
T
C V fLOAD DC
LOAD DC
2
2
= (337)
P C V fdynamic LOAD DC=
2
(338)
Of the energy required of VDC , half is
stored in the capacitor:
The remaining half of the energy required
of VDC has been dissipated as heat in
RHIGH .
Now the switch changes state, i.e., goes
low. CLOAD discharges toward VOL ( 0),≈
and the energy stored in CLOAD is
dissipated in RLOW.
Finally, suppose VO is continually changing states, with a frequency
f (i.e., with period T). The energy dissipated in the gate per period
is:
But energy per unit time is power, i.e., the dynamic power
dissipation:

VOH
VOL
100%
90%
50%
10%
0%
vI
t
tr tf
vO
t
tPHL tPLH
VOH
VOL
50%
Fig. 305. Generic examples of rise time, fall time, and
propagation delay.
Rise Time, Fall Time, and Propagation Delay
We use the following definitions to describe logic waveforms:
tr , rise time - time interval for a waveform to rise from 10% to
90% of its total change
tf , fall time - time interval for a waveform to fall from 90% to 10%
of its total change
tPHL and tPLH , propagation delay -
time interval from the 50% level of the input
waveform to 50% level of the output
tPD , average propagation delay -
simply, the average of tPHL and tPLH

Speed-Power Product
The speed-power product provides a “figure of merit” of a logic
family.
It is defined as the product of propagation delay (speed) and static
power dissipation (power) per gate
Note this product has units of energy.
Currently, the speed-power product of logic families range from
approximately from 5 pJ to 50 pJ

TTL Logic Families & Characteristics
hex inverter ⇒ 7404 74S04 74LS04 74AS04 74ALS04 74F04
parameter
unit
standard
S
Schottky
LS
low-powerS
AS
advancedS
ALS
advancedLS
F
FAST
tPD ns 10 3 10 2 4 3
Pstatic mW 10 19 2 7 1 4
IOH µA -400 -1000 -400 -2000 -400 -1000
IOL mA 16 20 8 20 8 20
IIH µA 40 50 20 20 20 20
IIL mA -1.6 -2.0 -0.4 -0.5 -0.1 -0.6
VOH V 2.4 2.7 2.7 3.0 3.0 2.7
VOL V 0.4 0.5 0.5 0.5 0.5 0.5
VIH V 2.0 V for all TTL families
VIL V 0.8 V for all TTL families
. . . table compiled by Prof. D.B. Brumm

CMOS Logic Families & Characteristics
These are typical examples of the guaranteed values for VDC = 5 V,
and are specifications for driving auxiliary loads, not other gates
alone..
Output current ratings depend upon the specific gate type, esp. in
the 4000 series.
Ratings for IOH and IOL are given for the specific VOH and VOL .
parameter
unit
4000
74C
74HC
74HCT
AC
ACT
tPD ns 80 90 9 10 5 5
Pstatic < 1 µW for all versions
IOH mA -1.0 -0.36 -4.0 -4.0 -24 -24
IOL mA 2.4 0.36 4.0 4.0 24 24
IIH µA 1.0 1.0 1.0 1.0 1.0 1.0
IIL mA -1.0 -1.0 -1.0 -1.0 -1.0 -1.0
VOH V 2.5 2.4 3.5 3.5 3.7 3.7
VOL V 0.4 0.4 0.4 0.4 0.4 0.4
VIH V 3.5 3.5 3.5 2.0 3.5 2.0
VIL V 1.5 1.5 1.0 0.8 1.5 0.8
VDC V 3 - 15 3 - 15 2 - 6 5±0.5 2 - 6 5±0.5
. . . table compiled by Prof. D.B. Brumm

Introduction to Electronics 230MOSFET Logic Inverters
VDD
VI
VO
Rpull-up
Fig. 306. NMOS inverter with
resistive pull-up for the load.
Drain Voltage, VDS
VGS = 3 V
VGS = 4 V
VGS = 5 V
VGS = 6 V
8 V VGS = 7 V910 V
Fig. 307. Ideal FET output characteristics, and load line for
VDD = 10 V and Rpull-up = 10 kΩ.
DrainCurrent,ID
MOSFET Logic Inverters
NMOS Inverter with Resistive Pull-Up
As Fig. 306 shows, this is the most basic of inverter circuits.
Circuit Operation:
The term NMOS implies an n-channel enhancement MOSFET.
Using a graphical analysis technique, we can plot the load line on
the output characteristics, shown below.
When the FET is operating in its triode region, it pulls the output
voltage low, i.e., toward zero. When the FET is in cutoff, the drain
resistance pulls the output voltage up, i.e., toward VCC, which is why
it is called a pull-up resistor.
Because VGS = VI and VDS = VO , we can use Fig. 307 to plot the
transfer function of this inverter.

Input Voltage, VI
Fig. 308. Inverter transfer function.
Drawbacks:
1. A large R results in reduced VO for anything but the largest
loads, and slows output changes for capacitive loads.
2. A small R results in excessive current, and power dissipation,
when the output is low.
The solution to both of these problems is to replace the pull-up
resistor with an active pull-up.
OutputVoltage,VO

VDD
VI VO
D
D
S
S
G
G
vGSN
vSGP
+
+
+-
-
-
vSDP
vDSN
+
-
Fig. 309. CMOS inverter.
Drain-Source Voltage of NMOS FET, VDSN
VGSN = 3 V
VGSN = 4 V
VGSN = 5 V
VGSN = 6 V
VGSN = 7 V8 V10 V 9
Fig. 310. Ideal NMOS output characteristics.
DrainCurrent,ID
CMOS Inverter
Circuit Operation:
The CMOS inverter uses an active pull-up,
a PMOS FET in place of the resistor.
The PMOS and NMOS devices are
complementary MOSFETs, which gives rise
to the name CMOS.
In the previous example, the resistor places
a load line on the NMOS output
characteristic.
Here, the PMOS FET places a load curve on the output
characteristic. The load curve changes as VI changes !!!
The NMOS output curves are the usual fare, and are shown in the
figure below:

VSGP = 3 V
VSGP = 4 V
VSGP = 5 V
VSGP = 6 V
VSGP = 7 V8 V10 V 9
Source-Drain Voltage of PMOS FET, VSDP
Fig. 311. Ideal PMOS output characteristics.
v V vSGP DD GSN= − (339)
v V vSDP DD DSN= − (340)
DrainCurrent,|ID|
The PMOS output curves, above, are typical also, but on the input
side of the PMOS FET:
This means we can re-label the PMOS curves in terms of vGSN.
And, on the output side of the PMOS FET:
This means we can “rotate and shift” the curves to display them in
terms of vDSN. This is done on the following page.

VDSN (= 10 V - VSDP )
VGSN = 7 V (VSGP = 3 V)
VGSN = 3 V 2 V 0 V1
Fig. 312. PMOS “load curves” for VDD = 10 V.
DrainCurrent,|ID|
The curves above are the same PMOS output characteristics of Fig.
233, but they’ve been:
1. Re-labeled in terms of vGSN .
2. Rotated about the origin and shifted to the right by 10 V (i.e.,
displayed on the vDSN axis).

VGSN = 7 V
VGSN = 6 V
VGSN = 5 V
VGSN = 4 V
VGSN = 3 V 2 V 0 V1
VGSN = 3 V
VGSN = 4 V
VGSN = 5 V
VGSN = 6 V
VGSN = 7 V8 V10 V 9
NMOS Drain-Source Voltage, VDSN
Fig. 313. NMOS output characteristics (in blue) and PMOS load
curves (in green) plotted on same set of axes.
DrainCurrent,|ID|
We can now proceed with a graphical analysis to develop the
transfer characteristic. We do so in the following manner:
1. We plot the NMOS output characteristics of Fig. 310, and the
PMOS load curves of Fig. 312, on the same set of axes.
2. We choose the single correct output characteristic and the
single correct load curve for each of several values of vI .
3. We determine the output voltage from the intersection of the
output characteristic and the load curve, for each value of vI
chosen in the previous step.
4. We plot the vO vs. vI transfer function using the output voltages
determined in step 3.
The figure below shows the NMOS output characteristics and the
PMOS load curves plotted on the same set of axes:

VI = VGSN = 3 V
Fig. 314. Appropriate NMOS and PMOS curves for vI = 3 V.
VI = VGSN = 4 V
DrainCurrent,|ID|DrainCurrent,|ID|
Note from Fig. 313 That for VI = VGSN 2 V the NMOS FET (blue≤
curves) is in cutoff, so the intersection of the appropriate NMOS and
PMOS curves is at VO = VDSN = 10 V.
As VI increases above 2 V, we select the appropriate NMOS and
PMOS curve, as shown in the figures below.

VI = VGSN = 5 V
VI = VGSN = 6 V
DrainCurrent,|ID|DrainCurrent,|ID|
Because the ideal characteristics shown in these figures are
horizontal, the intersection of the two curves for VI = VGSN = 5 V
appears ambiguous, as can be seen below.
However, real MOSFETs have finite drain resistance, thus the
curves will have an upward slope. Because the NMOS and PMOS
devices are complementary, their curves are symmetrical, and the
true intersection is precisely in the middle:

Input Voltage, VI
Fig. 319. CMOS inverter transfer function. Note the similarity to
the ideal transfer function of Fig. 298.
VI = VGSN = 7 V
OutputVoltage,VO
For VI = VGSN 8 V, the PMOS FET (green curves) is in cutoff, so≥
the intersection is at VO = VDSN = 0 V.
Collecting “all” the intersection points from Figs. 314-318 (and the
ones for other values of vI that aren’t shown here) allows us to plot
the CMOS inverter transfer function:
DrainCurrent,|ID|

Introduction to Electronics 239Differential Amplifier
+
-
+
-
+
-
+
-
vI1 vI2
vICM
vID /2
vID /2
1
1
2
2
+-
Fig. 320. Representing two sources by their differential and
common-mode components (Fig. 41 repeated).
v v
v
v v
v
I ICM
ID
I ICM
ID
1 2
2 2
= + = −and (341)
v v v v
v v
ID I I ICM
I I
= − =
+
1 2
1 2
2
and (342)
Differential Amplifier
We first need to remind ourselves of a fundamental way of
representing any two signal sources by their differential and
common-mode components. This material is repeated from pp. 27-
28:
Modeling Differential and Common-Mode Signals
As shown above, any two signals can be modeled by a differential
component, vID , and a common-mode component, vICM , if:
Solving these simultaneous equations for vID and vICM :
Note that the differential voltage vID is the difference between the
signals vI1 and vI2 , while the common-mode voltage vICM is the
average of the two (a measure of how they are similar).

RC RC
IBIAS
VCC
-VEE
vI1 vI2
vOD
vO1 vO2
Q1 Q2
iC1 iC2
+
+
+
-
- -
Fig. 321. Differential amplifier.
RC RC
IBIAS
VCC
-VEE
vOD
vO1 vO2
Q1 Q2
iC1 iC2
+
+
+
-
- -
vICM
+
-
vICM vICM
Fig. 322. Differential amplifier with only a
common-mode input.
v V R i
v V R i
O CC C C
O CC C C
1 1
2 2
= −
= −
(343)
( )
v v v
R i i
OD O O
C C C
= −
= −
1 2
2 1
(344)
i i
I
E E
BIAS
1 2
2
= = (345)
i i
I
C C
BIAS
1 2
2
= =
α (346)
vOD = 0 (347)
Basic Differential Amplifier Circuit
The basic diff amp circuit consists of
two emitter-coupled transistors.
We can describe the total
instantaneous output voltages:
And the total instantaneous differential
output voltage:
Case #1 - Common-Mode Input:
We let vI1 = vI2 = vICM, i.e., vID = 0.
From circuit symmetry, we can
write:
and

RC RC
IBIAS
VCC
-VEE
vOD
vO1 vO2
Q1 Q2
iC1 iC2
+
+
+
-
- -
vID /2 = 1 V vID /2 = 1 V
+
+-
-
+1 V -1 V
0.7 V
+
- 0.3 V -1.3 V
+
-
Fig. 323. Differential amplifier with +2 V
differential input.
RC RC
IBIAS
VCC
-VEE
vOD
vO1 vO2
Q1 Q2
iC1 iC2
+
+
+
-
- -
vID /2 = -1 V vID /2 = -1 V
+
+-
-
-1 V +1 V
0.7 V
+
- 0.3 V-1.3 V
+
-
Fig. 324. Differential amplifier with -2 V
differential input.
iC2 0= (348)
v VO CC2 = (349)
i i IC E BIAS1 1= =α α (350)
v V R IO CC C BIAS1 = −α (351)
v R IOD C BIAS= −α (352)
iC1 0= (353)
v VO CC1 = (354)
i i IC E BIAS2 2= =α α (355)
v V R IO CC C BIAS2 = −α (356)
v R IOD C BIAS= α (357)
Case #2A - Differential Input:
Now we let vID = 2 V and vICM = 0.
Note that Q1 is active, but Q2 is
cutoff. Thus we have:
Case #2B - Differential Input:
This is a mirror image of Case
#2A. We have vID = -2 V and
vICM = 0.
Now Q2 is active and Q1 cutoff:
These cases show that a common-mode input is ignored, and that
a differential input steers IBIAS from one side to the other, which
reverses the polarity of the differential output voltage!!!
We show this more formally in the following sections.

Introduction to Electronics 242Large-Signal Analysis of Differential Amplifier
RC RC
IBIAS
VCC
-VEE
vI1 vI2
vOD
vO1 vO2
Q1 Q2
iC1 iC2
+
+
+
-
- -
Fig. 325. Differential amplifier circuit
i I
V
V
C S
BE
T
1
1
=





exp (358)
i I
v
V
C S
BE
T
2
2
=





exp (359)
i
i
v v
V
v
V
C
C
BE BE
T
ID
T
1
2
1 2
=
−




 =





exp exp (360)
i
i
v
V
C
C
ID
T
1
2
1 1+ = +





exp (361)
i
i
i i
i
I
i
C
C
C C
C
BIAS
C
1
2
1 2
2 2
1+ =
+
=
α
(362)
Large-Signal Analysis of Differential Amplifier
We begin by assuming identical devices
in the active region, and use the forward-
bias approximation to the Shockley
equation:
Dividing eq. (358) by eq. (359):
From eq. (360) we can write:
And we can also write:

vID / VT
Fig. 326. Normalized collector currents vs.
normalized differential input voltage, for a differential
amplifier.
i
I
v
V
C
BIAS
ID
T
2
1
=
+






α
exp
(363)
i
I
v
V
C
BIAS
ID
T
1
1
=
+ −






α
exp
(364)
Equating (361) and (362) and solving for iC2 :
To find a similar expression for iC1 we would begin by dividing eqn.
(359) by (358) . . . the result is:
The current-steering effect of varying vID is shown by plotting eqs.
(363) and (364):
Note that IBIAS is steered from one side to the other . . .as vid
changes from approximately -4VT (-100 mV) to +4VT (+100 mV)!!!
iC/αIBIAS

i
I
v
V
v
V
v
V
I
v
V
v
V
v
V
C
BIAS
ID
T
ID
T
ID
T
BIAS
ID
T
ID
T
ID
T
2
1
2
2
2
2 2
=
+


















−






−


















=
−











 + −






α
α
exp
exp
exp
exp
exp exp
(365)
i
I
v
V
v
V
v
V
I
v
V
v
V
v
V
C
BIAS
ID
T
ID
T
ID
T
BIAS
ID
T
ID
T
ID
T
1
1
2
2
2
2 2
=
+ −










































=











 + −






α
α
exp
exp
exp
exp
exp exp
(366)
v I R
v
V
v
V
v
V
v
V
OD BIAS C
ID
T
ID
T
ID
T
ID
T
= −





 − −











 + −






α
exp exp
exp exp
2 2
2 2
(367)
v I R
v
V
OD BIAS C
ID
T
= −





α tanh
2
(368)
Using (363) and (364), and recalling that vOD = RC ( iC2 - iC1 ):
Thus we see that differential input voltage and differential output
voltage are related by a hyperbolic tangent function!!!

vID / VT
Fig. 327. Normalized differential output voltage vs.
normalized differential input voltage, for a differential
amplifier.
A normalized version of the hyperbolic tangent transfer function is
plotted below:
This transfer function is linear only for |vID /VT| much less than 1,
i.e., for |vID| much less than 25 mV!!!
We usually say the transfer function is acceptably linear for a |vID|
of 15 mV or less.
If we can agree that, for a differential amplifier, a small input signal
is less than about 15 mV, we can perform a small-signal analysis of
this circuit !!!
VOD/αRCIBIAS

Introduction to Electronics 246Small-Signal Analysis of Differential Amplifier
RC RC
IBIAS
VCC
-VEE
vI1 vI2
vOD
vO1 vO2
Q1 Q2
iC1 iC2
+
+
+
-
- -
Fig. 328. Differential amplifier (Fig. 321
repeated).
RC RC
βib2βib1
rπrπ
ib2ib1
REB
(β+1)ib2(β+1)ib1
vid /2 vid /2
vod
vo1 vo2
+
+
+
+ +
-
-
--
-
vX
Fig. 329. Small-signal equivalent with a differential input. REB is
the equivalent ac resistance of the bias current source.
Small-Signal Analysis of Differential Amplifier
Differential Input Only
We presume the input to the
differential amplifier is limited to a
purely differential signal.
This means that vICM can be any
value.
We further presume that the
differential input signal is small as
defined in the previous section.
Thus we can construct the small-
signal equivalent circuit using
exactly the same techniques that
we studied previously:

RC RC
βib2βib1
rπrπ
ib2ib1
REB
(β+1)ib2(β+1)ib1
vid /2 vid /2
vod
vo1 vo2
+
+
+
+ +
-
-
--
-
vX
Fig. 330. Diff. amp. small-signal equivalent (Fig. 329 repeated).
( )( )v
i r i i Rid
b b b EB
2
11 1 2= + + +π β (369)
( )[ ] ( )[ ]v
i r R i Rid
b EB b EB
2
1 11 2= + + + +π β β (370)
( )( )− = + + +
v
i r i i Rid
b b b EB
2
12 1 2π β (371)
( )[ ] ( )[ ]− = + + + +
v
i r R i Rid
b EB b EB
2
1 12 1π β β (372)
We begin with a KVL equation around left-hand base-emitter loop:
and collect terms:
We also write a KVL equation around right-hand base-emitter loop:
and collect terms:

RC RC
βib2βib1
rπrπ
ib2ib1
REB
(β+1)ib2(β+1)ib1
vid /2 vid /2
vod
vo1 vo2
+
+
+
+ +
-
-
--
-
vX
( ) ( )[ ]0 2 11 2= + + +i i r Rb b EBπ β (373)
( )i ib b1 2 0+ = (374)
Adding (370) and (372):
Because neither resistance is zero or negative, it follows that
and, because vX = (ib1 + ib2)REB , the voltage vX must be zero, i.e.,
point X is at signal ground for all values of REB !!!
The junction between the collector resistors is also at signal ground,
so the left half-circuit and the right half-circuit are independent of
each other, and can be analyzed separately !!!

Fig. 332. Left half-circuit of
differential amplifier with a differential
input.
v
v
v
v
R
r
o
in
o
id
C1 1
2 2
= =
−
/
β
π
(375)
A
v
v
R
r
vds
o
id
C
1
1
2
= =
−β
π
(376)
A
v
v
R
r
vds
o
id
C
2
2
2
= =
β
π
(377)
A
v
v
R
r
vdb
od
id
C
= =
−β
π
(378)
Analysis of Differential Half-Circuit
The circuit at left is just the small-
signal equivalent of a common emitter
amplifier, so we may write the gain
equation directly:
For vo1/vid we must multiply the
denominator of eq. (375) by two:
In the notation Avds the subscripts mean:
v, voltage gain d, differential input s, single-ended output
The right half-circuit is identical to Fig. 332, but has an input of
-vid /2, so we may write:
Finally, because vod = vo1 - vo2 , we have the result:
where the subscript b refers to a balanced output.
Thus, we can refer to differential gain for either a single-ended
output or a differential output.

RC RC
βib2βib1
rπrπ
ib2ib1
REB
(β+1)ib2(β+1)ib1
vid /2 vid /2
vod
vo1 vo2
+
+
+
+ +
-
-
--
-
vX
v
i
r
v
i
R rid
b
id
b
id
/ 2
2
1 1
= ⇒ = =π π (379)
R R R Ros C od C= =and 2 (380)
Remember our hyperbolic tangent transfer function? Eq. (378) is
just the slope of that function, evaluated at vID = 0 !!!
Other parameters of interest . . .
Differential Input Resistance
This is the small-signal resistance seen by the differential source:
Differential Output Resistance
This is the small-signal resistance seen by the load, which can be
single-ended or balanced. We can determine this by inspection:

RC RC
IBIAS
VCC
-VEE
vI1 vI2
vOD
vO1 vO2
Q1 Q2
iC1 iC2
+
+
+
-
- -
Fig. 334. Differential amplifier (Fig. 321
repeated).
RC RC
βib2βib1
rπrπ
ib2ib1
2REB
(β+1)ib2(β+1)ib1
vicm vicm
vod
vo1 vo2
+ +
+
+ +
-
-
--
-
2REB
Fig. 335. Small-signal equivalent with a common-mode input. The
resistance of the bias current source is represented by
2REB || 2REB = REB.
Common-Mode Input Only
We now restrict the input to a
common-mode voltage only.
This is, we let vID = 0.
We again construct the small-signal
circuit using the techniques we
studied previously.
As a bit of a trick, we represent the
equivalent ac resistance of the bias
current source as two resistors in
series:

RC RC
βib2βib1
rπrπ
ib2ib1
2REB
(β+1)ib2(β+1)ib1
vicm vicm
vod
vo1 vo2
+ +
+
+ +
-
-
--
-
iX = 0
2REB
Fig. 336. Small-signal equivalent with a common-mode input.
Note the current iX .
The voltage across each 2REB resistor is identical because the
resistors are connected across the same nodes.
Therefore, the current iX is zero and we can remove the connection
between the resistors !!!
This “decouples” the left half-circuit from the right half-circuit at the
emitters.
At the top of the circuit, the small-signal ground also decouples the
left half-circuit from the right half-circuit.
Again we need only analyze one-half of the circuit !!!

RC
βib1
rπ
ib1
vicm
vo1 or vo2
+
+
-
-
2REB
Fig. 337. Either half-circuit of diff.
amp. with a common-mode input.
( )
v
v
v
v
R
r R
o
icm
o
icm
C
EB
1 2
1 2
= =
−
+ +
β
βπ
(381)
Avcd = 0 (382)
( )[ ]R
v
i i
v
i
r Ricm
icm
b b
icm
b
EB=
+
= = + +
1 2 12
1
2
1 2π β (383)
R R R Ros C od C= =and 2 (384)
Analysis of Common-Mode Half-Circuit
Again, the circuit at left is just the
small-signal equivalent of a common
emitter amplifier (this time with an
emitter resistor), so we may write the
gain equation:
Eq. (381) gives Avcs , the common-
mode gain for a single-ended output.
Because vo1 = vo2 , the output for a
balanced load will be zero:
Common-mode input resistance:
Because the same vicm source is connected to both bases:
Common-mode output resistance:
Because we set independent sources to zero when determining Ro,
we obtain the same expressions as before:

( )CMRR
A
A
r R
r
R
r
vds
vcs
EB EB
= =
+ +
≈π
π π
β β1 2
2
(385)
CMRR CMRRdB = 20log (386)
Common-Mode Rejection Ratio
CMRR is a measure of how well a differential amplifier can amplify
a differential input signal while rejecting a common-mode signal.
For a single-ended load:
For a differential load CMRR is theoretically infinite because Avcd is
theoretically zero. In a real circuit, CMRR will be much greater than
that given above.
To keep these two CMRRs in mind it may help to remember the
following:
G Avcs = 0 if the bias current source is ideal (for which REB = ).∞
G Avcd = 0 if the circuit is symmetrical (identical left- and right-
halves).
CMRR is almost always expressed in dB:

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