EE100B-p11.ppt
- 1. 1 Figure 9.36 The process of periodically sampling an analog signal. (a) Sample-and-hold (S/H) circuit. The switch closes for a small part (t seconds) of every clock period (T). (b) Input signal waveform. (c) Sampling signal (control signal for the switch). (d) Output signal (to be fed to A/D converter). Data-Converter Circuits Because digital integrated circuits are economical and accurate, it is convenient to process signals in digital form, for example, to perform algebraic manipulations, to transmit or store signals.
- 2. 2 Figure 9.37 The A/D and D/A converters as circuit blocks. Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters as Functional Blocks
- 3. 3 Figure 9.39 An N-bit D/A converter using a binary-weighted resistive ladder network. D/A Converter Circuits • Binary-weighted registers 1 2... N b b b REF REF REF 1 2 1 ... 2 2 O N N V V V i b b b R R R O O f v i R
- 4. 4 Figure 9.40 The basic circuit configuration of a DAC utilizing an R-2R ladder network. • R-2R ladders REF O V i D R 1 2... N b b b
- 5. 5 Figure 9.41 A practical circuit implementation of a DAC utilizing an R-2R ladder network.
- 6. 6 Figure 9.42 Circuit implementation of switch Sm in the DAC of Fig. 9.41. In a BiCMOS technology, Qms and Qmr can be implemented using MOSFETs, thus avoiding the inaccuracy caused by the base current of BJTs.
- 7. 7 Figure 9.43 A simple feedback-type A/D converter. A/D Converter Circuits • Feedback-type converter
- 8. 8 Figure 9.44 The dual-slope A/D conversion method. Note that vA is assumed to be negative. • Dual-slope converter REF 2N n
- 9. 9 Figure 9.45 Parallel, simultaneous, or flash A/D conversion. • Parallel converter
- 10. 10 Figure 9.46 Charge-redistribution A/D converter suitable for CMOS implementation: (a) sample phase, (b) hold phase, and (c) charge-redistribution phase. • Charge-redistribution converter a) Sample phase b) Hold phase c) Redistribution phase 2 A Q C v 01101