Efficient Designs of Multiported Memory on FPGA
Download as DOCX, PDF0 likes56 views
This paper introduces more efficient designs for multiported memories on FPGAs that reduce BRAM usage. It presents a new approach to using a 2R1W memory as a 2R1W/4R memory, which can then be used as a building block for a hierarchical 4R1W memory design requiring 25% fewer BRAMs. The proposed designs reduce BRAM usage by up to 53-69% for 4R2W 8K-depth memories compared to previous approaches, and can achieve higher frequencies by alleviating complex routing. For a 4R3W 8K-depth memory, the design saves 53% of BRAMs and improves frequency by 20%.
Efficient Designs of Multiported Memory on FPGA
- 1. Efficient Designs of Multiported Memory on FPGA ABSTRACT: The utilization of block RAMs (BRAMs) is a critical performance factor for multiported memory designs on field programmable gate arrays (FPGAs). Not only does the excessive demand on BRAMs block the usage of BRAMs from other parts of a design, but the complex routing between BRAMs and logic also limits the operating frequency. This paper first introduces a brand new perspective and a more efficient way of using a conventional two reads one write (2R1W) memory as a 2R1W/4R memory. By exploiting the 2R1W/4R as the building block, this paper introduces a hierarchical design of 4R1W memory that requires 25% fewer BRAMs than the previous approach of duplicating the 2R1W module. Memories with more read/write ports can be extended from the proposed 2R1W/4R memory and the hierarchical 4R1W memory. Compared with previous xor-based and live value table-based approaches, the proposed designs can, respectively, reduce up to 53% and 69% of BRAM usage for 4R2W memory designs with 8K-depth. For complex multiported designs, the proposed BRAM-efficient approaches can achieve higher clock frequencies by alleviating the complex routing in an FPGA. For 4R3W memory with 8K-depth, the proposed design can save 53% of BRAMs and enhance the operating frequency by 20%. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
- 2. SOFTWARE IMPLEMENTATION: Modelsim Xilinx ISE