Final_Thesis_Presentation

Dresden, 20.01.2016
Analysis and Design of a High-Sensitivity
Bidirectional Power Detector for mm-
Wave Applications
Presented by Md Mohiuddin Abdul Quadir

Analysis and Design of a High-Sensitivity Bidirectional Power
Detector for mm-Wave ApplicationsDate: 20.01.2016
Contents
 Introduction
 Importance of Power Measurement
 RF Power Detector
 Power Measurement Techniques
 Power Detector
 Design and Analytical Solution
 Modification Due to Temperature
 Results of the respective sections
 Op-Amp
 Necessity of Design
 Topology utilized
 Logarithmic Amplifier
 Instrumentation Amplifier
 Results of the sections
 Directional Coupler
 Design
 Result
 Conclusion
Slide Nr. 2

Introduction
Why measure power?
 Accurate method to measure signal amplitude at high
frequencies.
 Proper signal level ensures optimum performance of each
components in a system.
 Transmitting device must obey the regulatory specifications.
Maximum allowed transmitted power is a crucial specification.
 Setting up receivers power level. For example, RSSI
measurement in BTS receiver.
Slide Nr. 3

Introduction
What is an RF Power Detector?
 Monitors or samples the output an RF circuit.
 Develops a DC output voltage with respect to the signal
power incident on it.
 Typically utilized to measure and control RF power in
wireless communication.
Slide Nr. 4

Figure 1: Typical RF Transceiver signal chain
Detector at the
receiver stage
Detector at the
transmitter stage
Directional
Coupler
Slide Nr. 5
Ref: Calvo, Carlos, Obscurities and Applications of RF Power Detectors, Analog Devices, 2007.

Power Measurement Techniques
 Diode Detector
 p-n Junction Diode Detector
 Shcottky Diode Detector
 Transistor Based Detector
 Meyer Detector
 Proposed Detector for this Work
Slide Nr. 6

Power Detector Design Specification
 Dynamic Range: -50 dBm to -20 dBm
 Bandwidth: 150 GHz to 250 GHz
 Settling Time: 10 ns
 Technology: IHP SG13G2 SiGe BiCMOS
Slide Nr. 7

Proposed Detector
Detector Stage Reference Stage
Slide Nr. 8

Proposed Detector (analytical solution)
a
1LI
1CI
01I
0111 III CL 





 
T
inB
S
V
tVV
I
cos
exp 






T
in
CQ
V
tV
I
cos
exp
Slide Nr. 9

a
1LI
1CI
01I
...cos2cos2
cos
exp 210 























t
V
V
Bt
V
V
B
V
V
B
V
tV
T
in
T
in
T
in
T
in


Where, Bn(Vin/VT) are modified Bessel function
Slide Nr. 10

a
1LI
1CI
01I







T
in
CQC
V
V
BII 01
___
1
Slide Nr. 11

a
1LI
1CI
01I
      010011det /exp1)()( tdBdBIRVtV CQLCC 
Where, d = Vin / VT
τ01 = time constant = RL1.C01
Slide Nr. 12

a
1LI
1CI
01I
)(..)(
.)0(
011det
11det
dBIRVtV
IRVtV
CQLCC
CQLCC


Slide Nr. 13

b
2LI
2CI
02I
2202 .)( LCQCC RIVtV 
Slide Nr. 14

     1)()( 0det  dBRItVtVtV LCQrefout
Slide Nr. 15

Transient Response of the Detector
Input signal power:
-20 dBm
Operating
frequency: 180 GHz
22)( LCQCCref RIVtV 
)()(
)0(
011det
11det
dBIRVtV
IRVtV
CQLCC
CQLCC


 1)()( 0  dBRItV LCQout
0 10 20 30 40 50
-1.5
-1
-0.5
0
0.5
Time / ns
V
det
-V
op
/V
0 10 20 30 40 50
-0.5
0
0.5
1
1.5
Time / ns
V
out
/V
Ripple
voltage
Slide Nr. 16

Ripple voltage
 The alternating
component of the
unidirectional voltage.
 Transient analysis
shows the existence of
ripple voltage.
 Lower value capacitor
provides fast settling
time in expense of
increasing ripple.
0 10 20 30 40 50
-1.5
-1
-0.5
0
0.5
Time / ns
Vdet
-V
op
/V
20 fF
250 fF
500 fF
Slide Nr. 17

Proposed Detector Response
-50 -45 -40 -35 -30 -25 -20
0
0.2
0.4
0.6
0.8
1
1.2
Input Signal Power / dBm
Vout
/V
-50 -45 -40 -35 -30 -25 -20
10
-2
10
-1
10
0
V
out
/V
Operating Frequency: 180 GHz
IBQ = 15 nA
ICQ = 16 µA
Slide Nr. 18

Proposed Detector (Response Due to Temparature
Variation)
Slide Nr. 19
-50 -45 -40 -35 -30 -25 -20
0
0.2
0.4
0.6
0.8
1
Vout
/V
300 K
315 K
330 K
345 K
360 K
-50 -45 -40 -35 -30 -25 -20
10
-4
10
-2
10
0
Vout
/V
300 K
315 K
330 K
345 K
360 K

Modification on Power Detector
Slide Nr. 20

Necessity of Op-Amp Design
 In order to provide logarithmic difference of the
detector stages.
 Delivers a linear in dB output response with respect to
the incident signal power.
 Buffer amplifier to isolate stages of the detector.
 Normalizes and scales the overall output.
Slide Nr. 21

Proposed Op-Amp for this Work
Slide Nr. 22
 Topology: Two
stage cascode
operational amplifier.
 Gain: one order
higher than the two
stage operational
amplifier gain.

 First stage of the
op-amp.
 The differential
inputs and current
mirror loads are
cascoded in order
to increase gain.
Slide Nr. 23

 Second stage
transistors.
 Consists of n-
channel
common-source
transistor M5 and
a p-channel
common-source
load M8.
Slide Nr. 24

 Bias currents:
Ibias = 24 µA
IG = 6 µA
 Compensation
capacitance:
CC =25 fF
 CC provides
stability to the op-
amp.
 VSS = 0 V
Slide Nr. 25

Bode Plot
Phase margin:
180 – 135 = 45 deg
Slide Nr. 26
10
0
10
2
10
5
10
7
10
10
-50
-25
0
25
50
75
Frequency f / GHz
Openloopgain/dB
10
0
10
2
10
5
10
7
10
10
-720
-630
-540
-450
-360
-270
-180
-90
0
90
Frequency f / GHz
PhaseT(j)/deg
0 dB Gain
-135 deg

Overall Design of the Power Detector
Input Impedance
matching section
Buffer stage
Logarithmic
Amplifier
Instrumentation Amplifier with
Offset correction
Slide Nr. 27

Input Impedance Matching
 Dual Band Impedance
matching
 TLshunt and Cseries forms
Low Band Matching
Network.
 TLseries and Cshunt forms
High Band Matching
Network.
Slide Nr. 28

Input Impedance Matching Network (results)
Slide Nr. 29

Logarithmic Amplifier
 Implemented after the
detector circuit in order
to provide linear in dB
response with respect to
input signal.
 A buffer stage utilized
in between these stages
for isolation purpose.























LCQ
rs
TEB
RI
RI
dB
VVV
.
.
)(
ln.
0
0
Slide Nr. 30

Logarithmic Amplifier Response
 A DC offset of around
550 mV can be seen which
requires correction.
 Shows a very linear
response.
 A difference amplifier is
necessary in order to
subtract the signals.
 Following stage:
Instrumentation amplifier
in stead of difference
amplifier
-50 -45 -40 -35 -30 -25 -20
550
600
650
700
750
(V
B
-V
E
)/mV
Slide Nr. 31

Instrumentation Amplifier
 Consists of an input
buffer stage and followed
by a differential amplifier
stage.
 Provides higher gain
than a difference
amplifier.
 If Rf=Rg and
Rin1=Rin2=Rin, then the
output can be calculated
by following equation:
  














in
f
gain
f
EBout
R
R
R
R
VVV
1
1
Slide Nr. 32

Instrumentation Amplifier (Normalization)
 But still requires
normalization.
 As the DC offset is
around 550 mV, a negative
DC signal is needed for
compensation.
 This is possible by
inserting an additional DC
signal at the inverting end.
 Following equation shows
the output voltage upon
offset correction:


















offset
f
CC
gain
f
BEout
R
R
V
R
R
VV .
.2
1.
1
Slide Nr. 33

Overall Response After Normalization
 The DC offset of the
output voltage has been
corrected.
 The response is scaled
upon amplification.
 The output voltage is
log-linearly proportional
to the input signal.
Slide Nr. 34

Directional Coupler
 Four port passive microwave
device.
 Used to isolate, separate or
combine RF signals.
 Application to this work:
measure the wave reflection
directly on the chip.
 Different types of
Directional Coupler:
Branchline coupler, Lange
Coupler, Coupled Line coupler.
Slide Nr. 35

Proposed Coupler Design
 Type: Coupled line
coupler.
 Simple design and easy
to construct.
 Symmetric design.
 Unit: micron
Slide Nr. 36
1 2
3 4

Response of the Directional Coupler
150 160 170 180 190 200 210 220 230 240 250
-30
-25
-20
-15
-10
-5
0
Frequency / GHz
S-parameter/dB
S11
S21
S31
S41
Design specification:
• Insertion loss: > -2 dB
• Return loss: < -10 dB
• Isolation: < -20 dB
• Bandwidth: 150 GHz to 250 GHz
Slide Nr. 37

Conclusion
 The power detector shows high linearity within the specified
dynamic range.
 Wideband operation is possible from 150 GHz to 250 GHz
range.
 The directional coupler met the desired specification.
 Simple, symmetric construction of both the power detector
and the directional coupler.
Slide Nr. 38

Thank you for your attention
Slide Nr. 39

Appendix

Operational Amplifier

Input differential
pair of p-channel
MOSFET .
Comprises of M1A
and M2A
transistors
respectively to
form Cascode
configuration.

n-channel MOS
Current mirror
load.
Similarly, M3A and
M4A common-
gate MOS
transistors used
to form Cascode.

Level-shift
transistors.
Make sures that,
second stage
input is driven a
signal whose DC
level is VGS3 above
ground

p-channel MOS
transistors.
Used for biasing
purpose.

Compensation
capacitor

Supply voltages.
VSS = 0 V as
negative supply is
not needed.

Buffer Amplifier
 Isolates two stages from
each other.
 Such as, detector stage and
the logarithmic amplifier stage.
 Shows high linearity between
the input and output.

Buffer Amplifier (relative difference)
%100
det
det



V
VV
RD
buffer

Op-Amp Performance Parameters
 Common mode input range: range of input voltage
for which all transistors at the fist stage operate in the
active or saturation region.
2 Vth3 +2 Vov3 -|Vth1|-|Vov1A|< VIC < VDD -|Vov1|-| Vth1|-| Vov7|
 Output Voltage Swing:
Vov5 ≤ Vout ≤ VDD - |Vov8|

Op-Amp Charateristics Curves
-20 -15 -10 -5 0 5 10 15 20
0
0.5
1
1.5
2
2.5
3
Differential input voltage / mV
Outputvoltage/V
-0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02
-100
-50
0
50
100
Differential Input Voltage / V
Gain/dB

Gain and Phase Margin (without compensation
capacitance)
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-75
-50
-25
0
25
50
75
X: 2.291e+008
Y: 40.11
Frequency f / GHz
OpenloopgainAv
X: 1.738e+009
Y: -0.03636
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-720
-630
-540
-450
-360
-270
-180
-90
0
90
X: 2.291e+008
Y: -180.2
Frequency f / GHz
PhaseT(j)/deg
X: 1.738e+009
Y: -313.7
Negative phase
margin= -134 deg
Gain margin= 40 dB

Gain and Phase Margin (with compensation
capacitance of different values)
25 fF compensation
capacitance gives a
phase margin of 45
deg
10
0
10
1
10
2
10
3
10
4
10
5
10
5
10
6
10
7
10
9
10
8
10
10
-75
-50
-25
0
25
50
75
Frequency f / GHz
OpenloopgainAv
1 fF
2 fF
5 fF
15 fF
30 fF
75 fF
175 fF
400 fF
1 pF
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-720
-540
-360
-180
0
90
Frequency f / GHz
PhaseT(j)/deg
1 fF
2 fF
5 fF
15 fF
30 fF
75 fF
175 fF
400 fF
1 pF

Process Corners
-10 -5 0 5 10
0
0.5
1
1.5
2
2.5
3
Differential Input / mV
OutputVoltage/V
tt
ss
ff
sf
fs
Offset compensation circuit is inevitable!

Op-Amp Circuit including Offset Compensation
Section

Response after offset compensation
-0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02
0
0.5
1
1.5
2
2.5
3
Differential input voltage / V
Outputvoltage/V
-10 mV
-7 mV
-5 mV
-3 mv
-1 mV
1 mV
3 mV
5 mV
7 mV
10 mV

Transistors aspect ratio and channel length
Transistor Aspect ratio Channel width [µm]
M1 3.22 2.00
M2 3.22 2.00
M3 1 0.40
M4 1 0.40
M5 4 2.00
M6 12.5 5.00
M7 12.5 5.00
M8 25 10.0
M9 1 0.40
M10 1 0.40
M11 1 0.40

Directional Coupler

Important Parameters
 Insertion Loss, IL: -20 log10 | S21| dB
 Return Loss, RL: -20 log10 | S11| dB
 Isolation, I: -20 log10 | S41| dB

Coupling vs Insertion Loss
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
8
10
12
14
16
18
Insertion Loss / dB
Coupling/dB
Coupling
/ dB
Insertion
Loss / dB
Power Ratio
(Through/Coupled)
3.0 3.0 50/50
6.0 1.2 75/25
10.0 0.46 90/10
20.0 0.04 99/1

Coupling and Insertion Loss with varying length
150 175 200 225 250
-30
-25
-20
-15
-10
Frequency / GHz
Coupling/dB
2.5 m
22 m
150 175 200 225 250
-15
-10
-5
0
Frequency / GHz
S-parameters/dB
Coupling (80 m)
Insertion Loss (80 m)
Coupling (55 m)
Insertion Loss (55 m)
Varying distance
between coupling lines
Varying the length of the
coupling section

Power Detector

ng13g2 bipolar transistor operating characteristics
Parameter Valid range
Collector current,
IC
< 30 mA
Base-emitter
voltage, VBE
0.65 to 0.94 V
Collector-emitter
voltage, VCE
0.4 to 2.0 V
Temperature 233K ... 400K

Temperature Variation Response of Modified Power
Detector
-50 -45 -40 -35 -30 -25 -20
10
0
10
-1
10
-2
10
-3
DifferenceVoltage/V
300 K
315 K
330 K
345 K
360 K
-50 -45 -40 -35 -30 -25 -20
10
-2
10
-1
10
0
Error/dB
315 K
330 K
345 K
360 K

Importance of impedance matching network
-50 -45 -40 -35 -30 -25 -20
0
0.2
0.4
0.6
0.8
1
1.2
DifferenceVoltage/V
Without impedance matching
With impedance matching

Temperature Dependence on Collector Current
300 310 320 330 340 350 360
10
20
30
40
50
60
70
Temperature / K
IC
/A
Without temperature stability
With temperature stability

Inductance and Q-factor

Impedance Matching Network
Passive Devices Conection Type Length or Size Equivalent
Inductance
Transmission
Lines
Series 165 µm 210 pH
Shunt 35 µm 17 pH
Capacitors Series 110 fF -
Shunt 50 fF -

Frequency response of the detector
-50 -45 -40 -35 -30 -25 -20
0
0.2
0.4
0.6
0.8
1
1.2
Vref
-Vdet
/V
150 GHz
175 GHz
200 GHz
225 GHz
250 GHz
-50 -45 -40 -35 -30 -25 -20
10
-2
10
0
Vref
-V
det
/V
150 GHz
175 GHz
200 GHz
225 GHz
250 GHz

Comparison with Meyer Detector
-50 -45 -40 -35 -30 -25 -20
10
-2
10
0
10
2
10
4
V
ref
-V
det
/mV
Meyer Detector
Proposed Detector

Comparison of Theoretical and Simulation Result
-50 -45 -40 -35 -30 -25 -20
0
0.2
0.4
0.6
0.8
1
Vref
-Vdet
/V
Theoretical Solution
Simulation Result
-50 -45 -40 -35 -30 -25 -20
10
-2
10
0
Vref
-V
det
/V
Simulation Result

Comparison of Theoretical and Simulation Result
-50 -45 -40 -35 -30 -25 -20
0.6
0.8
1
1.2
VBE
/V
Simulation Result

Process Corners and Detector Response
-50 -45 -40 -35 -30 -25 -20
0
0.5
1
1.5
Vref
-Vdet
/V
Typical
Worst case
Best case

Overall PD Device Values
Device Value
Rd 50 kΩ
Rr 50 kΩ
Rin 50 kΩ
Rg 17.5 kΩ
Rf 50 kΩ
Roffset 30 kΩ
Rf1 25 kΩ
Rgain 10 kΩ
RB1 50 kΩ
RB3 75 kΩ
RL1 32 kΩ
CB1 50 fF
C01 20 fF
VCC 2 V

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