FPGA Based Design of 32 Tap Band Pass FIR Filter Using Multiplier- Less Techniques

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 10 Issue: 12 | Dec 2023 www.irjet.net p-ISSN: 2395-0072
© 2023, IRJET | Impact Factor value: 8.226 | ISO 9001:2008 Certified Journal | Page 362
Amit Kumar Rana1, Nirbhay Kumar Singh2
1ME Student, Department of ECE, NITTTR Chandigarh, India
2ME Student, Department of ECE, NITTTR Chandigarh, India
---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - This paper deals with theimplementationofa 32
tap multiplier less band-pass FIR filter for digital signal
processing applications. The transposed architecture is
employed to design this FIR filter on a field-programmable-
gate-array (FPGA) using Spartan 3E, xc3s1200efg320-5, and
Virtex 4, xc4vfx20ff672-10 chips from Xilinx Inc. The VHSIC
Hardware Description Language (VHDL) is used fordesigning
this FIR filter. The main aim of this paper is to give a
comparison between Spartan 3E and Virtex 4 on the basis of
hardware utilization by a band-pass FIR filter. Here, the FIR
filter is implemented using the Equiripple method as it meets
the specifications with less complexity. Canonical SignedDigit
(CSD) and Factored- Canonical Signed Digit (FCSD)
representations are usedtorepresentthefiltercoefficientsand
it is observed that the FIR filter with FCSD representation
reduces the delay and area of the FIR filter. Simulation results
show that the 32 tap multiplier less FIR filterusingtheVirtex4
chip is 48.40% faster than the Spartan3E chip for the given
specifications.
Key Words: FIR filter; FPGA; VHDL; Filter coefficient; CSD;
FCSD.
1. INTRODUCTION
Digital signal processing is the analysis, interpretation,
and manipulation of real-word signals like audio, video,
voice, pressure, temperature, etc. Digital signal processing
techniques are used in various applications, like multimedia
and communication. A basic aspect of digital signal
processing is filtering. Filtering is a technique that is used to
modify the frequency properties of the input signal to meet
the design requirements. Filters are mostly used in
applications like noise reduction, image processing,
biomedical signal processing, video processing, audio
processing, and the analysis of financial and economic data
[1]. Filters are of two types: digital and analog filters. In
applications that require flexibility and programmability,
analog filters can be replaced with digital filters. Digital
filters transform the digital representations of the analog
signal to eliminate noise from the signal. A digital filter can
be designed using either infinite impulse response (IIR) or
finite impulse response (FIR) methods [2, 3]. The design of
the FIR filter is chosen because it is stable, simple to
implement, and has linear phase.
DSP applications require large-order FIR filters.
However, due to the multiplicity of calculations, the
complexity increases as the filter order increases. For an
efficient digital filter, the order of the FIR filter must be as
small as possible. There are basically three methods for
designing FIR filters: the window method, optimal filter
design method, and the frequency sampling technique.In all
three methods, optimal filter design methods are the best
methods to find the optimal solution in order to reduce
complexity [4]. There are basicallytwodesignenvironments
for the implementation of digital FIR filters: field-
programmable gate array (FPGA)-based and digital signal
processor–based. The FPGAs are the best choice for the
hardware design of DSP applications,andparticularlydigital
filters [2, 5]. The FPGAs provide flexibility in design and
hardware parallelism for high-speed applications.
The main elements of digital FIR filter design on FPGAs
are the register banks. The register banks are used to store
the samples of the signal, multipliersformultiplicationof the
signal samples to filter coefficients, and an adder to
implement addition operations. Although, design and
implementation of the digital FIR filters are easy, they are
expensive due to their large order and require more
memory. In digital circuits,thedesignmultiplier block canbe
replaced by using either canonical signed digit (CSD) or
factored-canonical signed digit (FCSD) representation.
Canonical singed digit and Factored: Canonical signeddigit
representation are used for representing the filter
coefficients in order to reduce the area, delay, and design
complexity of the FIR filters. The effect of coefficient
symmetry and replacing the multiplierblocksbyshifting and
addition operations are evaluated. It is important to select
the proper design approach for the specific applications.FIR
filters have two structures: directformandtransposedform.
In direct-form structures, filter coefficients multiply the
signal samples and are combined in an adder block. A
modification over direct form structure is called transposed
form structure, and it is employed for filter design. In this
work, the design and implementation of a digital band-pass
FIR filter on Spartan 3E, xc3s1200efg320-5, and Virtex 4,
xc4vfx20ff672-10, are considered. This digital filter is used
as a test bench to evaluate the algorithm’s performance for
different applications, such as radio communication [6, 7].
This paper is presented in this way: Section I presentsan
introduction to this work; Section II consists of an overview
of the digital FIR filter; the design simulation of the FIR filter
FPGA Based Design of 32 Tap Band Pass FIR Filter Using Multiplier-
Less Techniques

is presented in Section III; Section IV describes FPGA
synthesis; and finally, Section V concludes this paper.
2. DIGITAL FIR FILTER
A digital filter is a type of digital system that filters
discrete time signals [8]. A digital filter is an algorithm that
can be implemented in software or hardware, and operates
on digital input signals, and also produces digital output
signals. It can be represented by a block diagram as shownin
Fig. 1 [2].
X [n] Y [n]
Fig. 1. Basic block diagram of Digital filter
Digital filters are the main category of linear time-
invariant DSP systems, which are implemented for
modification of the frequency characteristics of the input
signal to meet design criteria. Digital filters have various
advantages that are not present in the analog filters,
examples includes excellent linear phase response,
performance that does not change with environment
changes, and tunable frequency response when designed
with a programmable processor using adaptive filters.
Adaptive filters can be used to filter multiple channels or
inputs without the need to reproduce the hardware and can
be operated over a wide range of frequencies. The steps for
designing a digital filter are illustrated in Fig. 2 [4, 9].
Fig. 2. Steps for FIR filter design
The digitalFIR filters withconstant coefficientsarelinear
time-invariant filters. The output of an N-order digital FIR
filter involves a convolution operation that could be written
as equation [6]:
Y[n] =H[n]*X[n] (1)
Another nameforFIRfiltersisnon-recursivedigitalfilters
because these filters do not have feedback. The response of
the FIR filter can be represented as:
Y[n] = H[k] X [n-k] (2)
Where
H[k] represents the coefficients of filter.
N represents the length of the FIR filter.
Basically, FIR filters are very useful for various electronic
applications where a true linear phase is required over the
whole range of frequencies [4]. The implementation of FIR
filters is a challenging task due to time delays, area, and
power in the digital circuit design. Therefore, different
architectures are shown in the literature; these are mainly of
two types: direct form and transposed form structures. The
direct-form realization of the FIR filter is shown in Fig. 3. A
modification of the direct structureis known as a transposed
structure, as shown in Fig. 4. In a transposed structure, the
sameinput signal is multiplied by various coefficients.Inthis
work, transposed structure is used in order to reduce delay
and area as compared to direct structure [2, 15].
X[n]
H[0] H[1] H[2] H[N]
Y[n]
Fig. 3. Direct form of FIR filter
X[n]
H[N] H[2] H[1] H[0]
Y[n]
Fig. 4. Transposed form of FIR filter
Factored-Canonical Signed Digit (FCSD) representationis
a modified form of Canonical Signed Digit (CSD)
representation. FCSD representation replaces multiplication
H [n]
Digital Filter
Star
t
Performance Specification
Coefficients Calculation
Structure Realization
Analyze finite word length
End
Implementation of H/W or
S/W
D3
D2
D1
D0
+
D0 +
D1 +
+
D2

operations with addition and shift operations on the basis of
a prime factor of coefficients. FCSD is the combination of
factorization and Canonical Signed Digit representation of
filter coefficients, which reduces the number of adders and
also the cost of hardware. It gives a greater reduction in filter
area, but there is a decrease in clock speed. The major
drawback of this algorithm is that it increases the delay. The
FCSD algorithm makes a trade-off between convergence
calculation and complexity [2]. This example shows the
comparison between CSD and factored-CSD algorithms:
w = 105 * u
= (1101001) * u % 105 in binary representation
= (101’01001) * u % 105 in signed digit representation
= (128- 32+8+1) * u
= (u << 7) –(u << 5) + (u << 3) + u
Cost of Canonical Signed Digit is 3 adders
w = 105 * u
= (7*15) * u
= (u << 3– u) * ( u << 4 – u )
Cost of Factored- Canonical Signed Digit (FCSD) is 2 adders
Therefore, the above example concludes that the number
of adders can be reduced by using the FCSD technique as
compared to CSD.
3. DESIGN SIMULATIONS
There are basically three methods for designing FIR
filters: the window method, the optimal filter design
methods, and the frequency sampling technique. In all three
methods, optimal filter design methods are the best method
to find the optimal solution [4].
Optimal filter design methods are of two types: oneisthe
equirripple method, and the other is the discrete least
squares method. The equirripple method is also called the
Chebyshev approach method or Remez method. In this
method, the mathematical process is very complex, which is
difficult to realize, but the main advantage is that it has a
lower order as compared to the least squares method, and
this method can control the frequency edge more accurately
[10].
The design of the FIR filter using the window method
includes truncating of infinite time duration impulse
response by using a set of time-limited weighted window
functions. This method results in a very low convergence of
the truncated series, especially in the vicinity of
discontinuities, which makes the method unsatisfactory for
approximating digital filters [11]. The aim of the window
method is that the ideal frequency response of the desired
filter is 1 for pass band frequencies, and for stop band
frequencies, it must be 0, after which the discrete Fourier
transform (DFT) of the ideal frequency response is takenfor
retrieving the filter impulse response. To design a finite
impulse response filter, the filter coefficients must be
restrained in number by multiplying a finite width window
function [12]. Some of the windows commonly used are
Kaiser windows, Rectangular windows, Tukey windows,
Gaussian windows, Hann windows, and Hammingwindows.
But in this work, the Equiripple method isusedfordesigning
the FIR filter to reduce the design complexity [15].
The required parameters for the implementation of a 32
tap multiplier less band-pass FIR filter using the Equiripple
method are the filter length, first stopband frequency, first
passband frequency, second passband frequency, second
stopband frequency and sampling frequency. In this
simulation, the filter length is 32 tap, first stopband
frequency is 7200Hz, and first passband frequency is
9600Hz, second passband frequency is 12000Hz, second
stopband frequency is 14400Hz and sampling frequency is
48000Hz. The design specificationsofa multiplierlessband-
pass FIR filter are given in Table I:
Table 1. Design Specifications of Band-Pass Filter
Filter Parameter Value
Filter Length 32 Tap
First Stopband
Frequency
7200Hz
First Passband
Frequency
9600Hz
Second Passband
Frequency
12000Hz
Second Stopband
Frequency
14400Hz
Sampling Frequency 48000Hz
The fixed-point method is considered in this work
because it reduces computational complexity and increases
speed performance, but the major drawback of this method
is that it reduces accuracy. As the magnitude response ofthe
band-pass multiplier less FIR filter is shown in Fig. 5, the
passband ripple and stopband attenuation have some
fluctuations as compared to the floating point method.
0 5 10 15 20
-70
-60
-50
-40
-30
-20
-10
0
Frequency (kHz)
Magnitude
(dB)
MagnitudeResponse(dB)
BandpassEquiripple:Quantized
BandpassEquiripple:Reference
Fig. 5. Magnitude Response of Band Pass FIR Filter
The phase response of a band-pass FIR filter is shown in
Fig. 6. As FIR filters have linear phase, the graph shows the
linear phase characteristics up to stopband frequency.

Fig. 6. Phase Response of Band Pass FIR Filter
The magnitude and phase response of a band-pass FIR
filter in a single graph are shown in Fig. 7.
0 5 10 15 20
-70
-60
-50
-40
-30
-20
-10
0
Frequency (kHz)
Magnitude
(dB)
MagnitudeResponse(dB) andPhaseResponse
-12.02
-9.7333
-7.4467
-5.16
-2.8733
-0.5866
1.7
3.9867
Phase
(radians)
Bandpass Equiripple:QuantizedMagnitude
Bandpass Equiripple:ReferenceMagnitude
Bandpass Equiripple:QuantizedPhase
Bandpass Equiripple:ReferencePhase
Fig. 7. Magnitude and Phase Response of the band pass
FIR Filter
The pole–zero plot of FIR filter using the Equiripple
method is shown in Fig. 8.
.
-5 -4 -3 -2 -1 0 1 2 3 4
-1
-0.5
0
0.5
1
RealPart
Imaginary
Part
32
32
Pole/ZeroPlot
Bandpass Equiripple:QuantizedZero
Bandpass Equiripple:ReferenceZero
Bandpass Equiripple:QuantizedPole
Bandpass Equiripple:ReferencePole
Fig. 8. Pole –Zero Plot of the Equiripple FIR Filter
4. FPGA SYNTHESIS
The multiplier less FIR filter has been designed in
MATLAB. After that, it is further simulated on theFPGAusing
Spartan 3E, xc3s1200efg320-5, and Virtex 4, xc4vfx20ff672-
10 chips. The simulation results of band pass FIR filter using
Spartan 3E, and Virtex 4 are shown in Figs. 9, and 10
respectively. The filter responses on the FPGA are the same
as on MATLAB.
Fig. 9. FIR filter input-output using Xilinx Spartan 3E
Fig. 10. FIR filter input-output using Xilinx Virtex 4
The characteristics table of Spartan 3E and Virtex 4 chips
is given in Table II, and III respectively.Thesetablesshowthe
availabilityand utilization oflogic by Spartan 3Eand Virtex4
chips.
Table 2. The Characteristics Table of Spartan 3E
Parameters CSD FCSD
Slices 1515 1463
Flip Flop 408 408
LUTs 2651 2547
Table 3. The Characteristics Table of Virtex 4
Parameters CSD FCSD
Slices 1505 1452
Flip Flop 402 402
LUTs 2621 2512
A 32 tap multiplier lessband-passFIRfilterusingCSDand
FCSD has been implementedonSpartan3EandVirtex4chips.

VHDL is used for designing this filter. Table II, and III show
that the band-pass FIR filter using CSD representation,
consume 1515 slices, 408 flip flops, 2651 LUTs and FCSD
representation consume 1463 slices, 408 flip flops, 2547
LUTs on Spartan 3E and on the other hand, on Virtex 4, the
band-passFIR filter usingCSDrepresentation,consume1505
slices, 402 flip flops, 2621 LUTs and FCSD representation
consume 1452 slices, 407 flipflops,2512LUTs.Thereforethe
FCSD representation consume less slices and LUTs as
compare to CSD representation. Here, Spartan 3E and Virtex
4 have minimum periods of 66.696ns and 44.942ns,
respectively. Hence, Spartan 3E has 48.40% more delay as
compared to Virtex 4.
5. CONCLUSIONS
In this work, a design analysis of a 32 tap multiplier less
digital band-pass FIR filter on an FPGA is presented. The
transposed architecture is used to design this band pass FIR
filter on MATLAB. After being implemented in MATLAB, the
CSD and FCSD based FIR filter is further simulated on the
FPGA using Spartan 3E and Virtex 4 chips. Here, FCSD
representation is adopted to represent the filter coefficients
as it reduces 3.55% slices and 4.08% LUTs on Spartan 3E
and 3.65% slices and 4.33% LUTs on Virtex 4 as compare to
CSD representation. Simulation results show that the
multiplier less FIR filter using Spartan 3E and Virtex 4 is
operated at a maximum frequency of 14.993MHz and
22.251MHz, respectively. Therefore, it is concluded that
Virtex 4, xc4vfx20ff672-10, is 48.40% faster as compared to
Spartan 3E, xc3s1200efg320-5.
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